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Comparing three online evolvable hardware implementations of a classification system

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Abstract

In this paper, we present three implementations of an online evolvable hardware classifier of sonar signals on a 28 nm process technology FPGA, and compare their features using the most relevant metrics in the design of hardware: area, timing, power consumption, energy consumption, and performance. The three implementations are: one full-hardware implementation in which all the modules of the evolvable hardware system, the evaluation module and the Evolutionary Algorithm have been implemented on the ZedBoard™ Zynq® Evaluation Kit (XC7-Z020 ELQ484-1); and two hardware/software implementations in which the Evolutionary Algorithm has been implemented in software and run on two different processors: Zynq® XC7-Z020 and MicroBlaze™. Additionally, each processor-based implementation has been tested at several processor speeds. The results prove that the full-hardware implementation always performs better than the hardware/software implementations by a considerable margin: up to \(\times \,7.74\) faster than MicroBlaze, between \(\times \,1.39\) and \(\times \,2.11\) faster that Zynq, and \(\times \,0.198\) lower power consumption. However, the hardware/software implementations have the advantage of being more flexible for testing different options during the design phase. These figures can be used as a guideline to determine the best use for each kind of implementation.

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Notes

  1. See Sect. 5 for a detailed description of the circuit.

  2. When \(p=0.5\) and n is very large, usually \(n \ge 30\), as in this case, the binomial distribution can be approximated by the normal distribution. So, in this case the number of mutations, \(n \sim N\left( 45, 22.5 \right)\).

  3. 2.5 DMIPS/MHz per CPU, up to 667 MHz, with L1 and L2 caches, and single and double precision floating point units.

  4. This processor can be instantiated in any Xilinx FPGA in any number, provided that there are enough resources in the FPGA.

  5. These figures are not available in Vivado 2014.2.

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Acknowledgements

This work is supported by the Spanish Research Grant TIN2015-65460-C2, and NILS Grant ABEL-IM-2014A.

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Authors and Affiliations

  1. Dpto. Arquitectura de Computadores, Universidad Complutense de Madrid, C/ Profesor José García Santesmases, 28040, Madrid, Spain

    Oscar Garnica

  2. Department of Informatics, University of Oslo, 0316, Oslo, Norway

    Kyrre Glette & Jim Torresen

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  1. Oscar Garnica
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  2. Kyrre Glette
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  3. Jim Torresen
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Correspondence to Oscar Garnica.

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Garnica, O., Glette, K. & Torresen, J. Comparing three online evolvable hardware implementations of a classification system. Genet Program Evolvable Mach 19, 211–234 (2018). https://doi.org/10.1007/s10710-017-9312-1

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