Skip to main content
SpringerLink
Log in

Systematic design of CNTFET based OTA and Op amp using gm/ID technique

  • Published:
Analog Integrated Circuits and Signal Processing Aims and scope Submit manuscript

Abstract

This paper presents for the first time all the steps required in optimal design of carbon nano tube field effect transistor (CNTFET) based single stage operational transconductance amplifier and two stage operational amplifier using transconductance to drain current ratio (\(g_{m}/I_{D}\)) technique for low voltage and low power applications. As square law model failed to produce exact behavior in short channel devices as well as moderate and weak inversion behavior of the transistor. Therefore, \(g_{m} / I_{D}\) methodology is used to design analog circuits in short channel devices to overcome the shortcomings of square law models. Also, the design using \(g_{m} / I_{D}\) methodology does not consider the inversion region of the transistor like square law equations. The \(g_{m} / I_{D}\) methodology is a well-established technique for CMOS analog IC design but CMOS has continuous width while CNTFET width is discrete and depends on different parameters like number of tubes, pitch and diameter of the carbon nanotube. Therefore, there is a need of a design methodology to design analog circuits using CNTFETs. Circuit performance has been investigated extensively using HSPICE simulation.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12

Similar content being viewed by others

References

  1. Silveira, F., Flandre, D., & Jespers, P. G. A. (1996). A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower ota. IEEE Journal of Solid-State Circuits, 31(9), 1314–1319.

    Article  Google Scholar 

  2. Flandre, D., Viviani, A., Eggermont, J.-P., Gentinne, B., & Jespers, P. G. A. (1997). Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology. IEEE Journal of Solid-State Circuits, 32(7), 1006–1012.

    Article  Google Scholar 

  3. Akbari, M., & Hashemipour, O. (2015). Design and analysis of folded cascode otas using gm/ID methodology based on flicker noise reduction. Analog Integrated Circuits and Signal Processing, 83(3), 343–352.

    Article  Google Scholar 

  4. Seth, S., & Murmann, B. (2013). Settling time and noise optimization of a three-stage operational transconductance amplifier. IEEE Transactions on Circuits and Systems I: Regular Papers, 60(5), 1168–1174.

    Article  MathSciNet  Google Scholar 

  5. Samiei, M., & Hashemipour, O. (2018). Design of active inductor-based current-controlled oscillators using gm/id methodology. AEU-International Journal of Electronics and Communications, 87, 1–9.

    Article  Google Scholar 

  6. Eldeeb, M. A., Ghallab, Y. H., Ismail, Y., & Elghitani, H. (2017). Low-voltage subthreshold CMOS current mode circuits: Design and applications. AEU-International Journal of Electronics and Communications, 82, 251–264.

    Article  Google Scholar 

  7. Dolatshahi, M., Hashemipour, O., & Navi, K. (2012). A new systematic design approach for low-power analog integrated circuits. AEU-International Journal of Electronics and Communications, 66(5), 384–389.

    Article  Google Scholar 

  8. Jespers, P. (2009). The gm/ID methodology, a sizing tool for low-voltage analog CMOS circuits: The semi-empirical and compact model approaches. New York: Springer.

    Google Scholar 

  9. Konishi, T., Inazu, K., Lee, J. G., Natsui, M., Masui, S., & Murmann, B. (2011). Design optimization of high-speed and low-power operational transconductance amplifier using gm/ID lookup table methodology. IEICE transactions on electronics, 94(3), 334–345.

    Article  Google Scholar 

  10. Moghadami, S., JalaliBidgoli, F., & Ardalan, S. (2016). Systematic approaches for analysis and design of terahertz and millimeter-wave integrated circuits using carbon nanotube fets. Canadian Journal of Electrical and Computer Engineering, 39(2), 92–102.

    Article  Google Scholar 

  11. Barboni, L., Siniscalchi, M., & Sensale-Rodriguez, B. (2015). TFET-based circuit design using the transconductance generation efficiency gm/ID method. IEEE Journal of the Electron Devices Society, 3(3), 208–216.

    Article  Google Scholar 

  12. da Luiz Antonio, S. Jr., Pavanato, L. R., Severo, T. P., & Girardi, A. (2013). A systematic methodology for analog design of operational amplifiers composed by nanodevices. In Microelectronics students forum (SFORUM), 2013.

  13. Possani, T., Pavanato, L. R., da Silva Jr, L. A., & Girardi A. (2013). Application of gm/id methodology for analog design using nanometer-scale devices. In XXVIII —South symposium of microelectronics—SIM, 2013.

  14. Possani, T., Severo, L. C., & Girardi, A. (2012). Automatic design of micropower carbon nanotube operational transconductance amplifiers. In SIM-south symposium on microelectronics.

  15. Possani, T., & Girardi, A.(2011). Design methodology of analog integrated circuits using carbon nanotube transistors. In Student forum (SFORUM), 2011.

  16. Carbon nanotube field effect transistors (CNFET) hspice model v. 2.2.1, Stanford University. http://nano.stanford.edu/models.php. Accessed June 6, 2018.

  17. Razavi, B. (2005). Design of analog CMOS integrated circuits. New York: McGraw-Hill Education.

    Google Scholar 

  18. Iijima, S. (1991). Helical microtubules of graphitic carbon. Nature, 354(6348), 56.

    Article  Google Scholar 

  19. McEuen, P. L., Fuhrer, M. S., & Park, H. (2002). Single-walled carbon nanotube electronics. IEEE Transactions on Nanotechnology, 99(1), 78–85.

    Article  Google Scholar 

  20. Wilder, J. W. G., Venema, L. C., Rinzler, A. G., Smalley, R. E., & Dekker, C. (1998). Electronic structure of atomically resolved carbon nanotubes. Nature, 391(6662), 59.

    Article  Google Scholar 

  21. Avouris, P., Hertel, T., Martel, R., Schmidt, T. H. R. H. S., Shea, H. R., & Walkup, R. E. (1999). Carbon nanotubes: Nanomechanics, manipulation, and electronic devices. Applied Surface Science, 141(3–4), 201–209.

    Article  Google Scholar 

  22. Wong, H.-S. P. (2002). Beyond the conventional transistor. IBM Journal of Research and Development, 46(2.3), 133–168.

    Article  Google Scholar 

  23. Imran, A., Hasan, M., Islam, A., & Abbasi, S. A. (2012). Optimized design of a 32-nm CNFET-based low-power ultrawideband CCII. IEEE Transactions on Nanotechnology, 11(6), 1100–1109.

    Article  Google Scholar 

  24. Deng, J., & Wong, H.-S. P. (2007). A compact spice model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: Model of the intrinsic channel region. IEEE Transactions on Electron Devices, 54(12), 3186–3194.

    Article  Google Scholar 

  25. Deng, J., & Wong, H.-S. P. (2007). A compact spice model for carbon-nanotube field-effect transistors including nonidealities and its application—Part II: Full device model and circuit performance benchmarking. IEEE Transactions on Electron Devices, 54(12), 3195–3205.

    Article  Google Scholar 

  26. Cen, M., Song, S., & Cai, C. (2017). A high performance CNFET-based operational transconductance amplifier and its applications. Analog Integrated Circuits and Signal Processing, 91(3), 463–472.

    Article  Google Scholar 

  27. Prakash, P., Sundaram, K. M., & Bennet, M. A. (2018). A review on carbon nanotube field effect transistors (CNTFETS) for ultra-low power applications. Renewable and Sustainable Energy Reviews, 89, 194–203.

    Article  Google Scholar 

  28. Sayed, S. I., Abutaleb, M. M., & Nossair, Z. B. (2016). Optimization of cnfet parameters for high performance digital circuits. Advances in Materials Science and Engineering, 2016, 1–9.

    Article  Google Scholar 

  29. Kshirsagar, C., Li, H., Kopley, T. E., & Banerjee, K. (2008). Accurate intrinsic gate capacitance model for carbon nanotube-array based fets considering screening effect. IEEE Electron Device Letters, 29(12), 1408–1411.

    Article  Google Scholar 

  30. Weste, N. H. E., & Harris, D. (2015). CMOS VLSI design: A circuits and systems perspective. London: Pearson Education India.

    Google Scholar 

  31. Baker, R. J. (2008). CMOS: Circuit design, layout, and simulation (Vol. 1). New York: Wiley.

    Book  Google Scholar 

  32. Allen, P. E., & Holberg, D. R. (2002). CMOS analog circuit design. Oxford: Oxford University Press.

    Google Scholar 

Download references

Acknowledgements

This work was supported by the DSA grant of the UGC and TEQIP-III scheme of MHRD, Government of India.

Author information

Authors and Affiliations

  1. Department of Electronics Engineering, Z. H. College of Engineering and Technology, Aligarh Muslim University, Aligarh, India

    Mohd Yasir & Naushad Alam

Authors
  1. Mohd Yasir
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Naushad Alam
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Mohd Yasir.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Yasir, M., Alam, N. Systematic design of CNTFET based OTA and Op amp using gm/ID technique. Analog Integr Circ Sig Process 102, 293–307 (2020). https://doi.org/10.1007/s10470-019-01492-0

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10470-019-01492-0

Keywords

Search

Navigation