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Implementing bitonic sorting on optical network-on-chip with bus topology

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Abstract

Optical network-on-chip (ONoC) is a new designing of multi-processor system-on-chip. On the one hand, global bus is a simple and common logical topology for ONoC. On the other hand, the parallel formulation of bitonic sorting has lower time complexity than the sequential implementation of bitonic sorting. Thus, it is meaningful to study the parallel implementation for bitonic sorting on bus ONoC. Different wavelengths are used to achieve the parallel processing for bitonic sorting on bus ONoC. The wavelength assignment scheme for n elements bitonic sorting is proposed such that the number of wavelengths required is just n/2.

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Acknowledgements

The authors would like to express their gratitude to the editor and the anonymous referees for their valuable suggestions about this paper. This work was supported by National Natural Science Foundation of China (No. 61501406) and the Doctorate Foundation of Zhengzhou University of Light Industry (No. 2014BSJJ026).

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Authors and Affiliations

  1. School of Computer and Communication Engineering, Zhengzhou University of Light Industry, Zhengzhou, 450002, People’s Republic of China

    Jing Zhang, Weiwei Zhang, Junling Yuan & Hua Wang

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  1. Jing Zhang
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  2. Weiwei Zhang
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  3. Junling Yuan
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  4. Hua Wang
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Correspondence to Jing Zhang.

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Zhang, J., Zhang, W., Yuan, J. et al. Implementing bitonic sorting on optical network-on-chip with bus topology. Photon Netw Commun 39, 129–134 (2020). https://doi.org/10.1007/s11107-019-00874-8

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  • DOI: https://doi.org/10.1007/s11107-019-00874-8

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