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Device physics and design of hetero-gate dielectric tunnel field-effect transistors with different low/high-k EOT ratios

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Abstract

The hetero-gate dielectric (HGD) structure was recently experimentally demonstrated to enhance the electrical performance of tunnel field-effect transistors (TFETs). This study examined the mechanisms underlying the HGD structure functioning and investigated the design of the structure to enhance the electrical characteristics of TFETs with different ratios of low- and high-k equivalent oxide thicknesses (EOT). The on-current enhancement by the source-side dielectric heterojunction, which directly modulates the on-state tunnel width, was much larger than that by the drain-side dielectric heterojunction, which indirectly affects the on-current by modulating the subthreshold tunnel width. The subthreshold swing is improved by the formation of a conduction band well near the source-channel junction. However, the swing improvement is limited by the hump effect when this local potential well approaches the source. The optimal design of the HGD structure and the maximal enhancement of on-current considerably depend on the EOT ratio of low- and high-k dielectrics. The on-current is most enhanced by the optimized HGD structure at a low/high-k EOT ratio of ten times, that is, approximately 160% of the on-current of the uniform high-k TFET counterpart. Due to the continuous trend of increasing the k-values or scaling EOTs, understanding the dependence of device physics and design on the low/high-k EOT ratio is crucial to optimize the performance of HGD-TFETs.

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Change history

  • 21 January 2020

    The correct name of the third author should be given as Huu-Duy Tran, not Huy-Duy Tran.

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Acknowledgements

This research is funded by Vietnam National Foundation for Science and Technology Development (NAFOSTED) under grant number 103.02–2018.309, by the Ministry of Education and Training of Vietnam and Dalat University under project code B2019-DLA-05. This work is also supported by the Ministry of Science and Technology and the National Center for High-Performance Computing of Taiwan.

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Authors and Affiliations

  1. Department of Electrical Engineering, National Chi Nan University, Nantou, 54561, Taiwan

    Chun-Hsing Shih

  2. Faculty of Physics and Nuclear Engineering, Dalat University, Dalat, Lam Dong, 670000, Vietnam

    Nguyen Dang Chien, Huy-Duy Tran & Phan Van Chuan

Authors
  1. Chun-Hsing Shih
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  2. Nguyen Dang Chien
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  3. Huy-Duy Tran
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  4. Phan Van Chuan
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Correspondence to Nguyen Dang Chien.

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Shih, CH., Chien, N.D., Tran, HD. et al. Device physics and design of hetero-gate dielectric tunnel field-effect transistors with different low/high-k EOT ratios. Appl. Phys. A 126, 66 (2020). https://doi.org/10.1007/s00339-019-3246-9

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