Abstract
We present a new noise shaping method and a dual-polarity calibration technique suited for successive approximation register type analog to digital converters (SAR–ADC). Noise is pushed to higher frequencies with the noise shaping by adding a switched capacitor. The SAR capacitor array mismatch has been compensated by the dual-polarity digital calibration with minimum circuit overhead. A proof-of-concept prototype SAR–ADC using the proposed techniques has been fabricated in a 0.5-μm standard CMOS technology. It achieves 67.7 dB SNDR at 62.5 kHz sampling frequency, while consuming 38.3 μW power with 1.8 V supply.
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Liu, W., Huang, P., & Chiu, Y. (2011). A 12-bit, 45MS/s, 3-mW redundant successive-approximation-register analog-to-digital converter with digital calibration. IEEE Journal of Solid-State Circuits, 46(11), 2661–2672.
McNeill, J., Coln, M. C. W., & Larivee, B. J. (2005). Split ADC architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC. IEEE Journal of Solid-State Circuits, 40(12), 2437–2445.
Baker, R. J. (2008). CMOS: circuit design, layout, and simulation (2nd edn., pp. 1010–1012). New Jersey: Wiley-IEEE.
Yoon, Y., Kim, J., Jang, T., & Cho, S. (2008). A time-based bandpass ADC using time-interleaved voltage-controlled oscillators. IEEE Transactions on Circuits and Systems I, 55(11), 3571–3581.
Pesenti, S., Clement, P., & Kayal, M. (2008). Reducing the number of comparators in multibit ∆∑ modulators. IEEE Transactions on Circuits and Systems I, 55(4), 1011–1022.
Naiknaware, R., Tang, H., & Fiez, T. S. (2000). Time-referenced single-path multi-bit ∆∑ ADC using a VCO-based quantizer. IEEE Transactions on Circuits and Systems II, 47(7), 596–602.
Maghari, N., & Moon, U. (2011). A third-order DT ∆∑ modulator using noise-shaped bidirectional single-slope quantizer. IEEE Journal of Solid-State Circuits, 46(12), 2882–2891.
Fredenburg, J., & Flynn, M. (2012). A 90 M/s 11 MHz bandwidth 62 dB SNDR noise-shaping SAR ADC. In International solid-state circuits conference (ISSCC), digest of tech. papers, pp. 468–469.
Kim, K. S., Kim, J., & Cho, S. H. (2010). nth-order multi-bit ∑∆ ADC using SAR quantiser. Electronics Letters, 46(19).
Razavi, B. (2000). Design of analog CMOS integrated circuits (1st edn., pp. 619–624). New York: McGraw-Hill.
Lee, H.-S., Hodges, D. A., & Gray, P. R. (1984). A self-calibrating 15 bit CMOS A/D converter. IEEE Journal of Solid-State Circuits, SSC-19(6), 813–819.
Li, J., & Moon, U. (2003). Background calibration techniques for multistage pipelined ADCs with digital redundancy. IEEE Transactions on Circuits and Systems II, 50(9), 531–538.
Yoshioka, M., Ishikawa, K., Takayama, T., & Tsukamoto, S. (2010). A 10-b 50-MS/s 820-μW SAR ADC with on-chip digital calibration. IEEE Transactions on Biomedical Circuits and Systems, 4(6), 410–416.
Chen, Y., Zhu, X., Tamura, H., Kibune, M., Tomita, Y., Hamada, T., et al. (2009). Split capacitor DAC mismatch calibration in successive approximation ADC (pp. 279–282). In IEEE custom integrated circuits conference.
Figueiredo, P. M., & Vital, J. C. (2006). Kickback noise reduction technique for CMOS latched comparators. IEEE Transactions on Circuits and Systems II, 53(7), 541–545.
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Park, H., Ghovanloo, M. A 13-bit noise shaping SAR–ADC with dual-polarity digital calibration. Analog Integr Circ Sig Process 75, 459–465 (2013). https://doi.org/10.1007/s10470-013-0050-x
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DOI: https://doi.org/10.1007/s10470-013-0050-x