Nanoelectromechanical (NEM) device has been regarded as one of the future switching devices due to its nearly infinite switching slope and zero off-state leakage current. However, it suffers from high pull-in voltage which causes high operation voltage. In this study , a sub-15 nm-thick Al-doped HfO2-based ferroelectric (FE) layer with a negative capacitance (NC) that can exceed the scalability limitation

• In this work we report on the integration of indium oxide (In2O3) nanoparticles (NPs) for Resistive Random Access Memory (RRAM) applications. This low-temperature integration process is fully compatible CMOS Back-End integration given a carefull selection of materials deposited by MOCVD and ALD. A detailed description of the process is provided together with AFM analysis performed on the indium oxide

This paper presents a generalized charge-based EKV MOSFET model that includes the effects of trapped charges in the bulk oxide and at the silicon/oxide interface. It is shown that in the presence of oxide- and interface-trapped charges, the mobile charge density can still be linearized but with respect to both the surface potential and the channel voltage. This enables us to derive closed-form expressions

We studied the mechanism of the proton-induced electrical degradation of AlGaN/GaN high electron mobility transistors (HEMTs) through 5-MeV proton irradiation. First, the AlGaN/GaN heterostructure was exposed to protons with a fluence of 1 × 1015 p/cm2 to investigate the relationship between the radiation-caused damage in the heterostructure and the electrical characteristics of HEMTs. The HEMTs fabricated

A physics-based compact model for phase-change random access memory (PcRAM) was proposed considering the ratio of vertical-to-lateral crystal growth rate (α) and it was incorporated into HSPICE via Verilog-A. The proposed model was verified by using the experimental results taken from the 256 × 256 cross-point (X-point) PcRAM cell array with the Ge2Sb2Te5 2z-nm technology node. The proposed compact

Herein, we investigated the effect of organic solvent drop-casting and solvent vapour annealing (SVA) on the surface morphology of copper phthalocyanine (CuPc) and its effect on the transistor performance and contact resistance in organic field effect transistors (OFETs). Organic solvents: acetone and isopropyl alcohol (IPA) are used for drop-casting and SVA treatment of CuPc film. The morphology,

In this paper, we demonstrate high-performance lateral AlGaN/GaN Schottky barrier diodes (SBD) on Si substrate with a recessed-anode structure. The optimized rapid etch process provides results in improving etching quality with a 0.26-nm roughness of the anode recessed surface. By using the high work function metal Pt as the Schottky electrode, a low turn-on voltage of 0.71 V is obtained with a high

In this paper, the experimental investigation on the electrical properties of silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT) after total-ionizing-dose (TID) irradiation is presented. We find that the TID irradiation reduces the threshold voltage (Vth), and increases the collector current (ICE) at the same gate voltage (Vg). The raising ICE is mainly attributed to the negative

This work investigates the transient current in the subthreshold region of a low-temperature polycrystalline silicon thin-film transistor (LTPS TFT) on a polyimide (PI) substrate. The measurement of this current shows an instability that is not seen in the device on a glass substrate; the instability appears as a current variation under constant voltage and overshoot or undershoot under external stress

In this paper, we propose a stochastic model for the resistive switching of ReRAM devices with 1T1R configuration. We work with the fact that the switching occurs in the narrowest zone of the conductive filament due to changes caused by the electric field. This active region is represented by a net of vertical connections, each one composed of three electrical elements: two of them are always low resistive

An accurate and efficient parasitic parameter extraction method is proposed for gallium nitride (GaN) high electron-mobility transistors (HEMTs). In this letter, a 19-element small signal equivalent circuit model is established to describe the characteristics of the device precisely. The simulation of the high frequency behavior is improved by introducing the series parasitic inductances into the cold

In this work, a continuous and symmetric trans-capacitance compact model for triple-gate junctionless MOSFETs is presented, valid in all regions of operation. Initially, the expressions of the gate, drain and source total charges are analytically derived based on a continuous and symmetric drain current compact model already developed. Then, the intrinsic capacitances are calculated via the differentiation

Charge stabilities and spin-based quantum bit (qubit) operations in Si double quantum dot (DQD) systems, whose confinement potentials are controlled with multiple gate electrodes, are theoretically studied with a multi-scale modeling approach that combines electronic structure simulations and a Thomas-Fermi method. Taking Si/SiGe heterostructures as the target of modeling, this work presents in-depth

We investigated the effect of growth temperature on the structural and electrical properties of InAlAs layers grown on InP (100) substrates by metalorganic chemical vapor deposition (MOCVD) method. Flat surface morphology of InAlAs layers with root mean square (RMS) surface roughness values below 0.4 nm were obtained at 500 ℃ and 660 ℃, while RMS surface roughness values of InAlAs layers grown in the

We report a comparative study of metamorphic InAs p-i-n photodetectors epitaxially grown on GaAs and Si by molecular beam epitaxy. Linearly graded InAlAs buffers were employed to bridge the high lattice mismatch between InAs and Si. Quantitative measurement for threading dislocation density (TDD) in the InAs layers grown on GaAs and Si has been performed using transmission electron microscopy and electron

Several methods of depositing pure boron (PureB) layers on silicon are examined with respect to their potential for fabricating advanced PureB (photo)diodes with back-end-of-line (BEOL) CMOS compatibility. PureB devices were fabricated in two different batch furnace chemical-vapor deposition (CVD) systems or by electron-beam-assisted physical-vapor deposition (EBPVD), and their electrical characteristics

InAs nanowires (NWs) were selectively grown on hole patterned InP (111)B substrate by Metal-Organic Chemical Vapor Deposition (MOCVD). This study reports the vertical growth behavior of InAs NWs transitioned at a certain height and its difference under various growth conditions. This certain height is referred as “critical height.” This is a boundary where both vertical and lateral growth occur. Under

We analyzed Incremental Step Pulse Programming (ISPP) slope degradation to improve the program efficiency of 3D NAND Flash memory using both measurement and simulation data. The simulation data are calibrated with the measurement data and they are in good agreement. The ISPP slope indicates program efficiency and its ideal value is 1. In reality, however, ISPP slope degradation (< 1) occurs in the

This paper describes device simulation studies of surface and buffer trapping effects on static I-V, output-admittance (Y22), and transient characteristics of AlGaN/GaN HEMTs. The TCAD simulation model considering surface donors at EC - 0.5 eV and buffer traps at EC - 0.47 eV have been used to quantitatively reproduce the measured DC, Y22 frequency dispersion, gate-lag (GL) and drain-lag (DL) transients

We observed abnormal threshold voltage (VT) shift in amorphous InGaZnO (a-IGZO) thin-film transistors under negative gate bias stress (NBS) after soaking them in H2O (pH 8). Before NBS, we soaked a-IGZO TFTs in H2O. During application of NBS, VT decreased by −0.43 V, then increased to nearly the initial value. We hypothesize that the electrical field that was applied during NBS caused some dissociation

Conventional Hall effect devices are designed to respond to a single magnetic field component in 3D space. However, if plastic encapsulated Hall effect devices in cubic crystals are exposed to poorly defined and unstable mechanical shear stress, small portions of unwanted, perpendicular magnetic field components will show up in the Hall output signals. Mathematically, any such crosstalk – may it originate

The built-in bipolar junction transistor of H-gate partially depleted SOI NMOS was characterized by measuring the common-emitter output curve and calculating the common-emitter current gain. Unoptimized doping results in a low common-emitter current gain. The bias state of the front gate of the MOS has a significant influence on the characteristics of the built-in BJT. The geometry effect of the device

Pattern-recessed ohmic contacts are investigated for InAlGaN/GaN high-electron-mobility transistors (HEMTs). Periodically-recessed patterns are introduced in the source and drain contact area to achieve the lower contact resistance by making sidewall contact as well as top contact on the active mesa. The lowest ohmic contact resistance (Rc) of 0.19 Ω·mm is achieved. It is significantly lower than the

Silicon Photonics Technology using sub micrometer SOI platform, which commercially emerged at the beginning of the century, has now gained market shares in the field of fiber optic interconnects, from Inter-to Intra-Data Center communications. With growing demands in terms of aggregated bandwidth, scalability, transceiver form factor, and cost, Silicon Photonics is expected to play a growing role,

The triboelectric nanogenerator (TENG) based on the contact-electrification and electrostatic induction are attractive for the abundant application in many disciplines. To explore the practical application of TENG devices, we firstly reported a novel TENG based on the white sugar (WS-TENG) to harvest mechanical energy, and simultaneously, which can also serve as the self-powered humidity sensor due

The thermal-oxidation/wet-etching gate-recess mask using low-pressure-chemical-vapor-deposition (LPCVD) SiN/atomic-layer-deposition (ALD) AlN combined with high-quality LPCVD-SiN/ALD-SiO2 gate dielectric has been developed for the fabrication of normally-off GaN MISFETs by the self-terminated gate recess etching technique. The experimental results showed that the SiN/AlN layer could effectively hinder

Recently, negative capacitance (NC) effect in the dielectric/ferroelectric (DE/FE) bilayer system has received significant attention due to its potential in achieving sub- 60 mV/decade subthreshold swing in FETs as well as extremely large capacitance density in dynamic random-access memory (DRAM). However, such reports, to date, are primarily based on conventional perovskite FE materials which are

A systematic method for the verification of high frequency measurement (up-to 500 GHz) of silicon germanium heterojunction bipolar transistor (SiGe HBT) is proposed. First of all, the method involves an accurate estimation of the effects of passive environment on the overall measurement by a detailed electro-magnetic (EM) simulation. This ensures that the complete measurement environment like probes

Due to their excellent photo-to-electric power conversion efficiency (PCE) (up to 25.2%) under AM 1.5G (≈100,000 Lux), the perovskite solar cells (PSCs) have received widespread attention in recent years, but the research on their weak light (0–1000 Lux) performances is still rare. So, the effect factors of their weak light performances were explored in this work. According to the results, the PSCs

It is important to characterize the distribution of spatial traps in the MOS structure for separating the interface states from the subgap density-of-states. In this study, we report a characterization technique for the spatial distribution of traps using the C-V characteristics under deep-depletion bias. Depletion capacitance is determined by the depletion depth (Xd) and the dielectric constant with

For pragmatic utilizations of field-effect transistors (FETs), the control of threshold voltage (Vth) is significant for sensing applications as various sensors and circuits require distinctive electrical characteristics. Moreover, the controllable threshold voltage is essential for creating integrated circuits (IC). The threshold voltage of a TFT is sensitive to numerous factors, which make it alluring

Processing techniques for the thickness-controlled layer separation of a single-crystalline semiconductor have been actively developed for manufacturing complementary metal–oxide–semiconductor (CMOS)-technology-based flexible devices. A mechanical separation process for thin semiconductor layers, called the spalling technique, has recently attracted much attention because of its process simplicity

TCAD modelling of InGaAs channel MOSFETs is a complex task due to the combined effect of quantization and interface or border traps, which affect the device electrostatics as well as the electron mobility through Coulomb scattering. In addition, trap distributions and mobility are strain-dependent. In this paper, we start from a microscopic physical approach, based on the use of Sentaurus SBand by

This paper presents an accurate, comprehensive and physics-based aging compact model for stress-induced degradation due to hot-carrier generation and oxide trapping in advanced complementary NPN and PNP SiGe HBTs. The analytical model equations are derived from the solution of reaction-diffusion theory and Fick’s law of diffusion combined with oxide trapping mechanism under accelerated stress conditions

The depth profiles of aluminum (Al) ion implantation on 4H-SiC epilayers with implantation energy range from 90 keV to above 1 MeV have been studied. The SIMS profiles show that the channeling effect is significantly reduced as the energy increases. This is attributed to the dechanneling effects due to the introduction of interstitial type defects created by preceding implanting ions under high-implantion

In this work, the use of sublimated copper phthalocyanine (CuPc) organic thin films as a buffer interlayer in aluminum tracks on paper is presented for the first time. The CuPc was synthetized using a new eco-friendly synthetic protocol and the higher purity of the product turn out to be useful for the set forth applications. With the use of the CuPc buffer interlayer it is possible to enable paper

This study presents a novel method to evaluate oscillation condition by technology computer-aided design (TCAD) simulation and is based on a signal flow graph model and a scattering parameter (S-parameter) computed using the TCAD simulation result. The parasitic oscillation of Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) when a short circuit occurs has been investigated

In this paper, the superlattice-like V2O5/Ge8Sb92 films are studied. Compared with Ge8Sb92 film, V2O5/Ge8Sb92 films have a high crystallization temperature (∼233°C), a large amorphous resistance (∼3.4×107 Ω) and good data retention temperature (∼171.2°C) for ten years. The volume change rate of V2O5/Ge8Sb92 superlattice-like film is only 1.855% during the crystallization, which can guarantee a better

Straightforward contact resistance extraction methods based on electrical device characteristics are described and applied here to graphene field-e_ect transistors from di_erent technologies. The methods are an educated adaptation of extraction procedures originally developed for conventional transistors by exploiting the drift-di_usion-like transport in graphene devices under certain bias conditions

This paper demonstrates the design strategy in the self-aligned quantum-well InAs MOSFETs with T-shape S/D. A 2-D TCAD simulation is performed based on the experimental data. The effect of air gap between the T-shape metal contacts is taken into account. It is found that the fringing effects induced by the air gap has significant impacts on both DC and RF performances. Further study is carried out

Electrical properties of metal-oxide-semiconductor (MOS) capacitors were measured with MgO / Al2O3 gate dielectrics deposited by atomic layer deposition (ALD) on GaN. For an Al2O3 (1 nm) / MgO (20 nm) dielectric layer, a leakage current density of 0.25 mA/cm2 at 1 V was measured for the MOS capacitor. A peak capacitance of ∼0.1 μF/cm2 was obtained from the C-V measurements with significant hysteresis

Thin films with HfO2/Al2O3 laminated structure were prepared by the ALD method in this paper. Typical bipolar resistance switching characteristics were observed in the Pt/HfO2/Al2O3/TiN structure device. The samples were characterized by X-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM). The effects of dielectric thickness and different test temperatures on the electrical performance

In this paper, high-power up to 4000 mW electro-mechanical behavior of a capacitive micro-electromechanical systems (MEMS) microwave power sensor using cantilever beam is investigated. Due to residual stress gradients, the power sensor is proposed for a warped cantilever beam connected to coplanar waveguide (CPW) structure. The proposed sensor is fabricated using the GaAs monolithic microwave integrated

ZnO thin-film transistors (TFTs) with scaled channel lengths of 10 μm, 5 μm, 4 μm, and 2 μm exhibit increasing intrinsic channel electron mobility at a gate bias of 10 V (15 V) from 0.782 cm2/Vs (0.83 cm2/Vs) in the 10 μm channel length TFT to 8.9 cm2/Vs (19.04 cm2/Vs) for the channel length scaled down to 2 μm. Current-voltage measurements indicate an n-type channel enhancement mode transistor operation

Cowell’s method of extracting barrier heights of top and bottom electrode metals in asymmetric metal-insulator-metal (MIM) tunneling diodes exhibiting Fowler-Nordheim tunneling is successfully automated. Pt-Al2O3-TiN MIM diodes with 5 nm insulator thickness are used in demonstration. Conditions assuring successful application of Cowell’s method and its automation are discussed.

Spin-transfer torque magnetic random access memory (STT-MRAM) is one of the most promising candidates for “universal memory” with the ultra-fast access speed, radiation resistance and theoretically unlimited endurance. However, there are many practical aspects that could degrade the life-time of STT-MRAM. In this paper, degradation on the life-time of the STT-MTJ device is observed experimentally,

We have investigated the effects of a silicon nitride (SiNx) passivation process using plasma-enhanced chemical vapor deposition (PECVD) on a ultra-thin-barrier AlGaN/GaN heterostructure field-effect transistors (HFETs). The bulk charge characteristics of the PECVD SiNx films were dependent on the film deposition conditions, which strongly influenced the sheet resistance (Rsh) and flat-band voltage

This paper presents an investigation of the abnormal hump phenomenon in amorphous indium gallium zinc oxide thin-film transistors under positive gate bias and temperature stress (PBTS). During PBTS, the current-voltage curve shows a severe hump and an abnormal double hump. Additional stress tests were conducted under long-term and low-temperature PBTS and current stress (CS), then the capacitance-voltage

Ge-rich GeSbTe (GST) alloys are attracting Phase Change Materials for future memories as their higher crystallization temperature offers an extended range of applications. We have studied the electrical characteristics of PCM cells using such alloys as active layers. We show by impedance spectroscopy that the cells in the RESET (amorphous) state are not only resistive but also exhibit a capacitive

The modern electronic devices have been scaled down significantly. The scaling rules would dictate higher doping concentrations which lead us to consider the degeneracy in the calculations. One of the semiconductor device quantities that would be impacted by considering the degeneracy is the Einstein Relation. The commonly used formula of Einstein Relation assumes that it is constant and independent

In this paper we have implemented a recently proposed direct-measurement technique to characterize near-interface oxide traps (NITs) in SiC MOS capacitors with gate oxides obtained by four different processes. This measurement technique enables characterization of NITs with energy levels above the bottom of the conduction band, which are active in the accumulation mode of MOS capacitors on N-type SiC

In this paper we identify the dominant contribution to the OFF-state distortion of an MOS transistor coming from the overlap regions applying of device-level harmonic balance simulations in a calibrated TCAD setup. Both overlap (Cgs,Cgd) and direct capacitance (Cds) are described with novel physics-based models that are, in conjunction with an analytical Volterra series analysis, capable of describing

The transition region between the active area and the edge termination of silicon carbide (SiC) MOSFET is either used to place a poly-silicon gate runner (G-MOS) or electrically contacted to the source potential (S-MOS), which is studied experimentally and by TCAD simulation in this work. The simulation results indicate that the transition region of G-MOS can effectively alleviate the propagation delay

Junctionless transistors (JLTs) are one of attractive candidates for further scaling down thanks to their promising advantages based on a structural simplicity without PN junctions, and their physical operation is quite different from traditional inversion-mode (IM) transistors. In this paper, we investigated the subthreshold operation of tri-gate JLTs with various effective width (Weff) and compared

Metal-insulator-metal (MIM) diode is considered as a promising candidate for various high frequency applications owing to its tunneling dominant ultra-fast switching time. The zero bias operation of these diode rectifiers is very desirable for detection of low power RF signals. In the present work, an Au/Al2O3/Mo MIM diode integrated with coplanar waveguide (CPW) is fabricated and its rectification

A parallel-MOS-triggered silicon-controlled rectifier (PMTSCR) is firstly proposed and verified in a 0.25-μm Bipolar-CMOS-DMOS process, aiming to prevent the latch-up effect of SCR in the electrostatic discharge (ESD) protection. Comparing to the conventional SCR, the trigger voltage (Vt1) of the PMTSCR decreases because of the effect of PMOS embedded in the N-well, and the holding voltage (Vh) increases

TiO2/g-CN based photocatalyst has been widely studied for its easy synthesis and outstanding charge separation efficiency. However, the difficulty in obtaining a high photocurrent value limits its application in photoelectrocatalysis water splitting. In this article, bimetallic NiMoO4 nanosheets co-catalyst was decorated onto TiO2/g-CN heterojunction to form TiO2/g-CN/NiMoO4 3D nanostructure. We obtained

Present work has used Green’s function approach to derive a two-dimensional analytical model of the double gate (DG) MOSFET at the subthreshold regime of operation that considers the effect of inevitable source/drain (S/D) lateral Gaussian doping profile. The non-integrable Gaussian term has been converted into an integrable function for accurate Fourier coefficient calculation which is then used to

This paper reports an investigation of the effects of varying different device parameters on the random-dopant-fluctuation (RDF) induced threshold voltage variability (σVT) in junctionless (JL) InGaAs FinFETs. Such investigation is made by means of a 3D numerical device simulator. Both gate length and fin height scaling are found to increase σVT in InGaAs JL FinFETs, similar to that in Si devices,