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Analysis and modeling of OFF-state hysteretic losses in GaN power HEMTs Solid State Electron. (IF 1.437) Pub Date : 2021-04-06 Dhawal Dilip Mahajan, Sourabh Khandelwal
We present a detailed analysis of large-signal Sawyer-Tower measurements on a power GaN HEMT device in OFF-state. The measurements show hysteresis which results in an energy loss dissipated as heat in the range of sub-μJ’s. We model this important phenomenon in this paper using a previously calibrated model of the same device. We propose two models, one with linear Effective Series Resistance (ESR)
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Improving the barrier inhomogeneity of 4H-SiC Schottky diodes by inserting Al2O3 interface layer Solid State Electron. (IF 1.437) Pub Date : 2021-03-23 Ding-kun Shi, Ying Wang, Xue Wu, Zhao-yang Yang, Xing-ji Li, Jian-qun Yang, Fei Cao
In this paper, an Al/Ti Schottky-electrode was fabricated on a 4H- SiC surface via sputtering, and an Al2O3 layer was inserted into the metal semiconductor contact-surface using atomic-layer deposition. We studied the inhomogeneity of the Schottky-barrier height by inserting the dielectric layer (Al2O3) with different thicknesses. The Schottky-barrier heights and ideality factors were extracted for
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Exploration of Logic Gates and Multiplexer using Doping-free Bipolar Junction Transistor Solid State Electron. (IF 1.437) Pub Date : 2021-04-02 Abhishek Sahu, Abhishek Kumar, Shree Prakash Tiwari
Logic gates are designed using symmetric lateral doping-free bipolar junction transistor (BJT) on silicon on insulator (SOI) using differential pass transistor logic, and their performance matrices are presented. Charge carriers are induced in lightly doped emitter and collector regions using two unique approaches. i.e., the charge plasma (CP) and polarity control (PC). AND, OR and XOR gates are designed
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Semi analytical model for electrical transport in single wall carbon nanotube thin film transistors Solid State Electron. (IF 1.437) Pub Date : 2021-04-01 Srijeet Tripathy, Tarun Kanti Bhattacharyya
With the recent advances in carbon nanotube (CNT) electronics, transistors made of thin films of single wall CNTs (SWNTs) are gaining great attention due to their high quality electrical characteristics. With such improvements it has become essential to develop suitable models to accurately predict the electrical transport in such devices which in the current scenario remains scarce. This work presents
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Analysis of reverse voltage distribution of high-voltage diode stack considering effect of temperature Solid State Electron. (IF 1.437) Pub Date : 2021-03-23 Hak Bong Kim, In Sik Ri, Hyon Chol Kang, Sin Ung Ri, Yong Taek Pak
In this paper, we proposed an equivalent circuit of a cell device (high-voltage silicon diode), considering effects of temperature and reverse voltage on it, and obtained the analytical expression of impedance of a cell device. Subsequently, in order to improve the reverse voltage distribution of the high-voltage diode stack consisting of a serial connection of cell devices, uniform voltage impedance
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Simplified electrical modeling for dye sensitized solar cells: Influences of the blocking layer and chenodeoxycholic acid additive Solid State Electron. (IF 1.437) Pub Date : 2021-02-23 Mian-En Yeoh, Kah-Yoong Chan, Dietmar Knipp
Dye sensitized solar cells (DSSCs) have been in the research limelight for some years and plenty of research were devoted to the investigation of material properties for device enhancement. The electrical modeling facilitates the simulation of the device characteristics of the DSSCs. In order to develop highly efficient DSSCs, it is crucial to elucidate the electric mechanism within the cell through
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Degradation study of carrier selective contact silicon solar cells with ageing: Role of silicon surface morphology Solid State Electron. (IF 1.437) Pub Date : 2021-03-06 Krishna Singh, Mrutyunjay Nayak, Dipak Kumar Singh, Vamsi K. Komarala
Ageing effect on the performance of Ag/ITO/MoOx/n-Si/LiFx/Al carrier selective contact (CSC) silicon solar cells has been investigated based on silicon surface morphology (planar, different pyramid sizes, and chemical polishing of pyramids). The cells with small silicon pyramids (~2 µm) have shown better stability with time than the medium/large pyramids (~5/~8 µm). The chemical polishing of pyramid
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High-state spin in Ru4+: Play the role in the interface coupling of the La0.7Sr0.3MnO3/SrRuO3 heterostructure Solid State Electron. (IF 1.437) Pub Date : 2021-03-04 Guoqing Zhao, Xingkun Ning
We have investigated the exchange bias effect in La0.7Sr0.3MnO3/SrRuO3 bilayers that epitaxial grown in different directions and various substrates. A linear-tunable exchange bias effect, which related to the spin states of the SrRuO3 layers have been discovered. The spin state of Ru4+ play the centre role in the interaction, and proposes mechanisms to understand the Mn-O-Ru antiferromagnetic coupling
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Fabrication and characterization of GaN HEMTs grown on SiC substrates with different orientations Solid State Electron. (IF 1.437) Pub Date : 2021-02-26 Chung-Wang Su, Tong-Wen Wang, Meng-Chyi Wu, Cheng-Jung Ko, Jun-Bin Huang
This article reports the fabrication and characterization of metal–semiconductor high electron mobility transistors (MS-HEMT) and metal–oxidesemiconductor (MIS-HEMT) grown on the semi-insulating SiC substrates with 0° and 4°-off axis. For the MIS-HEMT, the HfO2 film was used as the insulator deposited by atomic layer deposition. With a gate length of 2 μm, MS-HEMT and MIS-HEMT devices with 4°-off SiC
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Simulations of Residual Offset of Five-Contact Vertical Hall Devices with Slim Waist Solid State Electron. (IF 1.437) Pub Date : 2021-03-05 Shizhong Guo
As an important part of three-dimensional (3D) magnetic sensors, the vertical Hall devices directly determine the overall performance of the sensors. However, the traditional vertical Hall devices (5CVHD) have large offset and low sensitivity due to an inherent electrical asymmetry. In order to solve this problem, the traditional five-contact vertical Hall devices are optimized to obtain the five-contact
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In-depth analysis of electrical characteristics for polycrystalline silicon vertical thin film transistors Solid State Electron. (IF 1.437) Pub Date : 2021-02-23 Peng Zhang, Emmanuel Jacques, Régis Rogel, Laurent Pichon, Olivier Bonnaud
A polycrystalline silicon vertical thin film transistor (VTFT) is fabricated, and the electrical parameters are extracted and compared with the typical lateral thin film transistor (LTFT). The similar subthreshold slope and the distinct field effect mobility is verified by the DOS calculation in the deep and shallow trap regions, respectively, and in this article, it is used to compare with the grain
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Dependent of switching polarity for HfOx-based memory on doping content and current Solid State Electron. (IF 1.437) Pub Date : 2021-02-19 Tingting Guo, Tingting Tan, Li Duan, Yuxuan Wang, Zizhe Wang
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Temperature Optimization for AlGaN/GaN HEMT with the Etched AlGaN Layer Based on 2-D Thermal Model Solid State Electron. (IF 1.437) Pub Date : 2021-02-23 Luoyun Yang, Baoxing Duan, Yintang Yang
When the AlGaN/GaN HEMT is working for a long time under the high-power and high-temperature conditions, the internal heat will reduce its reliability. Here, the author first proposed a 2-D temperature distribution model to explain the mechanism of internal charge modulation to reduce the junction temperature of AlGaN / GaN HEMT. The etched AlGaN layer affects the channel 2DEG distribution and a new
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Suppression of Current Dispersion in AlGaN/GaN MISHFETs with in-situ AlN Passivation Layer Solid State Electron. (IF 1.437) Pub Date : 2021-02-23 Jun-Hyeok Lee, Jeong-Gil Kim, Hee-Sung Kang, Jung-Hee Lee
We demonstrate effective reduction of interface states and current collapse in AlGaN/GaN metal insulator semiconductor heterostructure field effect transistor (MISHFETs) with Al2O3 and in-situ AlN passivation layer. Here, first, a 3 nm-thick in-situ AlN layer is grown on AlGaN/GaN structure by using MOCVD at 1070 °C, and second a 7 nm-thick atomic layer deposition (ALD) Al2O3 layer is immediately deposited
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Novel Barrier-Well Heterostructure Diodes for Microwave and mm-Wave Detection Applications Solid State Electron. (IF 1.437) Pub Date : 2021-02-05 A. Hadfield, A. Salhi, J. Sexton, M. Missous
We present two novel barrier-well heterostructure diodes, for use as zero bias detectors in microwave and mm-wave applications. One based on the GaAs platform and one based on In0.53Ga0.47As lattice matched to InP. This is achieved by adding quantum wells to Asymmetric Spacer Layer Tunnel (ASPAT) diodes next to the barrier. The DC characteristics of these new diodes were simulated in SILVACO Atlas
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Advanced temperature dependent statistical analysis of forming voltage distributions for three different HfO2-based RRAM technologies Solid State Electron. (IF 1.437) Pub Date : 2021-01-23 Eduardo Pérez, David Maldonado, Christian Acal, Juan Eloy Ruiz-Castro, Ana María Aguilera, Francisco Jiménez-Molinos, Juan Bautista Roldán, Christian Wenger
In this work, voltage distributions of forming operations are analyzed by using an advanced statistical approach based on phase-type distributions (PHD). The experimental data were collected from batches of 128 HfO2-based RRAM devices integrated in 4-kbit arrays. Three different switching oxides, namely, polycrystalline HfO2, amorphous HfO2, and Al-doped HfO2, were tested in the temperature range from
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High performance InGaAs channel MOSFETs on highly resistive InAlAs buffer layers Solid State Electron. (IF 1.437) Pub Date : 2020-12-03 Sang Tae Lee, In-Geun Lee, Hyunchul Jang, Minwoo Kong, Changhun Song, Chang Zoo Kim, Sang Hyun Jung, Youngsu Choi, Shinkeun Kim, Su-keun Eom, Kwang-seok Seo, Dae-Hyun Kim, Dae-Hong Ko, Chan-Soo Shin
We investigated the effect of growth temperature on the structural and electrical properties of InAlAs layers grown on InP (1 0 0) substrates by metalorganic chemical vapor deposition (MOCVD) method. Flat surface morphology of InAlAs layers with root mean square (RMS) surface roughness values below 0.4 nm were obtained at 500 °C and 660 °C, while RMS surface roughness values of InAlAs layers grown
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Stochastic multiscale model for HfO2-based resistive random access memories with 1T1R configuration Solid State Electron. (IF 1.437) Pub Date : 2020-12-17 Silvana Guitarra, Laurent Raymond, Lionel Trojman
In this paper, we propose a stochastic model for the resistive switching of ReRAM devices with 1T1R configuration. We work with the fact that the switching occurs in the narrowest zone of the conductive filament due to changes caused by the electric field. This active region is represented by a net of vertical connections, each one composed of three electrical elements: two of them are always low resistive
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Trapping effects on AlGaN/GaN HEMT characteristics Solid State Electron. (IF 1.437) Pub Date : 2020-11-28 P. Vigneshwara Raja, Jean-Christophe Nallatamby, Nandita DasGupta, Amitava DasGupta
This paper describes device simulation studies of surface and buffer trapping effects on static I-V, output-admittance (Y22), and transient characteristics of AlGaN/GaN HEMTs. The TCAD simulation model considering surface donors at EC − 0.5 eV and buffer traps at EC − 0.47 eV have been used to quantitatively reproduce the measured DC, Y22 frequency dispersion, gate-lag (GL) and drain-lag (DL) transients
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Indium oxide nanoparticles for resistive RAM integration using a compatible industrial technology Solid State Electron. (IF 1.437) Pub Date : 2021-01-13 P.V. Guenery, E.A. León Pérez, K. Ayadi, N. Baboux, D. Deleruyelle, S. Blonkowski, J. Moeyaert, T. Baron, L. Militaru, A. Souifi
In this work we report on the integration of indium oxide (In2O3) nanoparticles (NPs) for Resistive Random Access Memory (RRAM) applications. This low-temperature integration process is fully compatible CMOS Back-End integration given a carefull selection of materials deposited by MOCVD and ALD. A detailed description of the process is provided together with AFM analysis performed on the indium oxide
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Effect of organic solvent vapor treatment on transistor performance and contact resistance of copper phthalocyanine based organic field-effect transistors Solid State Electron. (IF 1.437) Pub Date : 2021-01-05 Pankaj Kumar, Sarita Yadav, Naresh Kumar, Lokendra Kumar
Herein, we investigated the effect of organic solvent drop-casting and solvent vapour annealing (SVA) on the surface morphology of copper phthalocyanine (CuPc) and its effect on the transistor performance and contact resistance in organic field effect transistors (OFETs). Organic solvents: acetone and isopropyl alcohol (IPA) are used for drop-casting and SVA treatment of CuPc film. The morphology,
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Carbon-based, all-inorganic, lead-free Ag2BiI5 rudorffite solar cells with high photovoltages Solid State Electron. (IF 1.437) Pub Date : 2021-01-23 Fengqin He, Qian Wang, Weidong Zhu, Dazheng Chen, Jincheng Zhang, Chunfu Zhang, Yue Hao
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On the diffusion current in a MOSFET operated down to deep cryogenic temperatures Solid State Electron. (IF 1.437) Pub Date : 2021-01-23 G. Ghibaudo, M. Aouad, M. Casse, T. Poiroux, C. Theodorou
A detailed and didactic analysis of the diffusivity in a 2D inversion layer is carried out, providing its dependence on carrier density and temperature. Then, a comprehensive study of the diffusion and drift current components in a MOSFET is proposed. Their dependence with gate and drain voltages is investigated down to deep cryogenic temperature, revealing that at T = 4 K the diffusion current is
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Comparative study of metamorphic InAs layers grown on GaAs and Si for mid-infrared photodetectors Solid State Electron. (IF 1.437) Pub Date : 2020-12-03 Geunhwan Ryu, Soo Seok Kang, Jae-Hoon Han, Rafael Jumar Chu, Daehwan Jung, Won Jun Choi
We report a comparative study of metamorphic InAs p-i-n photodetectors epitaxially grown on GaAs and Si by molecular beam epitaxy. Linearly graded InAlAs buffers were employed to bridge the high lattice mismatch between InAs and Si. Quantitative measurement for threading dislocation density (TDD) in the InAs layers grown on GaAs and Si has been performed using transmission electron microscopy and electron
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Interfacial oxidation for spin transport in Fe3O4/sulfonic acid molecule nanoparticles Solid State Electron. (IF 1.437) Pub Date : 2021-01-23 Xurong Shi, Shen Wang, Xingliang Su, Yujun Shi, Baojun Shi, Haitao Zhou, Hujun Jiao
We fabricated the Fe3O4/alkyl-sulfonic acid molecules hybrid nanoparticles by self-assembly monolayers (SAMs) in air and nitrogen ambience to investigate the impact of the oxidation on the spin transport. X-ray photoelectron spectra (XPS) and Fourier transform infrared (FTIR) spectroscopy measurements infer that the chemical bonding between Fe3O4 and alkyl-sulfonic acid remains unchanged as interfacial
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Compact charge model for Si gate-all-around nMOSCAPs with cylindrical cross-sections considering the density-gradient equation Solid State Electron. (IF 1.437) Pub Date : 2021-01-21 Kwang-Woon Lee, Sung-Min Hong
A compact charge model for Si gate-all-around n-type metal-oxide-semiconductor capacitors (nMOSCAPs) with cylindrical cross-sections including the quantum confinement effect is presented. The density-gradient equation with a penetrating boundary condition is integrated to consider the quantum confinement effect. From the integrated equation, an expression for the surface potential is derived, and a
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Pragmatic Z2-FET compact model including DC and 1T-DRAM memory operation Solid State Electron. (IF 1.437) Pub Date : 2021-01-20 Sébastien Martinie, Joris Lacord, Kyunghwa Lee, Maryline Bawedin, Sorin Cristoloveanu
Z2-FET, a partially gated diode, was explored for ESD protection due to its sharp switching behavior and is also a promising candidate for 1T-DRAM application. Based on detailed TCAD simulations, we develop a pragmatic SPICE compact model, including DC and memory operation. The model is validated via TCAD and experimental data. The proposed model reproduces the S-shaped V-I characteristics, the hysteresis
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A Low-Power Nanoelectromechanical (NEM) Device with Al-Doped HfO2-Based Ferroelectric Capacitor Solid State Electron. (IF 1.437) Pub Date : 2021-01-13 Shinhee Kim, Jae Yeon Park, Seungwon Go, Hyug Su Kwon, Woo Young Choi, Sangwan Kim
Nanoelectromechanical (NEM) device has been regarded as one of the future switching devices due to its nearly infinite switching slope and zero off-state leakage current. However, it suffers from high pull-in voltage which causes high operation voltage. In this study , a sub-15 nm-thick Al-doped HfO2-based ferroelectric (FE) layer with a negative capacitance (NC) that can exceed the scalability limitation
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A Generalized EKV Charge-based MOSFET Model Including Oxide and Interface Traps Solid State Electron. (IF 1.437) Pub Date : 2021-01-07 Chun-Min Zhang, Farzan Jazaeri, Giulio Borghello, Serena Mattiazzo, Andrea Baschirotto, Christian Enz
This paper presents a generalized charge-based EKV MOSFET model that includes the effects of trapped charges in the bulk oxide and at the silicon/oxide interface. It is shown that in the presence of oxide- and interface-trapped charges, the mobile charge density can still be linearized but with respect to both the surface potential and the channel voltage. This enables us to derive closed-form expressions
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Mechanism of Proton-Induced Electrical Degradation of AlGaN/GaN High Electron Mobility Transistors Solid State Electron. (IF 1.437) Pub Date : 2021-01-07 Dong-Seok Kim, Jeong-Gil Kim, Jun-Hyeok Lee, Yong Seok Hwang, Young Jun Yoon, Jae Sang Lee, Youngho Bae, Jung-Hee Lee
We studied the mechanism of the proton-induced electrical degradation of AlGaN/GaN high electron mobility transistors (HEMTs) through 5-MeV proton irradiation. First, the AlGaN/GaN heterostructure was exposed to protons with a fluence of 1 × 1015 p/cm2 to investigate the relationship between the radiation-caused damage in the heterostructure and the electrical characteristics of HEMTs. The HEMTs fabricated
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A physics-based compact model for phase-change memory considering the ratio of vertical-to-lateral crystal growth rate for the design of cross-point storage-class memory Solid State Electron. (IF 1.437) Pub Date : 2021-01-06 Donguk Kim, Jun Tae Jang, Dong Myong Kim, Sung-Jin Choi, Sanghyun Ban, Minchul Shin, Hanwool Lee, Hyung Dong Lee, Hyun-Sun Mo, Dae Hwan Kim
A physics-based compact model for phase-change random access memory (PcRAM) was proposed considering the ratio of vertical-to-lateral crystal growth rate (α) and it was incorporated into HSPICE via Verilog-A. The proposed model was verified by using the experimental results taken from the 256 × 256 cross-point (X-point) PcRAM cell array with the Ge2Sb2Te5 2z-nm technology node. The proposed compact
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2.7-kV AlGaN/GaN Schottky Barrier Diode on Silicon Substrate with Recessed-anode Structure Solid State Electron. (IF 1.437) Pub Date : 2020-12-29 Ru Xu, Peng Chen, Menghan Liu, Jing Zhou, Yimeng Li, Bin Liu, Dunjun Chen, Zili Xie, Rong Zhang, Youdou Zheng
In this paper, we demonstrate high-performance lateral AlGaN/GaN Schottky barrier diodes (SBD) on Si substrate with a recessed-anode structure. The optimized rapid etch process provides results in improving etching quality with a 0.26-nm roughness of the anode recessed surface. By using the high work function metal Pt as the Schottky electrode, a low turn-on voltage of 0.71 V is obtained with a high
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Experimental Investigation on Total-Ionizing-Dose Radiation Effects on the Electrical Properties of SOI-LIGBT Solid State Electron. (IF 1.437) Pub Date : 2020-12-23 Guangan Yang, Wangran Wu, Xingyao Zhang, Pengyu Tang, Jing Yang, Long Zhang, Siyang Liu
In this paper, the experimental investigation on the electrical properties of silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT) after total-ionizing-dose (TID) irradiation is presented. We find that the TID irradiation reduces the threshold voltage (Vth), and increases the collector current (ICE) at the same gate voltage (Vg). The raising ICE is mainly attributed to the negative
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Analysis of the Transient Body Effect Model for an LTPS TFT on a Plastic Substrate Solid State Electron. (IF 1.437) Pub Date : 2020-12-17 Yunyeong Choi, Taekyeong Lee, Jisun Park, Hyungsoon Shin
This work investigates the transient current in the subthreshold region of a low-temperature polycrystalline silicon thin-film transistor (LTPS TFT) on a polyimide (PI) substrate. The measurement of this current shows an instability that is not seen in the device on a glass substrate; the instability appears as a current variation under constant voltage and overshoot or undershoot under external stress
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A Fast Small Signal Modeling Method for GaN HEMTs Solid State Electron. (IF 1.437) Pub Date : 2020-12-14 Ziyue Zhao, Yang Lu, Chupeng Yi, Yilin Chen, Xiaolong Cai, Yu Zhang, Xiangyang Duan, Xiaohua Ma, Yue Hao
An accurate and efficient parasitic parameter extraction method is proposed for gallium nitride (GaN) high electron-mobility transistors (HEMTs). In this letter, a 19-element small signal equivalent circuit model is established to describe the characteristics of the device precisely. The simulation of the high frequency behavior is improved by introducing the series parasitic inductances into the cold
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Continuous and Symmetric Trans-Capacitance Compact Model for Triple-Gate Junctionless MOSFETs Solid State Electron. (IF 1.437) Pub Date : 2020-12-09 T.A. Oproglidis, A. Tsormpatzoglou, D.H. Tassis, C.G. Theodorou, G. Ghibaudo, C.A. Dimitriadis
In this work, a continuous and symmetric trans-capacitance compact model for triple-gate junctionless MOSFETs is presented, valid in all regions of operation. Initially, the expressions of the gate, drain and source total charges are analytically derived based on a continuous and symmetric drain current compact model already developed. Then, the intrinsic capacitances are calculated via the differentiation
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Exploring Bahaviors of Electrode-driven Si Quantum Dot Systems: From Charge Control to Qubit Operation Solid State Electron. (IF 1.437) Pub Date : 2020-12-04 Ji-Hoon Kang, Junghee Ryu, Hoon Ryu
Charge stabilities and spin-based quantum bit (qubit) operations in Si double quantum dot (DQD) systems, whose confinement potentials are controlled with multiple gate electrodes, are theoretically studied with a multi-scale modeling approach that combines electronic structure simulations and a Thomas-Fermi method. Taking Si/SiGe heterostructures as the target of modeling, this work presents in-depth
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PureB diode fabrication using physical or chemical vapor deposition methods for increased back-end-of-line accessibility Solid State Electron. (IF 1.437) Pub Date : 2020-12-03 Shivakumar D. Thammaiah, Xingyu Liu, Tihomir Knežević, Kevin M. Batenburg, A.A.I. Aarnink, Lis K. Nanver
Several methods of depositing pure boron (PureB) layers on silicon are examined with respect to their potential for fabricating advanced PureB (photo)diodes with back-end-of-line (BEOL) CMOS compatibility. PureB devices were fabricated in two different batch furnace chemical-vapor deposition (CVD) systems or by electron-beam-assisted physical-vapor deposition (EBPVD), and their electrical characteristics
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Vertical growth characterization of InAs nanowires grown by selective area growth on patterned InP(111)B substrate by a MOCVD method Solid State Electron. (IF 1.437) Pub Date : 2020-12-03 Chang-Hun Song, Minwoo Kong, yunchul Jang, Sang Tae Lee, Hyeong-Ho Park, Chang Zoo Kim, Sang Hyun Jung, Youngsu Choi, Shinkeun Kim, Dae-Hong Ko, Kwangseok Seo, Chan-Soo Shin
InAs nanowires (NWs) were selectively grown on hole patterned InP (111)B substrate by Metal-Organic Chemical Vapor Deposition (MOCVD). This study reports the vertical growth behavior of InAs NWs transitioned at a certain height and its difference under various growth conditions. This certain height is referred as “critical height.” This is a boundary where both vertical and lateral growth occur. Under
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Origin of Incremental Step Pulse Programming (ISPP) Slope Degradation in Charge Trap Nitride based Multi-Layer 3D NAND Flash Solid State Electron. (IF 1.437) Pub Date : 2020-12-02 Kihoon Nam, Chanyang Park, Jun-Sik Yoon, Hyundong Jang, Min Sang Park, Jaesung Sim, Rock-Hyun Baek
We analyzed Incremental Step Pulse Programming (ISPP) slope degradation to improve the program efficiency of 3D NAND Flash memory using both measurement and simulation data. The simulation data are calibrated with the measurement data and they are in good agreement. The ISPP slope indicates program efficiency and its ideal value is 1. In reality, however, ISPP slope degradation (< 1) occurs in the
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Abnormal threshold voltage shift by the effect of H2O during negative bias stress in amorphous InGaZnO thin film transistors Solid State Electron. (IF 1.437) Pub Date : 2020-10-28 Tae-Kyoung Ha, Yongjo Kim, SangHee Yu, GwangTae Kim, Hoon Jeong, JeongKi Park, Ohyun Kim
We observed abnormal threshold voltage (VT) shift in amorphous InGaZnO (a-IGZO) thin-film transistors under negative gate bias stress (NBS) after soaking them in H2O (pH 8). Before NBS, we soaked a-IGZO TFTs in H2O. During application of NBS, VT decreased by −0.43 V, then increased to nearly the initial value. We hypothesize that the electrical field that was applied during NBS caused some dissociation
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Drift of the sensitive direction of Hall-effect devices in (1 0 0)-silicon caused by mechanical shear stress Solid State Electron. (IF 1.437) Pub Date : 2020-11-13 Udo Ausserlechner, Michael Holliber, Benjamin Kollmitzer, Richard Heinz
Conventional Hall effect devices are designed to respond to a single magnetic field component in 3D space. However, if plastic encapsulated Hall effect devices in cubic crystals are exposed to poorly defined and unstable mechanical shear stress, small portions of unwanted, perpendicular magnetic field components will show up in the Hall output signals. Mathematically, any such crosstalk – may it originate
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The characterization of the built-in bipolar junction transistor in H-gate PD-SOI NMOS Solid State Electron. (IF 1.437) Pub Date : 2020-11-24 Huilong Zhu, Dawei Bi, Xin Xie, Zhiyuan Hu, Chunmei Liu, Zhengxuan Zhang, Shichang Zou
The built-in bipolar junction transistor of H-gate partially depleted SOI NMOS was characterized by measuring the common-emitter output curve and calculating the common-emitter current gain. Unoptimized doping results in a low common-emitter current gain. The bias state of the front gate of the MOS has a significant influence on the characteristics of the built-in BJT. The geometry effect of the device
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Effects of periodic patterns in recessed ohmic contacts on InAlGaN/GaN heterostructures Solid State Electron. (IF 1.437) Pub Date : 2020-11-10 Mi Jang, Juyeong Park, Ji Hyun Hwang, Ha Jin Mun, Suhyeong Cha, Sung-Min Hong, Jae-Hyung Jang
Pattern-recessed ohmic contacts are investigated for InAlGaN/GaN high-electron-mobility transistors (HEMTs). Periodically-recessed patterns are introduced in the source and drain contact area to achieve the lower contact resistance by making sidewall contact as well as top contact on the active mesa. The lowest ohmic contact resistance (Rc) of 0.19 Ω·mm is achieved. It is significantly lower than the
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Silicon Photonics for Terabit/s communication in Data Centers and Exascale Computers Solid State Electron. (IF 1.437) Pub Date : 2020-11-23 S. Bernabé, Q. Wilmart, K. Hasharoni, K. Hassan, Y. Thonnart, P. Tissier, Y. Désières, S. Olivier, T. Tekin, B. Szelag
Silicon Photonics Technology using sub micrometer SOI platform, which commercially emerged at the beginning of the century, has now gained market shares in the field of fiber optic interconnects, from Inter-to Intra-Data Center communications. With growing demands in terms of aggregated bandwidth, scalability, transceiver form factor, and cost, Silicon Photonics is expected to play a growing role,
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A triboelectric nanogenerator based on white sugar for self-powered humidity sensor Solid State Electron. (IF 1.437) Pub Date : 2020-11-12 Hongye Liu, Hao Wang, Yanping Fan, Yan Lyu, Zenghua Liu
The triboelectric nanogenerator (TENG) based on the contact-electrification and electrostatic induction are attractive for the abundant application in many disciplines. To explore the practical application of TENG devices, we firstly reported a novel TENG based on the white sugar (WS-TENG) to harvest mechanical energy, and simultaneously, which can also serve as the self-powered humidity sensor due
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Improved fabrication of fully-recessed normally-off SiN/SiO2/GaN MISFET based on the self-terminated gate recess etching technique Solid State Electron. (IF 1.437) Pub Date : 2020-11-19 Mengjun Li, Jinyan Wang, Bin Zhang, Qianqian Tao, Hongyue Wang, Qirui Cao, Chengyu Huang, Jianghui Mo, Wengang Wu, Shujun Cai
The thermal-oxidation/wet-etching gate-recess mask using low-pressure-chemical-vapor-deposition (LPCVD) SiN/atomic-layer-deposition (ALD) AlN combined with high-quality LPCVD-SiN/ALD-SiO2 gate dielectric has been developed for the fabrication of normally-off GaN MISFETs by the self-terminated gate recess etching technique. The experimental results showed that the SiN/AlN layer could effectively hinder
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Trade-off between interfacial charge and negative capacitance effects in the Hf-Zr-Al-O/Hf0.5Zr0.5O2 bilayer system Solid State Electron. (IF 1.437) Pub Date : 2020-10-21 Dipjyoti Das, Taeho Kim, Venkateswarlu Gaddam, Changhwan Shin, Sanghun Jeon
Recently, negative capacitance (NC) effect in the dielectric/ferroelectric (DE/FE) bilayer system has received significant attention due to its potential in achieving sub- 60 mV/decade subthreshold swing in FETs as well as extremely large capacitance density in dynamic random-access memory (DRAM). However, such reports, to date, are primarily based on conventional perovskite FE materials which are
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TCAD and EM co-simulation method to verify SiGe HBT measurements up to 500 GHz Solid State Electron. (IF 1.437) Pub Date : 2020-10-23 Soumya Ranjan Panda, Sebastien Fregonese, Marina Deng, Anjan Chakravorty, Thomas Zimmer
A systematic method for the verification of high frequency measurement (up-to 500 GHz) of silicon germanium heterojunction bipolar transistor (SiGe HBT) is proposed. First of all, the method involves an accurate estimation of the effects of passive environment on the overall measurement by a detailed electro-magnetic (EM) simulation. This ensures that the complete measurement environment like probes
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Performances of perovskite solar cells at low-intensity light irradiation Solid State Electron. (IF 1.437) Pub Date : 2020-09-30 Shusheng Zhu, Yang Li
Due to their excellent photo-to-electric power conversion efficiency (PCE) (up to 25.2%) under AM 1.5G (≈100,000 Lux), the perovskite solar cells (PSCs) have received widespread attention in recent years, but the research on their weak light (0–1000 Lux) performances is still rare. So, the effect factors of their weak light performances were explored in this work. According to the results, the PSCs
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Deep depletion capacitance–voltage technique for spatial distribution of traps across the substrate in MOS structures Solid State Electron. (IF 1.437) Pub Date : 2020-10-13 Han Bin Yoo, Jintae Yu, Haesung Kim, Ji Hee Ryu, Sung-Jin Choi, Dae Hwan Kim, Dong Myong Kim
It is important to characterize the distribution of spatial traps in the MOS structure for separating the interface states from the subgap density-of-states. In this study, we report a characterization technique for the spatial distribution of traps using the C-V characteristics under deep-depletion bias. Depletion capacitance is determined by the depletion depth (Xd) and the dielectric constant with
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Comparison of floating probe transient technique for on-state channel characterization & threshold voltage of an organic thin film transistor for sensing applications Solid State Electron. (IF 1.437) Pub Date : 2020-10-14 Rajesh Agarwal
For pragmatic utilizations of field-effect transistors (FETs), the control of threshold voltage (Vth) is significant for sensing applications as various sensors and circuits require distinctive electrical characteristics. Moreover, the controllable threshold voltage is essential for creating integrated circuits (IC). The threshold voltage of a TFT is sensitive to numerous factors, which make it alluring
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Investigation of electrical characteristics of flexible CMOS devices fabricated with thickness-controlled spalling process Solid State Electron. (IF 1.437) Pub Date : 2020-09-22 Honghwi Park, Changhee Lim, Yeho Noh, Chang-Ju Lee, Heungsup Won, Jaedong Jung, Muhan Choi, Jae-Joon Kim, Hocheon Yoo, Hongsik Park
Processing techniques for the thickness-controlled layer separation of a single-crystalline semiconductor have been actively developed for manufacturing complementary metal–oxide–semiconductor (CMOS)-technology-based flexible devices. A mechanical separation process for thin semiconductor layers, called the spalling technique, has recently attracted much attention because of its process simplicity
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Electron mobility of strained InGaAs long-channel MOSFETs: from scattering rates to TCAD model Solid State Electron. (IF 1.437) Pub Date : 2020-09-24 Stefania Carapezzi, Susanna Reggiani, Elena Gnani, Antonio Gnudi
TCAD modelling of InGaAs channel MOSFETs is a complex task due to the combined effect of quantization and interface or border traps, which affect the device electrostatics as well as the electron mobility through Coulomb scattering. In addition, trap distributions and mobility are strain-dependent. In this paper, we start from a microscopic physical approach, based on the use of Sentaurus SBand by
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A Unified Aging Compact Model for Hot Carrier Degradation under Mixed-mode and Reverse E-B stress in Complementary SiGe HBTs Solid State Electron. (IF 1.437) Pub Date : 2020-09-23 C. Mukherjee, G.G. Fischer, F. Marc, M. Couret, T. Zimmer, C. Maneux
This paper presents an accurate, comprehensive and physics-based aging compact model for stress-induced degradation due to hot-carrier generation and oxide trapping in advanced complementary NPN and PNP SiGe HBTs. The analytical model equations are derived from the solution of reaction-diffusion theory and Fick’s law of diffusion combined with oxide trapping mechanism under accelerated stress conditions
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Ion implantation of aluminum in 4H-SiC epilayers from 90 keV to above 1 MeV Solid State Electron. (IF 1.437) Pub Date : 2020-09-22 Ling Sang, Jinghua Xia, Rui Jin, Yaohua Wang, Yiying Zha, Fei Yang, Junmin Wu
The depth profiles of aluminum (Al) ion implantation on 4H-SiC epilayers with implantation energy range from 90 keV to above 1 MeV have been studied. The SIMS profiles show that the channeling effect is significantly reduced as the energy increases. This is attributed to the dechanneling effects due to the introduction of interstitial type defects created by preceding implanting ions under high-implantion
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Copper phthalocyanine buffer interlayer film incorporated in paper substrates for printed circuit boards and dielectric applications in flexible electronics Solid State Electron. (IF 1.437) Pub Date : 2020-09-18 Miguel A. Domínguez, José L. Sosa-Sánchez
In this work, the use of sublimated copper phthalocyanine (CuPc) organic thin films as a buffer interlayer in aluminum tracks on paper is presented for the first time. The CuPc was synthetized using a new eco-friendly synthetic protocol and the higher purity of the product turn out to be useful for the set forth applications. With the use of the CuPc buffer interlayer it is possible to enable paper
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Study of parasitic oscillation of a multi-chip SiC MOSFET circuit based on a signal flow graph model by TCAD simulation Solid State Electron. (IF 1.437) Pub Date : 2020-09-08 Hiroshi Kono, Ichiro Omura
This study presents a novel method to evaluate oscillation condition by technology computer-aided design (TCAD) simulation and is based on a signal flow graph model and a scattering parameter (S-parameter) computed using the TCAD simulation result. The parasitic oscillation of Silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs) when a short circuit occurs has been investigated
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Performance of Pyrocatechol violet and Carminic acid sensitized ZnO/CdS nanostructured photoactive materials for Dye sensitized solar cell Solid State Electron. (IF 1.437) Pub Date : 2020-09-04 Rotaba Ansir, Syed Mujtaba Shah, Naimat Ullah, Muhammad Nasir Hussain
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Effect of V2O5 interlayers in V2O5/Ge8Sb92 superlattice-like film on thermal stability and size scaling Solid State Electron. (IF 1.437) Pub Date : 2020-09-04 Yongkang Xu, Yifeng Hu, Song Sun, Xiaoqin Zhu, Tianshu Lai, Sannian Song, Zhitang Song
In this paper, the superlattice-like V2O5/Ge8Sb92 films are studied. Compared with Ge8Sb92 film, V2O5/Ge8Sb92 films have a high crystallization temperature (∼233°C), a large amorphous resistance (∼3.4×107 Ω) and good data retention temperature (∼171.2°C) for ten years. The volume change rate of V2O5/Ge8Sb92 superlattice-like film is only 1.855% during the crystallization, which can guarantee a better
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