We present a detailed study of the effect of gate-oxide-related defects (traps) on the small-signal radio frequency (RF) response of III-V nanowire MOSFETs and find that the effects are clearly identifiable in the measured admittance parameters and in important design parameters such as h21 (forward current gain) and MSG (maximum stable gain). We include the identified effects in a small-signal model

A novel PNP-triggered dynamic substrate GGNMOS (gate-grounded NMOS) structure is proposed and verified in 0.18μm salicide CMOS process. Owing to the dynamic substrate technique and imbedded PNP transistor which injects triggering current to the substrate under ESD (electrostatic discharge) events, the proposed structure features a higher robustness and a larger margin of ESD design window, besides

In this work, the electrical stability of zinc nitride (Zn3N2) Thin-film Transistors (TFTs) under negative bias stress (NBS) and positive bias stress (PBS) is presented. The Zn3N2 TFTs were fabricated on plastic substrates. Spin-on glass was used as gate dielectric. The threshold voltage shift (ΔVT) and its recovery are analyzed during a long stress time and after a period of rest. The hysteresis of

The basic relationships for a Hall plate with N non-symmetric contacts placed in an arbitrary magnetic field are a set of N-1 relationships that are necessary and sufficient for the existence of a complex electrostatic potential function. By the application of the boundary conditions, they turn into a linear system of N-1 compatibility conditions involving the terminal voltages and currents. The construction

Monolithic optoelectronic integrated circuits, OEICs are seen as key enabling technologies to minimal power loss criteria. Monolithic OEICs combine, on the same die, cutting-edge optical devices and high speed III-V electronics able to generate terahertz signal targeting beyond-5G networks. Computationally efficient compact models compatible with existing software tool and design flow are essential

In this paper, the local oxidation of SiC (LOCOSiC) isolation using pre-amorphization implantation technology is integrated into the 4H-SiC Schottky barrier didoes (SBD) fabrication to evaluate its isolation ability due to the high sensitivity of SBD to those defects induced by process. Using Ar plasma treatment, the barrier height can be centralized at ∼1.1 eV with reduced variation, which lies in

Development of accurate models for resistive switching devices (memristors) is a research topic of utmost interest. Behavioral models usually employ window functions (WFs) to capture the dependency of the resistance switching-rate on the bias conditions. Several WFs have been published so far, all of them being functions of just the state variable(s), ignoring the effect of the applied signal magnitude

In this paper, Silvaco Atlas TCAD device-circuit mixed simulation and MATLAB programming are used to compute the reverse recovery processes of silicon PIN diodes. The latter is based on solving the ambipolar diffusion equation (ADE) with the moving boundaries. The results of the ADE-based Fourier expansion (FE) and finite difference (FD) method are first compared with that from the Atlas simulation

The thermometric behavior of lateral 50-nm thin Silicon-On-Insulator (SOI) diodes are studied down to 80 K, close to liquid-nitrogen temperature. A comparison between PtSi/n-Si Schottky and implanted p-i-n diodes is presented. In this study, the intrinsic region is a moderately-doped n-type region. Key figures are extracted at room and cryogenic temperatures for each diode. A Temperature Coefficient

A spatial systematic mismatch, occurring in the integrated circuit manufacturing process, leads to differences in parameters for two or more identical devices. It is widely accepted that placing devices into symmetrical patterns reduces the spatial systematic mismatch between their parameters. In this paper, a novel method based on linear and nonlinear parameter gradient modeling for the assessment

This paper investigates the local variability in nanoscale triple-gate junctionless FinFETs utilizing an analytical symmetric and continuous compact model combined with Monte Carlo simulations. Initially, the device parameters are extracted from the experimental transfer characteristics, such as threshold voltage, ideality factor, low-field mobility, source-drain series resistance, channel length modulation

In this work, we investigated an anomalous hump in the bottom-gate amorphous-InGaZnO thin-film transistors. The hump in the subthreshold region appeared at elevated temperature and disappeared after N2 atmosphere annealing. The anomalous hump phenomenon is attributed to the existence of both main current path composed by electron and parasitic current path induced by positive charges formed by adsorbed

A comparative investigation on device characteristics of AlGaN/GaN high electron mobility transistors (HEMTs) with SiNx, SiOx, and SiON passivation by using plasma enhanced chemical vapor deposition (PECVD) technique is conducted. The electrical performance of passivated GaN HEMTs are evaluated through DC current-voltage, pulsed current-voltage, and small-signal measurements. Obvious increases of 10

A comprehensive analysis of the MOSFET subthreshold swing for a 2D subband with exponential band tail of states is first proposed. Then, a compact analytical expression for the subthreshold swing as a function of temperature is derived, well accounting for both its cryogenic temperature saturation and classical higher temperature increase. Moreover, a generalized subthreshold swing calculation applicable

The effect of different point defects in CdZnTe (CZT) crystals on carrier transport performance were discussed. The energy level and concentration of the traps were determined by the photo-induced current transient spectroscopy (PICTS). By adding the infrared light illumination into the PICTS experiment, the effect of sub-bandgap light on defects was observed. Meanwhile, several DC photoconductive

Herein, the effect of pulsed Nd:YAG laser irradiation at different fluencies in air at room temperature on the performance of n-PSi/ZnO-based UV MSM photodetector was demonstrated. Thermal and photon energies were coupled to synthesize n-PSi/ZnO NCs heterojunctions. The porous silicon (PSi) films with nano-sized pore arrays were first prepared via photoelectrochemical etching (PECE) of n-type silicon

Tunnel Field Effect Transistors (TFETs) are known to be compromised by higher order processes that downgrade their performance compared to ballistic projections. Using a quasi-analytical model that extends the chemistry based Simmons equation to include finite temperature effects, potential variations and scattering, we exhibit that non-idealities like trap-assisted tunneling and Auger generation can

Conductivity and work function of the conductive polymer, poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT:PSS), has been investigated for a top electrode of the solution-processed organic solar cells (OPV). It has been found that both conductivity and work function could be changed by adjusting the mixing ratio of different commercial grade PEDOT:PSS such as PH 1000 and AI 4083. A 2:1 vol

Investigation of the third-order intercept point, IP3 and nonlinear distortion level, NDL for pre-and post-multilayer processed GaAs pHEMTs has been accomplished by employing two-tone intermodulation distortion measurements. The third-order intercept point is a biasing, input power, frequency-dependent term, particularly related to the fundamental and third-order intermodulation distortion component

The impact of channel flattening process, dozen digital etching (DDE), which is several dozen cyclic treatments of plasma oxidation and oxide wet etching, on device performance and reliability of Ge(1 0 0) nMOSFETs has been systematically investigated. It was found that DDE improves not only electron mobility but also Positive Bias Temperature Instability (PBTI). The PBTI degradation was found related

We present experimental results for junctionless nanowire transistors (JNTs) with different gate alignments to the nanowire. Devices with nanowire source/drain extensions (NSDE) show high series source/drain resistance due to the low doped nanowire extensions, which causes lower drive current and larger device performance variations comparing with devices in which the gate electrode overlaps with the

Junctionless Transistors (JL) and One-Transistor (1T) DRAMs are concepts that come out in order to improve the scalability of logic and volatile memories, respectively. In some recent papers, Floating Body (FB) DRAMs (a class of 1T-DRAM) and JL transistors have been joined in order to propose a solution to overcome the scaling limit of the conventional 1T-1C DRAM cells. In this paper they are discussed

In this work, we report a high-performance lateral GaN Schottky barrier diode (SBD) with a low turn-on voltage (VON) of 0.39 V and low reverse current. Meanwhile we have proposed a model to comprehend the leakage current mechanism in this GaN SBDs. The reverse current transport mechanism was analyzed by temperature-dependent current–voltage (T-I-V) measurements. The results indicate that reverse current

A simple model is proposed for the Back Enhanced SOI MOSFET in triode region. This model is based on a conventional MOSFET model in series with resistors and antiparallel Schottky diodes. A robust parameter extraction method, based on lateral optimization, is also presented. The dependence of the extracted parameters with the back-gate bias is studied.

This paper presents a physics-based scalable formulation for interface trap generation in the vicinity of the emitter-base spacer oxide interface in advanced SiGe HBTs. Aging tests were performed for various emitter dimensions to investigate the scalability of the dynamics of hot-carrier degradation. An improved formulation of the bond dissociation rate is also proposed incorporating a scaling rule

Thin film transistors (TFTs) with lateral channels are limited in current density due to the design rule. For many applications with improved integration, the introduction of vertical channels reduces channel lengths while increasing current density per unit surface area. In previous works, vertical TFTs have been designed and manufactured using low-temperature polycrystalline silicon technology (T≤600°C)

Low frequency noise study is performed at deep cryogenic temperature of 10 K in p-channel gate-all-around (GAA) nanowire (NW) FETs. As expected, the carrier number fluctuations mechanism explains the flicker noise origin for conventional fixed applied drain bias. At very low applied drain biases step-like effects impact the drain current transfer characteristics. Noise measurements performed at a fixed

Neuromorphic systems are expected to be a breakthrough beyond the conventional von Neumann architecture when implementing an artificial neural network. In a neuromorphic system, analog synaptic devices store the synaptic weight values of an artificial neural network. Among various memory devices, RRAM-based synaptic device has several advantages such as excellent scaling potential with a simple two-terminal

In this paper we present a simulation study of a novel Double-Gate (DG) Ferroelectric FET (Fe-FET) architecture, exhibiting a subthreshold swing well below 60 mV/dec with a hysteresis-free behavior. The new device topology is based on the interposition of a floating gate between the ferroelectric layer and the gate oxide. The floating gate can be extended above the source and drain regions, so that

A recently developed nonlocal history dependent model for electron and hole impact ionization is used to compute the gain and the excess noise factor in avalanche photodiodes featuring heterojunctions of III-V compound semiconductors while accounting for both carriers. The model has been calibrated with measurements by our group, as well as on noise versus gain data from the literature. We explore

We report a novel switched-mode light-emitting device (LED) in an undoped ultra-thin-body (UTB) based on the electrostatically-induced electron-hole bilayer (EHB) concept. The proposed device works on the principle of formation of EHB channels by applying suitable gate biases during the charging-cycle, and their recombination during a discharging-cycle. Using TCAD simulations, we show that continuous

For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty, as well as the capability to route two additional row-wise signals on individual back planes. Experimental data are extracted from a 14 nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078 µm2 SRAM cell in order to

We investigate the robustness of a purely electrical field-free switching of a perpendicularly magnetized free layer based on SOT. The effective magnetic field which leads to deterministic switching of a rectangular as well as of a square free layer is created dynamically by a two-current pulse scheme. It is demonstrated that the switching is very robust, being insensitive to fluctuations of the write

In this paper, small- and large-signal performances of passive devices integrated on high-resistivity, trap-rich and gold-doped silicon wafers are presented and compared through measurements and simulations. The gold-doped silicon substrate was produced starting from standard silicon having a nominal resistivity of 56 Ω·cm. We show that the gold-doped substrate presents high effective resistivity and

The unique electrostatic properties of semiconductor nanowires enable the realization of novel transistor types by the possibility to use surround gate architectures resembling ideal gate electrostatic control. Nevertheless one fundamental issue of semiconducting nanowire channels is the reliable control of doping to adjust the charge carrier concentration. Indeed, as dimensions scale down the surrounding

In this paper, using numerical simulations, analytical modeling and experimental data, we validate the applicability of the transconductance-to-current ratio (gm/ID) derivative (d(gm/ID)/dVG) method for extracting the threshold voltage (VTH) in junctionless (JL) MOSFETs and show its advantages over the commonly-used transconductance derivative (or double derivative of drain current) method (dgm/dVG≡d2ID/dVG2)

We report on vertically stacked lateral nanowires (NW)/nanosheets (NS) gate-all-around (GAA) FET devices as promising candidates to obtain a better power-performance metric for logic applications for advanced sub-5 nm technology nodes, in comparison to finFETs. In addition, vertical NW/NS GAA FETs appear particularly attractive for enabling highly dense memory cells such as SRAMs (with improved read

This paper reports on resistive switching behavior observed in resistive random access memory (RRAM) devices fabricated with aluminum oxide (AlOx) and graphene oxide (GO) dielectric films, which were solution-processed under low annealing temperatures of 250 °C and 50 °C for AlOx and GO dielectric films, respectively. As representative of metal oxide and two-dimensional material, a detailed study and

Preliminary results are reported on an in-situ heater for thermal assist recovery of MOS transistor and is demonstrated in 28 nm Fully Depleted Silicon-On-Insulator (FD-SOI) Ultra-Thin Body and Buried oxide (UTBB) high-k metal gate CMOS technology. This approach consists in functionalizing the source of a MOS device. We demonstrate that it is possible to heat the device with the current flowing between

New computation schemes inspired by biological processes are arising as an alternative to standard von-Neumann architectures, to provide hardware accelerators for information processing based on a neural networks approach. Systems of frequency-locked, coupled oscillators are investigated using the phase difference of the signal as the state variable rather than the voltage or current amplitude. As

Neuromorphic computing is an emerging field of investigation for new algorithm solutions and daily life applications. We propose a novel approach to achieve an operator which uses a parasitic bipolar metal oxide semiconductor filed effect transistor combined with a capacitor and a n-type metal oxide semiconductor filed effect transistor. The resulting BIMOS-based leaky-integrate-and-fire spiking neuron

A new methodology for MOSFET characterization making use of the on-resistance characteristics Ron(Vg,Vd) = Vd/Id(Vg,Vd) and associated derivatives dRon/dVg and dRon/dVd is proposed. This approach enables to eliminate the influence of source-drain series resistance Rsd not only in linear region but also in non-linear region of MOSFET operation. Therefore, it allows for intrinsic MOSFET parameter extraction

The interest of 5G in centimeter and millimeter waves relies on large blocks of available spectra and thus increased bandwidth. At these frequencies, the dielectric and conductive losses of the substrate can greatly degrade the performances of RF circuits. With high electrical resistivity and low relative permittivity, porous silicon is an ideal candidate as a high-quality RF substrate. This paper

The pseudo-MOSFET configuration is an electrical characterization technique developed for silicon-on-insulator (SOI) wafers. The wide variety of experiments that have been performed to date have also extended recently in the study of out-of-equilibrium phenomena for bio-sensing applications. However, the lack of a full understanding of the ohmic contact behaviour between the probes and the low doped

Low frequency noise studies are performed in Si/SiGe superlattice I/O n-channel FinFETs. It was observed that the experimental noise spectra may contain additionally to flicker and white noise one or several generation recombination (GR) components. The methodology to estimate the noise parameters corresponding to the 1/f noise and each GR noise contribution was detailed. It is found that the carrier

PEALD-grown hafnia and alumina buried oxide (BOX) stacks in silicon-on-insulator (SOI) structures were produced and characterized by XTEM and pseudo-MOSFET techniques. The ferroelectric phases of hafnia were observed by XTEM and SAED. It was shown that the minimal interface states density (IFS) < 1012 cm−2 and the maximal one with a memory window MW ~1 V could be obtained by the right choice of high-k

In this work, we present a compact modeling of capacitorless A2RAM memory cell. It is obtained by combining A2RAM DC compact model with an equivalent circuit that mimics the memory state. The DC modeling is achieved by considering the A2RAM architecture as the combination of a SOI transistor in parallel with a variable-resistance bridge. The crucial aspect is the analytical description of the bridge

In this paper, we compare the evolution with temperature of the experimental characteristics of Nanonet-based Field-Effect Transistors, with a modelling of carrier transport in the percolating regime. The main electrical parameters of Nanonet-based Field-Effect Transistors that featured different nanowire densities and source-drain distances were extracted from static measurements at different temperatures

Vertical heterojunction Ge0.92Sn0.08/Ge gate-all-around (GAA) nanowire pMOSFETs fabricated with a top-down approach are reported. With optimized processes, pFETs with nanowire diameters as small as 32 nm were achieved and a decent ION/IOFF ratio of ~3 × 106 was obtained thanks to the GAA nanowire geometry, the GeSn/Ge heterostructure and NiGeSn metallization. A compensating effect between top source

In this paper, we demonstrate experimentally a novel SOI-based photodiode using electrostatic doping and fabricated in a simple, low-cost process. Unlike a conventional ion-implanted pn junction diode, the electrostatically doped devices feature extremely low reverse-bias current. When used for photodetection, our devices exhibit a dark current three decades lower than a conventional photodiode and

This work presents statistical measurements on the effects of the electrostatic coupling on the on-current, off-current and low frequency noise characteristics of individual top-tier devices, due to bottom-tier devices being biased. No inter-tier coupling impact was observed on device low-frequency noise regardless the transistor area. While for analog applications the coupling-induced ΔVt, ΔIoff and

This paper introduces the integrated generator and its design verification. In order to analyze the output performance of the thermoelectric generator, the design verification is carried out using ANSYS finite element simulation. In the simulation of traditional thermocouple structure, the maximum power factor is 8.99 × 10−3 μWcm−2K−2. In the simulation of I-shaped thermocouple structure, the maximum

The inevitable current overshoot which follows forming in filamentary RRAM devices is often perceived as a source of variability that should be minimized. This sentiment has led to efforts to curtail the overshoot by decreasing the parasitic capacitance using highly integrated 1T-1R or 1R-1R device structures. While this is readily achievable in single device test structures, it poses an intricate

We present a model based on k · p theory which is able to capture the subband structure effects present in ultra-thin strained silicon nanowires. For electrons, the effective mass and valley minima are calculated for different crystal orientations, thicknesses, and strains. The actual enhancement of the transport properties depends highly on the crystal orientation of the nanowire axis; for certain

The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation

This work reports on three speed optimized pnp bipolar phototransistors build in a standard 180 nm CMOS process using a special starting wafer. The starting wafer consists of a low doped p epitaxial layer on top of the p substrate. This low doped p epitaxial layer leads to a thick space-charge region between base and collector and thus to a high -3 dB bandwidth at low collector-emitter voltages. For

The potential of strained DOTFET technology is demonstrated. This technology uses a SiGe island as a stressor for a Si capping layer, into which the transistor channel is integrated. The structure information of fabricated samples is extracted from atomic force microscopy (AFM) measurements. Strain on the upper surface of a 30 nm thick Si layer is in the range of 0.7%, as supported by finite element

One-dimensional nanostructures such as silicon nanowires (SiNW) are attractive candidates for low power density electronic and optoelectronic devices including sensors. A new simple method for SiNW bulk synthesis[1, 2] is demonstrated in this work, which is inexpensive and uses low toxicity materials, thereby offering a safe, energy efficient and green approach. The method uses low flammability liquid

CMOS compatible, high voltage SOI MESFETs have been fabricated using a standard 3.3V CMOS process without any changes to the process flow. A 0.6μm gate length device operates with a cut-off frequency of 7.3GHz and a maximum oscillation frequency of 21GHz. There is no degradation in device performance up to its breakdown voltage, which greatly exceeds that of CMOS devices on the same process. Other

We have fabricated and tested the performance of sub-50nm gate nMOSFETs to assess their suitability for mixed signal applications in the super high frequency (SHF) band, i.e. 3-30GHz. For a 30nm×40 μm×2 device, we found f(T) =465GHz at V(ds)=2V, V(g)=0.67V, which is the highest cut-off frequency reported for a MOSFET produced on bulk silicon substrate so far. However, our measurements of f(max) and