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Bias stress stabilities of PMMA-passivated indium-gallium-zinc-oxide thin-film transistors after 100 °C steam exposure Solid State Electron. (IF 1.7) Pub Date : 2024-02-28 Yuyun Chen, Guodong Xu, Yunpeng Yu, Yi Shen
Bias stress stabilities of the polymethyl methacrylate (PMMA)-passivated IGZO thin-film transistors (TFTs) after being exposed in a normal and harsh (100 °C steam) environment were studied, in order to comprehensively evaluate protection effects of PMMA. In a normal environment, the PMMA-passivated TFTs exhibited normal switching characteristics and electrical stabilities. However, the switching characteristics
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Investigation of low to high-dose gamma-ray (γ-ray) radiation effects on indium-zinc-oxide (IZO) thin film transistor (TFT) Solid State Electron. (IF 1.7) Pub Date : 2024-02-28 Do-Kywn Kim, Dong-Seok Kim, Tae-Eon Kim, Min-Ju Kim, Seung Heon Shin
This paper investigates the impact of gamma-ray (γ-ray) radiation at doses of 100 krads and 1,000 krads on amorphous indium-zinc-oxide (IZO) thin-film transistors (TFTs). The IZO channel's properties are analyzed using X-ray photoelectron spectroscopy (XPS) before and after radiation. Following 100 krads exposure, the oxygen vacancy (V) peak in the IZO channel increases from 41.8 % to 59.4 % due to
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Fabrication of garnet solid electrolytes via sputtering for solid-state batteries Solid State Electron. (IF 1.7) Pub Date : 2024-02-24 Shu-Yi Tsai, Kuan-Zong Fung
In this study, the deposition of LiLaZrO (LLZO) thin films onto MgO substrates was successfully achieved using the radio frequency magnetron sputtering technique. The deposition process was carried out at various substrate temperatures to investigate their influence on the film properties The as-deposited films were initially amorphous; however, they could be crystallized into the cubic phase by increasing
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Analysis and 3D TCAD simulations of single-qubit control in an industrially-compatible FD-SOI device Solid State Electron. (IF 1.7) Pub Date : 2024-02-23 Pericles Philippopoulos, Félix Beaudoin, Philippe Galy
In this study, 3D simulations are introduced to analyze electric-dipole spin resonance (EDSR) for a spin qubit defined in a -node Ultra-Thin Body and Buried oxide (UTBB) Fully-Depleted Silicon-On-Insulator (FD-SOI) device operated at cryogenic temperatures. The device under consideration is designed to be compatible with STMicroelectronics’ standard fabrication techniques. The simulations predict the
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Process optimization of titanium self-aligned silicide formation through evaluation of sheet resistance by design of experiment methodology Solid State Electron. (IF 1.7) Pub Date : 2024-02-17 In-Chi Gau, Yao-Wen Chang, Giin-Shan Chen, Yi-Lung Cheng, Jau-Shiung Fang
A low-resistivity titanium silicide (TiSi) is crucial as a gate and source/drain material in microelectronic device fabrication, offering notable properties to enhance device performance. This study aims to experimentally determine the optimum process parameters, including arsenic doping dosage, titanium thickness, and two-step rapid thermal process (RTP) temperature, for the sheet resistance of titanium
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Characterization of DC performance and low-frequency noise of an array of nMOS Forksheets from 300 K to 4 K Solid State Electron. (IF 1.7) Pub Date : 2024-02-16 R. Asanovski, A. Grill, J. Franco, P. Palestri, H. Mertens, R. Ritzenthaler, N. Horiguchi, B. Kaczer, L. Selmi
The DC and low-frequency noise performance of an array of 800 parallel Forksheet MOSFETs were investigated by performing measurements over a wide temperature range from 300 K to 4 K. The array structure allowed to measure a representative average performance of the devices and provided a large effective area for 1/f noise analysis. Results showed an improvement in the saturation drain current when
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Mechanisms of negative bias instability of commercial SiC MOSFETs observed by current transients Solid State Electron. (IF 1.7) Pub Date : 2024-02-16 Mayank Chaturvedi, Daniel Haasmann, Philip Tanner, Sima Dimitrijev
This article explains the mechanisms of negative bias instability in commercial n-channel SiC metal–oxide semiconductor field-effect transistors (MOSFETs) by analysis of transient gate currents. The current–voltage measurements were performed at different temperatures along with capacitance–voltage measurements to characterise hole trapping and de-trapping in planar SiC MOSFETs. The experimental results
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Low-Frequency Noise Characterization of Positive Bias Stress Effect on the Spatial Distribution of Trap in β-Ga2O3 FinFET Solid State Electron. (IF 1.7) Pub Date : 2024-02-15 Hagyoul Bae, Geon Bum Lee, Jaewook Yoo, Khwang-Sun Lee, Ja-Yun Ku, Kihyun Kim, Jungsik Kim, Peide D. Ye, Jun-Young Park, Yang-Kyu Choi
The reliability of a -GaO thin-film field-effect transistor is investigated under positive-bias stress (PBS). The transistor has a tri-gate structure with a gate dielectric of AlO. By characterizing low-frequency noise (LFN), the spatial distribution of trap in the gate dielectric was quantitatively extracted. The measured power spectral density (PSD) followed a 1/f-shape due to trapping and de-trapping
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Impact of passivation layer on the subthreshold behavior of p-type CuO accumulation-mode thin-film transistors Solid State Electron. (IF 1.7) Pub Date : 2024-02-13 Qi Chen, Xi Zeng, Denis Flandre
In this work, models of p-type CuO metal-oxide- semiconductor (MOS) capacitor and thin-film transistors (TFTs) are established using numerical simulation tools and compared with experimental data, to investigate the impact of a passivation layer on the TFT subthreshold behavior. Simulated transfer curves and hole concentrations of back-gated CuO TFT with 10 μm channel length confirm the experimental
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Experimental study of time-dependent dielectric degradation by means of random telegraph noise spectroscopy Solid State Electron. (IF 1.7) Pub Date : 2024-02-08 Nishant Saini, Davide Tierno, Kristof Croes, Valeri Afanas’ev, Jan Van Houdt
Time-dependent dielectric breakdown (TDDB) is commonly used to assess dielectric failures. However, TDDB provides limited insights into the physics of dielectric degradation. In this paper, we explore the potential of random telegraph noise (RTN) spectroscopy to study the physics of dielectric breakdown. RTN is a fluctuation in the dielectric leakage current due to capture/emission of injected electrons
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First-principles screening for sustainable OTS materials Solid State Electron. (IF 1.7) Pub Date : 2024-02-03 S. Clima, D. Matsubayashi, T. Ravsher, D. Garbin, R. Delhougne, G.S. Kar, G. Pourtois
Chalcogenides Ovonic Threshold Switching (OTS) chalcogenide materials have suitable electronic properties for two-terminal selector application. To reduce the use of toxic elements, there is a need to replace As and Se of the presently-used OTS materials with environmentally friendly OTS materials. In an effort to accelerate the discovery of such materials, we predicted electrical device parameters
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Hot-carrier induced degradation of Ge/STI interfaces in Ge-on-Si junction devices Solid State Electron. (IF 1.7) Pub Date : 2024-02-02 Solomon Musibau, Jacopo Franco, Artemisia Tsiara, Ingrid De Wolf, Kristof Croes
The degradation of Ge junctions epitaxially grown within shallow trench isolation (STI) on Si is investigated for geometries with different Area-to-Perimeter (A/P) ratios under constant-voltage stress. We show that the reverse-bias relative current shift () exhibits a two component behaviour ascribed to the interplay between charge trapping in (pre-existing) traps and generation of new defects mostly
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Characterization of trap density in Indium-Gallium-Zinc-Oxide thin films by admittance measurements in multi-finger MOS structures Solid State Electron. (IF 1.7) Pub Date : 2024-02-02 Hongwei Tang, Attilio Belmonte, Dennis Lin, Valeri Afanas'ev, Patrick Verdonck, Adrian Chasin, Harold Dekkers, Romain Delhougne, Jan Van Houdt, Gouri Sankar Kar
We perform trap density (D) extraction through admittance measurements on amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin films using multi-finger MOS structures. We investigate the impact of channel length (L) on C-V and G-V characteristics and demonstrate a reliable trap density extraction method in short channel devices. The method is validated for pure and Magnesium-doped a-IGZO (Mg:IGZO). The
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Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures Solid State Electron. (IF 1.7) Pub Date : 2024-02-01 Michelly de Souza, Antonio Cerdeira, Magali Estrada, Mikaël Cassé, Sylvain Barraud, Maud Vinet, Olivier Faynot, Marcelo A. Pavanello
This paper presents a comprehensive experimental analysis of the gate-induced drain leakage (GIDL) in two-level stacked nanowire SOI nMOSFETs for operating temperatures between 300 K and 580 K. Devices with different channel lengths and fin widths were measured. The results show that temperature rise increases the GIDL current for stacked nanowire transistors and its dependence on nanowire width. For
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Preconditioning of Ohmic p-GaN power HEMT for reproducible Vth measurements Solid State Electron. (IF 1.7) Pub Date : 2024-01-30 L. Ghizzo, D. Trémouilles, F. Richardeau, G. Guibaud
The fluctuation of the threshold voltage (Vth) presents a challenge while monitoring electrical drift in reliability studies of GaN HEMTs. While technologies, such as ohmic p-GaN, may lessen Vth fluctuations, the issue of recoverable charge trapping still remains. Therefore, it is crucial to adopt novel characterization methods when conducting reliability studies, in order to measure intrinsic changes
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Influence of gate-source/drain overlap on FeFETs Solid State Electron. (IF 1.7) Pub Date : 2024-01-26 Changha Kim, Dong-Oh Kim, Woo Young Choi
The influences of gate-source/drain overlap on ferroelectric field-effect transistors (FeFETs) are investigated with various gate-source/drain overlap lengths (Lov’s) and doping concentrations of the gate-source/drain overlap region (Dov’s). In contrast to conventional metal-ferroelectric-insulator-semiconductor (MFIS) FeFETs, a metal layer between a ferroelectric and an insulator layer allows overlap
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Improved electrical performance of InAlN/GaN high electron mobility transistors with forming gas annealing Solid State Electron. (IF 1.7) Pub Date : 2024-01-19 Siheng Chen, Peng Cui, Handoko Linewih, Kuan Yew Cheong, Mingsheng Xu, Xin Luo, Liu Wang, Jiuji Sun, Jiacheng Dai, Jisheng Han, Xiangang Xu
The surface electronic states and defects of gallium nitride based high-electron-mobility transistors (HEMTs) play a critical role affecting channel electron density, electron mobility, leakage current, radio frequency (RF) power output and power added efficiency of devices. This article demonstrates the improved surface properties of InAlN/GaN HEMTs through forming gas (FG) annealing, resulting in
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Deep Spiking Neural Networks with Integrate and Fire Neuron Using Steep Switching Device Solid State Electron. (IF 1.7) Pub Date : 2024-01-12 Sung Yun Woo, Sangyeon Pak, Sung-Tae Lee
Deep learning has shown impressive capabilities in tasks like speech recognition and image classification. However, modern deep neural networks often demand a significant number of weights and extensive computational resources, creating efficiency challenges for applications on edge devices. To address these issues, researchers have introduced deep spiking neural networks (DSNNs) that leverage specialized
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Quantum information processing in electrically defined Silicon triple quantum dot systems Solid State Electron. (IF 1.7) Pub Date : 2024-01-15 Ji-Hoon Kang, Hoon Ryu
Quantum bits (qubits) operations in electrically defined Silicon (Si) triple quantum dots (TQDs) are computationally investigated to elevate the potential of TQD structure as a platform for quantum information processing. Employing a realistic Si/Si-germanium heterostructure as a target model, device simulations are conducted to secure an initialized qubit state. Basic programmability is verified through
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Voltage ramp stress based lifetime-prediction model of advanced Al-doped HfO2 dielectric for 2.5D MIMCAPs Solid State Electron. (IF 1.7) Pub Date : 2024-01-15 Corinna Fohn, Emmanuel Chery, Kristof Croes, Michele Stucchi, Valeri Afanas’ev
The reliability of an Al-doped HfO2 dielectric used in a high density 2.5D MIMCAP is investigated by constant voltage stress (CVS) and voltage ramp stress (VRS) measurements. The good agreement of the results from the two techniques allows to propose a model for lifetime prediction based on the breakdown characteristics. The extracted activation energy shows a voltage dependence associated with a change
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Performance potential of transistors based on tellurium nanowire arrays: A quantum transport study Solid State Electron. (IF 1.7) Pub Date : 2024-01-09 Ning Yang, Jing Guo
Low-dimensional nanomaterials provide promising material platforms for aggressively scaled transistor technologies. We assess the performance potential of transistors based on an array of Tellurium nanowires (TNWs), by parameterizing a machine-learning (ML) tight-binding model with quantum transport device simulations. It has been shown that a transistor based on a parallel array of carbon nanotubes
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Silicon nitride resistance switching MIS cells doped with silicon atoms Solid State Electron. (IF 1.7) Pub Date : 2024-01-03 A. Mavropoulis, N. Vasileiadis, C. Bonafos, P. Normand, V. Ioannou-Sougleridis, G. Ch. Sirakoulis, P. Dimitrakis
Stoichiometric SiNx layers (x = [N]/[Si] = 1.33) are doped with Si atoms by ultra-low energy ion implantation (ULE-II) and subsequently annealed at different temperatures in inert ambient conditions. Detailed material and memory cells characterization is performed to investigate the effect of Si dopants on the switching properties and performance of the fabricated resistive memory cells. In this context
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Bismuth tungstate nanosheets sensors based on Temkin adsorption model for triethylamine detection Solid State Electron. (IF 1.7) Pub Date : 2023-12-28 Zhongyuan Wu, Fengyu Luo, Xiaohong Zheng, Jin Liu
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A novel dual-directional DTSCR in twin-well process for ultra-low-voltage ESD protection Solid State Electron. (IF 1.7) Pub Date : 2023-12-20 Xiaofeng Gu, Jian Xu, Hailian Liang, Junliang Liu, Dong Wang, Shurong Dong, Wen Lei, Juin J. Liou
By embedding additional NPN- and PNP- type bipolar junction transistors into a diode-triggered silicon-controlled rectifier (DTSCR) with single-directional ESD protection, we propose and implement a novel dual-directional DTSCR (DDTSCR) by using the twin-well process in a 0.18-µm CMOS process that provides highly efficient ultra-low-voltage ESD protection. Compared to conventional DTSCRs, the failure
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A unified core model of double-gate and surrounding-gate MOSFETs for circuit simulation Solid State Electron. (IF 1.7) Pub Date : 2023-12-21 Luigi Colalongo, Simone Comensoli, Anna Richelli
This paper presents a new core compact model of double-gate (DGFET) and surrounding-gate (SGFET) MOSFETs for circuit simulations. The current and the terminal charges are continuous with high computation efficiency and accuracy. Despite its accuracy, it retains the same simplicity of the industry standard transistors models. The drain current is worked out without invoking the charge-sheet approximation
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SPICE Model of MoS2/p-Si Photodiode Solid State Electron. (IF 1.7) Pub Date : 2023-12-14 Feng Li, Shubin Zhang, Yanfeng Jiang
Molybdenum disulfide (MoS2) 2D-material is considered as one of potential candidates for next generation optoelectronic devices due to its tunable bandgap, relatively high carrier mobility, and good light absorption, etc.. From the perspective of circuit simulation and system verification, an equivalent circuit model of MoS2/p-Si photodiode is required. In the paper, the optical response and the carrier
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Physics-based compact current model for Schottky barrier transistors at deep cryogenic temperatures including band tail effects and quantum oscillations Solid State Electron. (IF 1.7) Pub Date : 2023-12-12 Christian Roemer, Nadine Dersch, Ghader Darbandy, Mike Schwarz, Yi Han, Qing-Tai Zhao, Benjamín Iñíguez, Alexander Kloes
This paper presents a compact model for the DC current of Schottky barrier field-effect transistors at deep cryogenic temperatures, close to absolute zero kelvin. The proposed model is physics based and calculates the injection current over a device’s Schottky barriers, by considering physical effects at these temperatures (e.g. quantum oscillations, band tail effect, phonon-assisted tunneling, etc
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Influence of interface traps position along channel in the low-frequency noise of junctionless nanowire transistors Solid State Electron. (IF 1.7) Pub Date : 2023-12-03 Rodrigo T. Doria, Marcos P. Picoli Junior, Sylvain Barraud, Renan Trevisoli
Differently from inversion mode MOS transistors, Junctionless Nanowires surface potential presents a strong dependence on the gate and drain biases, when the devices are biased in partial depletion. For that reason, the position of interface trap centers along the channel could have a significant influence on the electrical characteristics of the devices. Therefore, this work has evaluated how the
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p-type NiOx ultrathin film as highly efficient hole extraction layer in n-type PbS quantum dots based NIR photodiode Solid State Electron. (IF 1.7) Pub Date : 2023-12-02 Louis David Mohgouk Zouknak, Mickael Gros-Jean, Serge Blonkowski, Charles Leroux, Gerard Ghibaudo
Recently, the development of zero-dimensional (0D) materials has experienced significant growth. Among them, PbS colloidal quantum dots (CQDs) have received special attention due to their outstanding properties, including tunable optical absorption ranging from 600 to 2600 nm (size dependent bandgap) and easy solution synthesis. PbS CQDs are considered as one of the most promising materials for the
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Resolving the discrepancy between coercive voltages extracted from C-V and P-V measurements in a ferroelectric capacitor Solid State Electron. (IF 1.7) Pub Date : 2023-12-06 Shankha Mukherjee, Jasper Bizindavyi, Sergiu Clima, Mihaela I. Popovici, Valeri V. Afanas'ev, Jan Van Houdt
In this work, we study hafnium zirconate (HZO) based ferroelectric (FE) capacitors (FeCAP) intended for random access memory and compute-in-memory (CiM) applications. We show that there exists a discrepancy between the coercive voltages (VC) extracted from a small-signal capacitance–voltage (C-V) measurement ({VC}CV) and dynamic polarization-voltage (P-V) measurement ({VC}PV): |{VC}CV| < |{VC}PV|.
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Study of electrical transport properties in split-gate AlGaN/GaN heterostructure field-effect transistors Solid State Electron. (IF 1.7) Pub Date : 2023-12-03 Heng Zhou, Yuanjie Lv, Chao Liu, Ming Yang, Zhaojun Lin, Yang Liu, Mingyan Wang
In this study, we fabricated two similar split-gate AlGaN/GaN heterostructure field-effect transistors (SG AlGaN/GaN HFETs). However, minor variations in structural design resulted in substantial differences in the current–voltage characteristics. The mechanism of current modulation in the open region of the HFET can be explained by the fringe electric field (FEF) effect and the polarization Coulomb
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Analog resistive switching behavior in BiCoO3 thin film Solid State Electron. (IF 1.7) Pub Date : 2023-12-01 Manisha Kumari, Kajal Jindal, Sandeep Munjal, Monika Tomar, Pradip K. Jha
In this work, resistive switching behaviour of BiCoO3 (BCO) thin film has been reported. The BCO thin film was grown on ITO coated corning glass substrate using pulsed laser deposition (PLD) technique at a substrate temperature of 550 ˚C in the presence of oxygen ambient pressure of 200 mT. The Al/BCO/ITO device was found to exhibit analog bipolar resistive switching behaviour, as no electroforming
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The effects and mechanisms of 2 MeV proton irradiation on high bias conditions of InP/InGaAs DHBTs Solid State Electron. (IF 1.7) Pub Date : 2023-12-01 Runkun Liu, Bo Mei, Yongbo Su, Feng Yang, Jialin Zhang, Chen Zhang, Huanqing Yun, Yi Sun, Haiming Zhang, Zhi Jin, Yinghui Zhong
In this work, a 2 MeV proton irradiation experiment has been carried out on self-fabricated InP/InGaAs heterojunction bipolar transistors (HBTs) with fluence of 5 × 1013 H+/cm2 and 1 × 1014 H+/cm2. The degradation and mechanisms have systematically been studied under different bias conditions. The irradiated InP-based HBTs have suffered more sever degradation at low and high bias voltages with larger
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An enzymatic glucose biosensor using the BESOI MOSFET Solid State Electron. (IF 1.7) Pub Date : 2023-11-15 L.S. Yojo, R.C. Rangel, P.H. Duarte, K.R.A. Sasaki, J.A. Martino
A reconfigurable transistor glucose biosensor was fabricated using the BESOI MOSFET structure. Glucose oxidase enzyme was immobilized on the sensitive regions of the device to specifically detect glucose. The experimental measurements showed a positive linear relationship between the sensitivity and the glucose solution concentration, in the measured range (0–200 mM). The maximum value of 0.52 was
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1540 V 21.8mΩ·cm2 4H-SiC lateral MOSFETs with DOUBLE RESURFs for power integration applications Solid State Electron. (IF 1.7) Pub Date : 2023-11-13 Li Liu, Jue Wang, Zhengyun Zhu, Hongyi Xu, Qing Guo, Na Ren, Kuang Sheng
This work demonstrates 4H-SiC lateral MOSFETs for power integrated circuits application designed with DOUBLE-RESURFs (reduced surface field) technology. Optimized by device simulation, the P-top RESURF dose was designed to be 10 × 1012cm−2. Various RESURF lengths (LRESURF) have been employed in the device manufacturing. As the result, the blocking capability of the fabricated device is significantly
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Investigation and Modeling of Multifrequency CV characteristics for 10-nm Bulk FinFETs at Cryogenic Temperatures Solid State Electron. (IF 1.7) Pub Date : 2023-11-11 Sumreti Gupta, Asifa Amin, Reinaldo A. Vega, Abhisek Dixit
In this work, multifrequency capacitance–voltage characteristics have been investigated from 300K to 10K for high-k HfO2-based 10-nm bulk n-channel FinFETs. The dispersion observed in the accumulation region for the multifrequency capacitance characteristics with respect to temperature is explored taking into consideration the temperature dependence of border traps, series resistance, tunneling current
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SOS Pseudo-FeFETs after Furnace or Rapid Annealings and Thining by Thermal Oxidation Solid State Electron. (IF 1.7) Pub Date : 2023-11-07 V.A. Antonov, F.V. Tikhonenko, V.P. Popov, A.V. Miakonkikh, K.V. Rudenko, V.A. Sverdlov
The silicon-on-sapphire (SOS) pseudo-MOSFETs with high-k buried hafnium dioxide interlayer (IL) were investigated after the hydrogen induced Si and HfO2 layer transfer on c-sapphire wafers and annealing at 600-1100 °C. HRTEM, GIXRD and Raman measurements were used to reveal the hafnia phases for furnace and rapid thermal annealings (FA and RTA).
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Novel crossbar array of silicon nitride resistive memories on SOI enables memristor rationed logic Solid State Electron. (IF 1.7) Pub Date : 2023-11-07 N. Vasileiadis, A. Mavropoulis, I. Karafyllidis, G. Ch. Sirakoulis, P. Dimitrakis
In this work, the fabrication of crossbar arrays of silicon nitride resistive memories on silicon-on-insulator substrate and their utilization to realize multi-rationed logic circuits are presented. Typical electrical characterization of the memristors revealed their ability of multi-state operation by the presence of 12 well separated resistance levels. Through a dedicated modeling and fitting procedure
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Effect of addition of indium oxide layer on all-inorganic perovskite solar cells Solid State Electron. (IF 1.7) Pub Date : 2023-11-03 Xiao Wang, Chaofan Zheng, Bei Liu, Jinghua Zhou, Qing Zhang, Zelin Jia, Tao Xue, Kunping Guo, Jin Huang, Fanghui Zhang
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Statistical modeling of degradation behavior in Split-Gate Non-Volatile memory devices Solid State Electron. (IF 1.7) Pub Date : 2023-11-04 S. Mei, L. Luo, K. Shubhakar, N. Raghavan, K.L. Pey
A comprehensive modeling approach combining Kinetic Monte Carlo method and the Finite Element Method is presented in this study for simulating the degradation behavior of split gate non-volatile memory. The oxide layer between erase gate and floating gate is proved to be the weakest link, caused by the intensive electrical field enhancement during the erase process. The clustering effect shown by the
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Analogies for Dirac fermions physics in graphene Solid State Electron. (IF 1.7) Pub Date : 2023-11-03 Daniela Dragoman, Mircea Dragoman
Graphene monolayer was the first solid-state material to show a linear dispersion relation around the corners of the first Brillouin zone. This unusual dispersion relation led to specific physical phenomena, as well as to the possibility of testing ultra-relativistic particle theories. Since graphene discovery, many attempts have been made to mimic its properties in other solid-state structures as
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Technology and design study of 3D physics-based inductor on FDSOI in GHz-range Solid State Electron. (IF 1.7) Pub Date : 2023-11-03 Franck Sabatier, Cédric Durand, Dominique Drouin, Michel Pioro-Ladrière, Fabien Ndagijimana, Philippe Galy
This study investigates several ways to improve the quality factor and (or) the inductance by evaluating the possibility to add magnetic materials around an inductor integrated into the BEOL of CMOS technology. Performance boost evaluation is done through 3D numerical simulations of an inductor integrated on an SOI substrate made in a 28 nm UTBB FDSOI technology. The choice of materials and their design
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Investigating the impact of quantum confinement on the THz behavior of Nanoscale FinFETs Solid State Electron. (IF 1.7) Pub Date : 2023-10-29 Mathias Pech, Dirk Schulz
The stationary and transient behavior of a 3 nm wide on-insulator type FinFET is investigated. The focus is laid on the evaluation and characterization of the effect of quantum confinement on the amplifier behavior. The high computational burden related to the time-resolved analysis of such three-dimensional simulations is dealt with by applying a mode-space approach onto a Quantum Liouville-type Equation
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Performance optimization of epitaxial-layer based Si/SiGe hetero-junction area scaled tunnel FET label-free biosensors considering steric hindrance Solid State Electron. (IF 1.7) Pub Date : 2023-11-02 Sourabh Panwar, Shobhit Srivastava, Shashidhara M., Deepak Joshi, Abhishek Acharya
This paper explores Si/SiGe hetero-junction dielectrically modulated area-scaled tunnel FET (DM-ASTFET) for label-free bio-sensing applications. The proposed sensor can detect bioanalytics such as protein, APTES, Choline Oxidase and Uricase. We have also investigated the influence of quantum confinement on the proposed device, and the onset voltage shifted by 0.1–0.3 V, as reported, without affecting
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Modeling the impact of incomplete conformality during atomic layer processing Solid State Electron. (IF 1.7) Pub Date : 2023-11-02 Tobias Reiter, Luiz Felipe Aguinsky, Frâncio Rodrigues, Josef Weinbub, Andreas Hössinger, Lado Filipovic
Atomic layer processing (ALP) is a modern fabrication technique for the deposition or etching of materials, which provides precise control of film thickness, composition, and conformality on a nanometer scale. This makes it crucial for the fabrication of high aspect ratio (HAR) structures, such as 3D NAND memory stacks, as its self-limiting nature provides enhanced conformality compared to traditional
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Low contact resistance of NiGeSn on n-GeSn Solid State Electron. (IF 1.7) Pub Date : 2023-11-02 Jingxuan Sun, Yi Han, Yannik Junk, Omar Concepción, Jin-Hee Bae, Detlev Grützmacher, Dan Buca, Qing-Tai Zhao
A systematic investigation of the NiGeSn formation and its contact resistivity with GeSn semiconductors are studied. The method of investigation is based on the circular transmission line measurement (CTLM) geometry. The optimum NiGeSn formation temperature is 325 °C, offering a lower contact resistivity of 4.15 × 10−5 Ω·cm2 on n-GeSn. The elemental diffusion mechanism during the NiGeSn formation is
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Electrical parameters and low-frequency noise of AlGaN/GaN high-electron mobility transistors with different channel orientation Solid State Electron. (IF 1.7) Pub Date : 2023-11-02 Maria Glória Caño de Andrade, Carlos Roberto Nogueira, Nilton Graciano Júnior, Rodrigo T. Doria, Renan Trevisoli, Eddy Simoen
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Opportunity to achieve an efficient SiC/SiO2 interface N passivation by tuning the simultaneous oxidation modes during the SiC surface nitridation in N2 + O2 annealing Solid State Electron. (IF 1.7) Pub Date : 2023-11-02 Tianlin Yang, Koji Kita
We investigated a possible guideline to design the SiC surface nitridation process for an efficient interface N passivation in high-temperature N2 + O2 annealing, based on the understandings of SiC surface nitridation kinetics. Based on the findings of the time-dependent transition of the simultaneous SiC surface oxidation mode from passive to active during the annealing with reduced O2 partial pressure
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Modeling and simulation of successive breakdown events in thin gate dielectrics using standard reliability growth models Solid State Electron. (IF 1.7) Pub Date : 2023-10-28 E. Miranda, F.L. Aguirre, E. Salvador, M.B. González, F. Campabadal, J. Suñé
The application of constant electrical stress to a metal–insulator-semiconductor (MOS) or metal–insulator-metal (MIM) structure can generate multiple breakdown events in the dielectric film. Very often, these events are detected as small jumps in the current–time characteristic of the device under test and can be treated from the stochastic viewpoint as a counting process. In this letter, a wide variety
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Evidence of trapping and electrothermal effects in vertical junctionless nanowire transistors Solid State Electron. (IF 1.7) Pub Date : 2023-10-31 Y. Wang, C. Mukherjee, H. Rezgui, M. Deng, J. Müller, S. Pelloquin, G. Larrieu, C. Maneux
Understanding trap dynamics and formation of localized temperature hot-spots due to self-heating is crucial for the design optimization of emerging vertical junctionless nanowire transistors (VNWFET). This work investigates the operation of an 18 nm VNWFET technology, for the first time, leveraging pulsed current–voltage measurements. Results indicate increased trap activity as well as electrothermal
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Thermal desorption from zeolite layer for VOC detection Solid State Electron. (IF 1.7) Pub Date : 2023-10-28 G. Oliva, A.S. Fiorillo, T. Antonić Jelić, S. Valić, S.A. Pullano
Volatile organic compounds (VOCs) are being considered for a wide range of applications, since they provide information on specific processes (e.g., metabolic processes in humans and plants). To date, environmental VOCs detection can be accomplished with low selectivity using both portable photoionization techniques or using gold standard laboratory techniques (e.g., gas and liquid chromatography,
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TCAD simulation methodology of total ionizing dose effects for PDSOI transistor with a hump characteristic Solid State Electron. (IF 1.7) Pub Date : 2023-10-30 J. Lomonaco, N. Rostand, S. Martinie, A. Bournel
In this work, we developed a simulation methodology with the Synopsys Sentaurus Technology Computer Aided Design (TCAD) suite in order to analyze Total Ionizing Dose (TID) effects in 65 nm Body Contacted (BC) Partially Depleted (PD) SOI technology for a MOS transistor including a hump characteristic induced by an unknown parasitic transistor.
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Detailed analysis of electrical components on a layered wafer via the AC pseudo-MOS method Solid State Electron. (IF 1.7) Pub Date : 2023-10-29 Yifan Yuan, Shingo Sato
This letter discusses electrical components on a silicon-on-insulator (SOI) wafer employing the AC pseudo-metal-oxide-semiconductor (MOS) method, following the removal of contact resistance between metal probes and the SOI layer of the wafer. This study attempts to clarify that the contact resistance between the back surface of the wafer and measurement chuck exerts a substantial impact on the repeatability
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Efficient Post-Processing techniques for enhancing performance of PeLEDs Solid State Electron. (IF 1.7) Pub Date : 2023-10-24 Shi Jing, Wang Liyuan, Sanam SaeidNahaei
Metal halide perovskites have gained significant attention as a hopeful research area for developing perovskite light-emitting diodes. Achieving high-quality and cost-effective perovskite light-emitting diodes is crucial for their commercialization. This report focuses on an effective postprocessing approach that enhances the performance of perovskite emissive thin films without the need for vacuum
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Bottom interface passivation with benzylamine thiocyanate for improving the performance of inverted perovskite solar cells Solid State Electron. (IF 1.7) Pub Date : 2023-10-20 Chengyi Duan, Minglin Zhao, Ramy El-Bashar, S.S.A. Obayya, Mohammed Hameed, Jun Dai
The organic–inorganic hybrid perovskite materials have attracted a lot of attention in the photovoltaics field due to their excellent photovoltaic properties and simple preparation process in recent years. The well-known hole transport layer PTAA in the inverted perovskite solar cells (PSCs) is prone to trigging the nonradiative recombination and limiting the device performance. Here, we added benzylamine
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A comparative study of noise performance for InP HEMT Solid State Electron. (IF 1.7) Pub Date : 2023-10-19 Ao Zhang, Jianjun Gao
A comparative study to determine the scaling rules of noise model parameters for InP HEMT devices between 90 nm and 70 nm process is proposed in this paper. The expressions of noise model parameters in terms of four noise parameters are also derived. Both gate length and gate width scalable rules of the gate and drain noise model parameters (P and R) are discussed between 90 nm and 70 nm devices. Good