Thin films with HfO2/Al2O3 laminated structure were prepared by the ALD method in this paper. Typical bipolar resistance switching characteristics were observed in the Pt/HfO2/Al2O3/TiN structure device. The samples were characterized by X-ray photoelectron spectroscopy (XPS) and atomic force microscopy (AFM). The effects of dielectric thickness and different test temperatures on the electrical performance

In this paper, high-power up to 4000 mW electro-mechanical behavior of a capacitive micro-electromechanical systems (MEMS) microwave power sensor using cantilever beam is investigated. Due to residual stress gradients, the power sensor is proposed for a warped cantilever beam connected to coplanar waveguide (CPW) structure. The proposed sensor is fabricated using the GaAs monolithic microwave integrated

Cowell’s Method of extracting barrier heights of top and bottom electrode metals in asymmetric Metal-Insulator-Metal tunneling diodes exhibiting Fowler-Nordheim tunneling is successfully automated. Pt-Al2O3-TiN MIM diodes with 5-nm insulator thickness are used in demonstration. Condition assuring successful application of Cowell’s method and its automation is discussed.

Spin-transfer torque magnetic random access memory (STT-MRAM) is one of the most promising candidates for “universal memory” with the ultra-fast access speed, radiation resistance and theoretically unlimited endurance. However, there are many practical aspects that could degrade the life-time of STT-MRAM. In this paper, degradation on the life-time of the STT-MTJ device is observed experimentally,

We have investigated the effects of a silicon nitride (SiNx) passivation process using plasma-enhanced chemical vapor deposition (PECVD) on a ultra-thin-barrier AlGaN/GaN heterostructure field-effect transistors (HFETs). The bulk charge characteristics of the PECVD SiNx films were dependent on the film deposition conditions, which strongly influenced the sheet resistance (Rsh) and flat-band voltage

ZnO thin-film transistors (TFTs) with scaled channel lengths of 10 μm, 5 μm, 4 μm, and 2 μm exhibit increasing intrinsic channel electron mobility at a gate bias of 10 V (15 V) from 0.782 cm2/Vs (0.83 cm2/Vs) in the 10 μm channel length TFT to 8.9 cm2/Vs (19.04 cm2/Vs) for the channel length scaled down to 2 μm. Current-voltage measurements indicate an n-type channel enhancement mode transistor operation

This paper presents an investigation of the abnormal hump phenomenon in amorphous indium gallium zinc oxide thin–film transistors under positive gate bias and temperature stress (PBTS). During PBTS, the current-voltage curve shows a severe hump and an abnormal double hump. Additional stress tests were conducted under long–term and low–temperature PBTS and current stress (CS), then the capacitance–voltage

Ge-rich GeSbTe (GST) alloys are attracting Phase Change Materials for future memories as their higher crystallization temperature offers an extended range of applications. We have studied the electrical characteristics of PCM cells using such alloys as active layers. We show by impedance spectroscopy that the cells in the RESET (amorphous) state are not only resistive but also exhibit a capacitive

The modern electronic devices have been scaled down significantly. The scaling rules would dictate higher doping concentrations which lead us to consider the degeneracy in the calculations. One of the semiconductor device quantities that would be impacted by considering the degeneracy is the Einstein Relation. The commonly used formula of Einstein Relation assumes that it is constant and independent

The transition region between the active area and the edge termination of silicon carbide (SiC) MOSFET is either used to place a poly-silicon gate runner (G-MOS) or electrically contacted to the source potential (S-MOS), which is studied experimentally and by TCAD simulation in this work. The simulation results indicate that the transition region of G-MOS can effectively alleviate the propagation delay

Present work has used Green’s function approach to derive a two-dimensional analytical model of the double gate (DG) MOSFET at the subthreshold regime of operation that considers the effect of inevitable source/drain (S/D) lateral Gaussian doping profile. The non-integrable Gaussian term has been converted into an integrable function for accurate Fourier coefficient calculation which is then used to

A novel PNP-triggered dynamic substrate GGNMOS (gate-grounded NMOS) structure is proposed and verified in 0.18 μm salicided CMOS process. Owing to the dynamic substrate technique and imbedded PNP transistor which injects triggering current to the substrate under ESD (electrostatic discharge) events, the proposed structure features a small trigger voltage, a small snapback region, a high robustness

Metal-insulator-metal (MIM) diode is considered as a promising candidate for various high frequency applications owing to its tunneling dominant ultra-fast switching time. The zero bias operation of these diode rectifiers is very desirable for detection of low power RF signals. In the present work, an Au/Al2O3/Mo MIM diode integrated with coplanar waveguide (CPW) is fabricated and its rectification

This paper reviews the feasibility of the state-of-the-art electrical techniques adopted from Si technology for characterization of SiC MOS devices. The inability of these conventional characterization techniques to correctly evaluate the trap capture cross section and field-effect mobility in SiC MOS devices are investigated and explained. As near-interface traps (NITs) are an important cause of field-effect

In this paper we identify the dominant contribution to the OFF-state distortion of an MOS transistor coming from the overlap regions applying of device-level harmonic balance simulations in a calibrated TCAD setup. Both overlap (Cgs,Cgd) and direct capacitance (Cds) are described with novel physics-based models that are, in conjunction with an analytical Volterra series analysis, capable of describing

Junctionless transistors (JLTs) are one of attractive candidates for further scaling down thanks to their promising advantages based on a structural simplicity without PN junctions, and their physical operation is quite different from traditional inversion-mode (IM) transistors. In this paper, we investigated the subthreshold operation of tri-gate JLTs with various effective width (Weff) and compared

A parallel-MOS-triggered silicon-controlled rectifier (PMTSCR) is firstly proposed and verified in a 0.25-μm Bipolar-CMOS-DMOS process, aiming to prevent the latch-up effect of SCR in the electrostatic discharge (ESD) protection. Comparing to the conventional SCR, the trigger voltage (Vt1) of the PMTSCR decreases because of the effect of PMOS embedded in the N-well, and the holding voltage (Vh) increases

In this study, the phenol red (PR) dye film has been deposited on n-type silicon wafer and SEM, XRD measurements of the film have taken. Then, the PR/n-Si photodiode has been fabricated and (dark) electrical and photoresponse characterization has been analysed. The current-Voltage (I-V) measurements have been carried out at varied light power ranging from 100 mW/cm2 to 400 mW/cm2. Rectification ratios

TiO2/g-CN based photocatalyst has been widely studied for its easy synthesis and outstanding charge separation efficiency. However, the difficulty in obtaining a high photocurrent value limits its application in photoelectrocatalysis water splitting. In this article, bimetallic NiMoO4 nanosheets co-catalyst was decorated onto TiO2/g-CN heterojunction to form TiO2/g-CN/NiMoO4 3D nanostructure. We obtained

This paper reports an investigation of the effects of varying different device parameters on the random-dopant-fluctuation (RDF) induced threshold voltage variability (σVT) in junctionless (JL) InGaAs FinFETs. Such investigation is made by means of a 3D numerical device simulator. Both gate length and fin height scaling are found to increase σVT in InGaAs JL FinFETs, similar to that in Si devices,

This letter reports a systematic study about the effect of surface stoichiometry induced by inductively coupled plasma (ICP) etching on the ohmic contact to N-face n-GaN. It is found that N-face n-GaN surface has a very high activity towards oxygen adsorption. And it is indispensable to remove GaOx layer on the N-face n-GaN surface prior to the metal deposition to realize ohmic contact. Moreover, the

We present a detailed study of the effect of gate-oxide-related defects (traps) on the small-signal radio frequency (RF) response of III-V nanowire MOSFETs and find that the effects are clearly identifiable in the measured admittance parameters and in important design parameters such as h21 (forward current gain) and MSG (maximum stable gain). We include the identified effects in a small-signal model

In this work, the electrical stability of zinc nitride (Zn3N2) Thin-film Transistors (TFTs) under negative bias stress (NBS) and positive bias stress (PBS) is presented. The Zn3N2 TFTs were fabricated on plastic substrates. Spin-on glass was used as gate dielectric. The threshold voltage shift (ΔVT) and its recovery are analyzed during a long stress time and after a period of rest. The hysteresis of

The basic relationships for a Hall plate with N non-symmetric contacts placed in an arbitrary magnetic field are a set of N-1 relationships that are necessary and sufficient for the existence of a complex electrostatic potential function. By the application of the boundary conditions, they turn into a linear system of N-1 compatibility conditions involving the terminal voltages and currents. The construction

Monolithic optoelectronic integrated circuits, OEICs are seen as key enabling technologies to minimal power loss criteria. Monolithic OEICs combine, on the same die, cutting-edge optical devices and high speed III-V electronics able to generate terahertz signal targeting beyond-5G networks. Computationally efficient compact models compatible with existing software tool and design flow are essential

In this paper, the local oxidation of SiC (LOCOSiC) isolation using pre-amorphization implantation technology is integrated into the 4H-SiC Schottky barrier didoes (SBD) fabrication to evaluate its isolation ability due to the high sensitivity of SBD to those defects induced by process. Using Ar plasma treatment, the barrier height can be centralized at ~1.1 eV with reduced variation, which lies in

Development of accurate models for resistive switching devices (memristors) is a research topic of utmost interest. Behavioral models usually employ window functions (WFs) to capture the dependency of the resistance switching-rate on the bias conditions. Several WFs have been published so far, all of them being functions of just the state variable(s), ignoring the effect of the applied signal magnitude

In this paper, Silvaco Atlas TCAD device-circuit mixed simulation and MATLAB programming are used to compute the reverse recovery processes of silicon PIN diodes. The latter is based on solving the ambipolar diffusion equation (ADE) with the moving boundaries. The results of the ADE-based Fourier expansion (FE) and finite difference (FD) method are first compared with that from the Atlas simulation

The thermometric behavior of lateral 50-nm thin Silicon-On-Insulator (SOI) diodes are studied down to 80 K, close to liquid-nitrogen temperature. A comparison between PtSi/n-Si Schottky and implanted p-i-n diodes is presented. In this study, the intrinsic region is a moderately-doped n-type region. Key figures are extracted at room and cryogenic temperatures for each diode. A Temperature Coefficient

A spatial systematic mismatch, occurring in the integrated circuit manufacturing process, leads to differences in parameters for two or more identical devices. It is widely accepted that placing devices into symmetrical patterns reduces the spatial systematic mismatch between their parameters. In this paper, a novel method based on linear and nonlinear parameter gradient modeling for the assessment

This paper investigates the local variability in nanoscale triple-gate junctionless FinFETs utilizing an analytical symmetric and continuous compact model combined with Monte Carlo simulations. Initially, the device parameters are extracted from the experimental transfer characteristics, such as threshold voltage, ideality factor, low-field mobility, source-drain series resistance, channel length modulation

In this work, we investigated an anomalous hump in the bottom-gate amorphous-InGaZnO thin-film transistors. The hump in the subthreshold region appeared at elevated temperature and disappeared after N2 atmosphere annealing. The anomalous hump phenomenon is attributed to the existence of both main current path composed by electron and parasitic current path induced by positive charges formed by adsorbed

A comparative investigation on device characteristics of AlGaN/GaN high electron mobility transistors (HEMTs) with SiNx, SiOx, and SiON passivation by using plasma enhanced chemical vapor deposition (PECVD) technique is conducted. The electrical performance of passivated GaN HEMTs are evaluated through DC current-voltage, pulsed current-voltage, and small-signal measurements. Obvious increases of 10

A comprehensive analysis of the MOSFET subthreshold swing for a 2D subband with exponential band tail of states is first proposed. Then, a compact analytical expression for the subthreshold swing as a function of temperature is derived, well accounting for both its cryogenic temperature saturation and classical higher temperature increase. Moreover, a generalized subthreshold swing calculation applicable

The effect of different point defects in CdZnTe (CZT) crystals on carrier transport performance were discussed. The energy level and concentration of the traps were determined by the photo-induced current transient spectroscopy (PICTS). By adding the infrared light illumination into the PICTS experiment, the effect of sub-bandgap light on defects was observed. Meanwhile, several DC photoconductive

Herein, the effect of pulsed Nd:YAG laser irradiation at different fluencies in air at room temperature on the performance of n-PSi/ZnO-based UV MSM photodetector was demonstrated. Thermal and photon energies were coupled to synthesize n-PSi/ZnO NCs heterojunctions. The porous silicon (PSi) films with nano-sized pore arrays were first prepared via photoelectrochemical etching (PECE) of n-type silicon

Tunnel Field Effect Transistors (TFETs) are known to be compromised by higher order processes that downgrade their performance compared to ballistic projections. Using a quasi-analytical model that extends the chemistry based Simmons equation to include finite temperature effects, potential variations and scattering, we exhibit that non-idealities like trap-assisted tunneling and Auger generation can

Conductivity and work function of the conductive polymer, poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT:PSS), has been investigated for a top electrode of the solution-processed organic solar cells (OPV). It has been found that both conductivity and work function could be changed by adjusting the mixing ratio of different commercial grade PEDOT:PSS such as PH 1000 and AI 4083. A 2:1 vol

Investigation of the third-order intercept point, IP3 and nonlinear distortion level, NDL for pre-and post-multilayer processed GaAs pHEMTs has been accomplished by employing two-tone intermodulation distortion measurements. The third-order intercept point is a biasing, input power, frequency-dependent term, particularly related to the fundamental and third-order intermodulation distortion component

The impact of channel flattening process, dozen digital etching (DDE), which is several dozen cyclic treatments of plasma oxidation and oxide wet etching, on device performance and reliability of Ge(1 0 0) nMOSFETs has been systematically investigated. It was found that DDE improves not only electron mobility but also Positive Bias Temperature Instability (PBTI). The PBTI degradation was found related

We present experimental results for junctionless nanowire transistors (JNTs) with different gate alignments to the nanowire. Devices with nanowire source/drain extensions (NSDE) show high series source/drain resistance due to the low doped nanowire extensions, which causes lower drive current and larger device performance variations comparing with devices in which the gate electrode overlaps with the

Junctionless Transistors (JL) and One-Transistor (1T) DRAMs are concepts that come out in order to improve the scalability of logic and volatile memories, respectively. In some recent papers, Floating Body (FB) DRAMs (a class of 1T-DRAM) and JL transistors have been joined in order to propose a solution to overcome the scaling limit of the conventional 1T-1C DRAM cells. In this paper they are discussed

In this work, we report a high-performance lateral GaN Schottky barrier diode (SBD) with a low turn-on voltage (VON) of 0.39 V and low reverse current. Meanwhile we have proposed a model to comprehend the leakage current mechanism in this GaN SBDs. The reverse current transport mechanism was analyzed by temperature-dependent current–voltage (T-I-V) measurements. The results indicate that reverse current

A simple model is proposed for the Back Enhanced SOI MOSFET in triode region. This model is based on a conventional MOSFET model in series with resistors and antiparallel Schottky diodes. A robust parameter extraction method, based on lateral optimization, is also presented. The dependence of the extracted parameters with the back-gate bias is studied.

This paper presents a physics-based scalable formulation for interface trap generation in the vicinity of the emitter-base spacer oxide interface in advanced SiGe HBTs. Aging tests were performed for various emitter dimensions to investigate the scalability of the dynamics of hot-carrier degradation. An improved formulation of the bond dissociation rate is also proposed incorporating a scaling rule

Low frequency noise study is performed at deep cryogenic temperature of 10 K in p-channel gate-all-around (GAA) nanowire (NW) FETs. As expected, the carrier number fluctuations mechanism explains the flicker noise origin for conventional fixed applied drain bias. At very low applied drain biases step-like effects impact the drain current transfer characteristics. Noise measurements performed at a fixed

In this paper we present a simulation study of a novel Double-Gate (DG) Ferroelectric FET (Fe-FET) architecture, exhibiting a subthreshold swing well below 60 mV/dec with a hysteresis-free behavior. The new device topology is based on the interposition of a floating gate between the ferroelectric layer and the gate oxide. The floating gate can be extended above the source and drain regions, so that

A recently developed nonlocal history dependent model for electron and hole impact ionization is used to compute the gain and the excess noise factor in avalanche photodiodes featuring heterojunctions of III-V compound semiconductors while accounting for both carriers. The model has been calibrated with measurements by our group, as well as on noise versus gain data from the literature. We explore

We report a novel switched-mode light-emitting device (LED) in an undoped ultra-thin-body (UTB) based on the electrostatically-induced electron-hole bilayer (EHB) concept. The proposed device works on the principle of formation of EHB channels by applying suitable gate biases during the charging-cycle, and their recombination during a discharging-cycle. Using TCAD simulations, we show that continuous

For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty, as well as the capability to route two additional row-wise signals on individual back planes. Experimental data are extracted from a 14 nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078 µm2 SRAM cell in order to

We investigate the robustness of a purely electrical field-free switching of a perpendicularly magnetized free layer based on SOT. The effective magnetic field which leads to deterministic switching of a rectangular as well as of a square free layer is created dynamically by a two-current pulse scheme. It is demonstrated that the switching is very robust, being insensitive to fluctuations of the write

In this paper, small- and large-signal performances of passive devices integrated on high-resistivity, trap-rich and gold-doped silicon wafers are presented and compared through measurements and simulations. The gold-doped silicon substrate was produced starting from standard silicon having a nominal resistivity of 56 Ω·cm. We show that the gold-doped substrate presents high effective resistivity and

The unique electrostatic properties of semiconductor nanowires enable the realization of novel transistor types by the possibility to use surround gate architectures resembling ideal gate electrostatic control. Nevertheless one fundamental issue of semiconducting nanowire channels is the reliable control of doping to adjust the charge carrier concentration. Indeed, as dimensions scale down the surrounding

In this paper, using numerical simulations, analytical modeling and experimental data, we validate the applicability of the transconductance-to-current ratio (gm/ID) derivative (d(gm/ID)/dVG) method for extracting the threshold voltage (VTH) in junctionless (JL) MOSFETs and show its advantages over the commonly-used transconductance derivative (or double derivative of drain current) method (dgm/dVG≡d2ID/dVG2)

We report on vertically stacked lateral nanowires (NW)/nanosheets (NS) gate-all-around (GAA) FET devices as promising candidates to obtain a better power-performance metric for logic applications for advanced sub-5 nm technology nodes, in comparison to finFETs. In addition, vertical NW/NS GAA FETs appear particularly attractive for enabling highly dense memory cells such as SRAMs (with improved read

This paper reports on resistive switching behavior observed in resistive random access memory (RRAM) devices fabricated with aluminum oxide (AlOx) and graphene oxide (GO) dielectric films, which were solution-processed under low annealing temperatures of 250 °C and 50 °C for AlOx and GO dielectric films, respectively. As representative of metal oxide and two-dimensional material, a detailed study and

Preliminary results are reported on an in-situ heater for thermal assist recovery of MOS transistor and is demonstrated in 28 nm Fully Depleted Silicon-On-Insulator (FD-SOI) Ultra-Thin Body and Buried oxide (UTBB) high-k metal gate CMOS technology. This approach consists in functionalizing the source of a MOS device. We demonstrate that it is possible to heat the device with the current flowing between

New computation schemes inspired by biological processes are arising as an alternative to standard von-Neumann architectures, to provide hardware accelerators for information processing based on a neural networks approach. Systems of frequency-locked, coupled oscillators are investigated using the phase difference of the signal as the state variable rather than the voltage or current amplitude. As

Neuromorphic computing is an emerging field of investigation for new algorithm solutions and daily life applications. We propose a novel approach to achieve an operator which uses a parasitic bipolar metal oxide semiconductor filed effect transistor combined with a capacitor and a n-type metal oxide semiconductor filed effect transistor. The resulting BIMOS-based leaky-integrate-and-fire spiking neuron

A new methodology for MOSFET characterization making use of the on-resistance characteristics Ron(Vg,Vd) = Vd/Id(Vg,Vd) and associated derivatives dRon/dVg and dRon/dVd is proposed. This approach enables to eliminate the influence of source-drain series resistance Rsd not only in linear region but also in non-linear region of MOSFET operation. Therefore, it allows for intrinsic MOSFET parameter extraction