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  • Robust power grid network design considering EM aging effects for multi-segment wires
    Integration (IF 1.214) Pub Date : 2020-10-19
    Han Zhou; Liang Chen; Sheldon X.-D Tan

    This paper presents a number of power grid network design and optimization techniques that consider the electromigration (EM) effects for multi-segment interconnect wires. First, we consider a new EM immortality constraint due to EM void saturation volume for multi-segment interconnects. It helps reduce conservativeness in the EM-aware on-chip power grid design. Along with the EM nucleation phase immortality

  • Accelerating Deep Convolutional Neural Network base on stochastic computing
    Integration (IF 1.214) Pub Date : 2020-09-29
    Mohamad Hasani Sadi; Ali Mahani

    Deep Convolutional Neural Networks (DCNNs) are highly computational, and low budget platforms face many restrictions due to their implementation. Recently, Stochastic Computing (SC) demonstrated satisfying solution with simple and low power arithmetic units. In this paper, we present a highly efficient SC-based inference framework of DCNNs. We first propose a new Approximate Parallel Counter (APC)

  • Comments on “Improved designs of digit-by-digit decimal multiplier”
    Integration (IF 1.214) Pub Date : 2020-10-15
    Mojtaba Valinataj; Zahra Yazdanian Amiri

    Decimal multiplication is one of the complex operations in the applications that still radix-10 representations are preferred. To improve the performance, Ahmed et al. proposed some fast and area efficient binary-to-decimal converters to be used for both partial product generation and partial product reduction stages of digit-by-digit decimal multiplication. These converters that transform each binary

  • Invasive weed optimization based scheduling for digital microfluidic biochip operations
    Integration (IF 1.214) Pub Date : 2020-10-14
    Kolluri Rajesh; Sumanta Pyne

    Digital Microfluidic Biochips (DMFBs) based on electro-wetting-on-dielectric (EWOD) technology are a class of lab-on-a-chip (LOC) devices. DMFBs can efficiently carry out biochemical analysis and have many advantages over the traditional laboratory system. DMFBs offer miniaturization, automation, and programmability. Resource-constrained scheduling is the first and vital step of fluidic-level synthesis

  • A PVT aware differential delay circuit and its performance variation due to power supply noise
    Integration (IF 1.214) Pub Date : 2020-10-14
    Anirban Tarafdar; Abir J. Mondal; Uttam K. Bera; B.K. Bhattacharyya

    Delay circuits are one of the key components in time domain blocks such as pulse width modulator. This work describes the working of a differential delay circuit under process, voltage and temperature. The proposed design is also coupled to a typical power delivery network (PDN) and a central processing unit (CPU) core ramping current from 0 A to 10–40 A in 10 ns Simulated in a 90-nm CMOS technology

  • A novel approach to fractional-N PLLs generating ultra-fast low-noise chirps for FMCW radar
    Integration (IF 1.214) Pub Date : 2020-10-11
    Frank Herzel; Arzu Ergintav; Gunter Fischer

    This paper presents a novel approach to generate ultra-fast chirps for frequency-modulated continuous wave (FMCW) radar systems. A symmetric triangular frequency chirp is analyzed. A very large loop bandwidth could minimize the PLL settling time, but would result in a high phase noise and in large spurs. This work minimizes the settling times without using an excessive loop bandwidth. Rather, the initial

  • Electronically tunable third-order dual-mode quadrature sinusoidal oscillators employing VDCCs and all grounded components
    Integration (IF 1.214) Pub Date : 2020-09-15
    Suvajit Roy; Radha Raman Pal

    Two new configurations of third-order dual-mode (i.e. both voltage and current mode) quadrature sinusoidal oscillator using a newly reported active block, called the voltage differencing current conveyor (VDCC) have been presented in this manuscript. Both the proposed oscillators employ two VDCCs, three capacitors, and three resistors. The circuits are suitable for integrated circuit (IC) realization

  • The Involution Tool for Accurate Digital Timing and Power Analysis
    Integration (IF 1.214) Pub Date : 2020-09-22
    Daniel Öhlinger; Jürgen Maier; Matthias Függer; Ulrich Schmid

    We introduce the prototype of a digital timing simulation and power analysis tool for integrated circuits that supports the involution delay model (Függer et al. 2019). Unlike the pure and inertial delay models typically used in digital timing analysis tools, the involution model faithfully captures short pulse propagation and related effects. Our Involution Tool facilitates experimental accuracy evaluation

  • Custom NoC topology generation using Discrete Antlion Trapping Mechanism
    Integration (IF 1.214) Pub Date : 2020-09-10
    Poornima Narayanasamy; Seetharaman Gopalakrishnan; Santhi Muthurathinam

    This paper outlines an innovative and creative algorithm known as Discrete Antlion Trapping Mechanism (DATM). It imitates the hunting mechanism of antlions in nature. The proposed DATM is incorporated in Network on Chip (NoC) which is a replacement to standard transmission technique along with the Reliable Reconfigurable Real-Time Operating System (R3TOS) for intertask communications. Though there

  • 2.3–21 GHz broadband and high linearity distributed low noise amplifier
    Integration (IF 1.214) Pub Date : 2020-09-14
    El Bakkali Moustapha; Elftouh Hanae; Amar Touhami Naima; Elhamadi Taj-eddin

    This paper focuses on the design of a 2.3–21 GHz Distributed Low Noise Amplifier (LNA) with low noise figure (NF), high gain (S21), and high linearity (IIP3) for broadband applications. This distributed amplifier (DA) includes S/C/X/Ku/K-band, which makes it very suitable for heterodyne receivers. The proposed DA uses a 0.18 μm GaAs pHEMT process (OMMIC ED02AH) in cascade architecture with lines adaptation

  • A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition
    Integration (IF 1.214) Pub Date : 2020-09-16
    Bibin Sam Paul S; Antony Xavier Glittas; Lakshminarayanan Gopalakrishnan

    In this paper, a low-complex chip to extract the Mel Frequency Cepstral Coefficient for a speech recognition system is presented. The architecture can operate in a continuous-flow manner to process streaming or the stored speech signal at high speed. The frame-overlap Hamming window, DFT and Mel-filter bank computations are deeply integrated to share memory buffers and avoid bit-reversal circuit to

  • Low delay non-binary error correction codes based on Orthogonal Latin Squares
    Integration (IF 1.214) Pub Date : 2020-09-09
    Francisco Garcia-Herrero; Alfonso Sánchez-Macián; Juan Antonio Maestro

    Due to the scaling of technology and the environment effects, such as radiation, memory systems that are on board of spacecraft such as satellites, are more sensitive to errors. This kind of error is difficult to predict and its correction in real-time is crucial for the correct behavior of the whole system. In this paper, a low delay fully parallel non-binary decoder based on orthogonal Latin squares

  • An improved heuristic technique for nearest neighbor realization of quantum circuits in 2D architecture
    Integration (IF 1.214) Pub Date : 2020-09-11
    Anirban Bhattacharjee, Chandan Bandyopadhyay, Philipp Niemann, Bappaditya Mondal, Rolf Drechsler, Hafizur Rahaman

    Last couple of years has witnessed tremendous advancements in the field of quantum computing and even it has started providing technological footprints in the design industry. Though advancements in the physical implementation of quantum circuits has taken a giant leap but it has faced with several design challenges and one such design constraint is Nearest Neighbor (NN) criteria which demands the

  • MOS based pseudo-resistors exhibiting Tera Ohms of Incremental Resistance for biomedical applications: Analysis and proof of concept
    Integration (IF 1.214) Pub Date : 2020-08-30
    Kulbhushan Sharma, Anisha Pathania, Rahul Pandey, Jaya Madan, Rajnish Sharma

    Performance of biomedical analog circuits vitiates due to non-linear V-R characteristics of Pseudo-resistor (PR) structure, their excess dependency over Process Voltage Temperature (PVT) and common mode variations. In this paper, Incremental Resistance (IR) expressions, V-R curves and statistical results for wider PVT variations for diverse categories of non-tunable and tunable PR structures have been

  • Power-aware hold optimization for ASIC physical synthesis
    Integration (IF 1.214) Pub Date : 2020-08-28
    Mohamed Chentouf, Foffie Stevmelin, Zine El Abidine Alaoui Ismaili

    Hold timing closure is an important milestone at the physical design phase of every Application Specific Integrated Circuit (ASIC). Many approaches have been proposed by different researchers and commercial Electronic Design Automation (EDA) providers to fix hold timing violations, but there has been no effort to study the impact of each technique on power consumption. Nowadays, the rise of low power

  • READ: A fixed restoring array based accuracy-configurable approximate divider for energy efficiency
    Integration (IF 1.214) Pub Date : 2020-08-22
    Neelam Arya, Teena Soni, Manisha Pattanaik, G.K. Sharma

    Energy efficiency has emerged as one of the most essential design parameters in contemporary computing system design. Approximate computing is a new computing paradigm to achieve energy efficiency by trading-off energy/area/latency improvements with accuracy for error-resilient applications. This paper proposes Reconfigurable Energy-efficient Approximate Divider (READ) that achieves several energy–quality

  • On reverse converters for arbitrary multi-moduli RNS
    Integration (IF 1.214) Pub Date : 2020-08-20
    Piotr Patronik

    In this paper, we propose a new design of reverse converters for residue number systems with arbitrary moduli sets consisting of any number of odd moduli and one even modulus of the type 2k. The new converters are arithmetic-based designs, that may be implemented using only arithmetic components without any read-only memories nor lookup tables. We tackle the problem of large modular reduction imposed

  • Refinement Rules for the Automatic TLM-to-RTL Conversion of Temporal Assertions
    Integration (IF 1.214) Pub Date : 2020-08-17
    Laurence PIERRE

    Today’s systems on chip (SoCs) require a complex design and verification process. In early design stages, high-level debugging of the SoC functionality is feasible on TLM (Transaction-Level Modeling) descriptions. To ease debugging of such SoC’s models, Assertion-Based Verification (ABV) enables the runtime verification of temporal properties. In the last design stages, RTL (Register Transfer Level)

  • High-throughput architecture for post-quantum DME cryptosystem
    Integration (IF 1.214) Pub Date : 2020-08-02
    José L. Imaña, Ignacio Luengo

    Quantum computers have the potential to solve difficult mathematical problems efficiently, therefore meaning an important threat to Public-Key Cryptography (PKC) if large-scale quantum computers are ever built. The goal of Post-Quantum Cryptography (PQC) is to develop cryptosystems that are secure against both classical and quantum computers. DME is a new proposal of quantum-resistant PKC algorithm

  • Time-domain writing architecture for multilevel RRAM cells resilient to temperature and process variations
    Integration (IF 1.214) Pub Date : 2020-08-01
    Amadeo de Gracia Herranz, Marisa Lopez-Vallejo

    The high potential of memristors as multilevel resistance devices is undermined by their highly non-linear behaviour and a strong dependency on different sources of variability (process, voltage, temperature…). Temperature fluctuations are specially harmful because small thermal variations may significantly modify the operation point of the device. For these reasons the circuitry required to accurately

  • Harvester-aware transient computing: Utilizing the mechanical inertia of kinetic energy harvesters for a proactive frequency-based power loss detection
    Integration (IF 1.214) Pub Date : 2020-07-27
    Carl C. Rheinländer, Norbert Wehn

    Power-neutral system design avoids energy buffers by directly powering the load by the energy harvester. In case of a power loss, checkpointing methods ensure forward progress by preserving the volatile system state using non-volatile memories. The timely detection of upcoming power losses is essential for a reliable checkpointing process. Moreover, various applications require early detections to

  • Area and power efficient hard multiple generator for radix-8 modulo 2n − 1 multiplier
    Integration (IF 1.214) Pub Date : 2020-07-25
    Naveen Kr Kabra, Zuber M. Patel

    In this paper, we introduce an area and power efficient algorithm to design a hard multiple generator for radix-8 modulo 2n − 1 multiplier, which is based on parallel prefix computation of carry propagate. Only odd carry is used to generate hard multiple bits. The proposed architecture uses ⌈log2n⌉-2 prefix level with n2 prefix operators. The Post-synthesis result of proposed architecture shows 27

  • On the quadrature accuracy of in-phase coupled quadrature LC oscillator
    Integration (IF 1.214) Pub Date : 2020-07-24
    Mahsa Hadjmohammadi, Hossein Miar Naimi, Hojat Ghonoodi

    In this article, closed-form equations are proposed for phase and amplitude errors of an in-phase coupled quadrature LC oscillator. First of all, the injected current from coupling network to switching one is analytically calculated in a novel approach. Then, fundamental equations are obtained to derive phase and amplitude errors which are results of mismatches of the tank's inductors, capacitors and

  • Investigating the influence of adiabatic load on the 4-phase adiabatic system design
    Integration (IF 1.214) Pub Date : 2020-07-06
    Himadri Singh Raghav, V.A. Bartlett

    This paper investigates the power-clock generation using Step Charging Circuits (SCC). In particular, the impact of the adiabatic load on the energy dissipation of the 4-phase Power-Clock Generator (PCG) and on the overall adiabatic system is investigated. The adiabatic implementations are compared with their conventional CMOS counterparts based on energy dissipation, the number of transistors and

  • Low-power content addressable memory design using two-layer P-N match-line control and sensing
    Integration (IF 1.214) Pub Date : 2020-07-04
    Sheikh Wasmir Hussain, Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat

    Content addressable memory (CAM) is a specialized search engine mostly used for speeding memory lookup in network devices. Despite fast searching, activation of all comparison circuits in every clock cycle costs huge power. Power dissipation is more severe in high capacitive NOR match-line (ML) because of higher precharge activity and multiple transitions in ML. This paper proposes a two-layer ML scheme

  • An efficient multiple shortest augmenting paths algorithm for constructing high performance VLSI subarray
    Integration (IF 1.214) Pub Date : 2020-07-01
    Junyan Qian, Bisheng Huang, Hao Ding, Zhide Zhou, Lingzhong Zhao, Zhongyi Zhai

    Reconfiguring a high-performance subarray of a VLSI array with faults is to construct a maximum target array with the minimum number of long interconnects, which can reduce communication costs, capacitance and dynamic energy dissipation. An existing work proved that the high performance VLSI subarray can be constructed in polynomial time using network flow algorithm. However, because of the disadvantage

  • A high-efficiency charge pump with charge recycling scheme and finger boost capacitor
    Integration (IF 1.214) Pub Date : 2020-07-01
    Hui Peng, Herbert De Pauw, Pieter Bauwens, Jan Doutreloigne

    A 16-phase 8-branch charge pump with finger boost capacitor is proposed to increase the power efficiency and it is implemented in a 0.35 μm high-voltage CMOS IC technology. Compared with the standard capacitor, the finger capacitor can significantly reduce the parasitic capacitance. By combining the charge recycling method and the finger capacitor, the proposed four-stage charge pump can achieve an

  • Design space exploration of low-power flip-flops in FinFET technology
    Integration (IF 1.214) Pub Date : 2020-06-26
    Ehsan Mahmoodi, Morteza Gholipour

    As technology evolves, new devices emerge to overcome the known short-channel effects of conventional MOSFETs. FinFETs, as recent devices, are widely used in modern processor designs. Elaborate design of circuit elements can effectively increase the overall chip performance. In this paper we studied the design of high performance flip-flop (FF) using FinFET devices. We have investigated several transistor

  • Avoidance vs. repair: New approaches to increasing electromigration robustness in VLSI routing
    Integration (IF 1.214) Pub Date : 2020-06-10
    Steve Bigalke, Jens Lienig

    Studies on further IC development mutually predict that the reliability of future integrated circuits (ICs) will be severely endangered by the occurrence of electromigration (EM). The reason for the increasing number of EM damages are the ongoing structural reductions in the IC. Digital circuits are particularly at risk because they have been neglected in the consideration of EM, resulting in a lack

  • Graph-based STA for asynchronous controllers
    Integration (IF 1.214) Pub Date : 2020-06-09
    Stavros Simoglou, Nikolaos Xiromeritis, Christos Sotiriou, Nikolaos Sketopoulos

    We present a Graph-based Asynchronous Static Timing Analysis (ASTA) methodology for Asynchronous Control Circuits, which pessimistically computes Critical Cycle(s), instead of Critical Paths, without cycle cutting. Its additional requirement over STA is a graph-based Event Model, Marked Graph or Petri Net. We contrast STA, ASTA results for 23 asynchronous circuit benchmarks, and demonstrate significant

  • A passive and low-complexity Compressed Sensing architecture based on a charge-redistribution SAR ADC
    Integration (IF 1.214) Pub Date : 2020-05-31
    Carmine Paolino, Luciano Prono, Fabio Pareschi, Mauro Mangia, Riccardo Rovatti, Gianluca Setti

    An innovative analog-to-digital converter (ADC) architecture is proposed, with the aim of acquiring an input signal according to the Compressed Sensing (CS) paradigm and without the need for dedicated active analog blocks. Its core is the capacitive array employed in traditional successive-approximation-register (SAR) ADCs. Introducing only a few additional switches, the array can compute the linear

  • An ultra-wideband 6–14 GHz frequency modulated continuous wave primary radar with 3 cm range resolution
    Integration (IF 1.214) Pub Date : 2020-05-31
    Tom Drechsel, Niko Joram, Frank Ellinger

    This paper describes the design and verification of an ultra-wideband 6–14 GHz frequency modulated continuous wave (FMCW) primary radar system with very high range resolution. The design and measurement results of the utilized signal generator and receiver are presented. The signal generator features a 86% relative continuous tuning range and average phase noise of −106 dBc/Hz at 1 MHz offset to the

  • A new realization scheme for dynamic PFSCL style
    Integration (IF 1.214) Pub Date : 2020-05-29
    Ranjana Sivaram, Kirti Gupta, Neeta Pandey

    In this paper, a new scheme of logic function realization in dynamic positive feedback source-coupled logic (D-PFSCL) style is proposed. The existing scheme implements only NOR/OR based realization of a logic function. Thus, a complex function in D-PFSCL has high gate count which degrades the overall circuit performance measured in terms of power and delay. This paper therefore aims to resolve the

  • Sensor based adaptive voltage scaling on FPGAs: Calibration and parametrization
    Integration (IF 1.214) Pub Date : 2020-05-29
    Christoph Niemann, Munawar Ali, Obaid Ullah Shah, Jakob Heller, Dirk Timmermann

    The impacts of aging and process variations on the performance of VLSI systems is increasing with each process generation. The conventional way to counteract them are extensive guard bands, which are calculated at system design time. Hence, they are necessarily worst case guard bands, i.e., most often too pessimistic. Current research tries to mitigate this by means of in-situ performance measurement

  • System-level evaluation of dynamic effects in a GaN-based class-E power amplifier
    Integration (IF 1.214) Pub Date : 2020-05-29
    Andrea Minetto, Bernd Deutschmann, Oliver Häberlen, Gilberto Curatola

    Gallium Nitride shows huge potential in power electronics applications thanks to the superior intrinsic material properties which result in improved performance both at device level and system level. Great effort has been taken in recent years to industrialize GaN technology and to solve some of the major drawbacks like reliability issues and dynamic effects. The goal of this work is to propose a novel

  • New lightweight Anti-SAT block design and obfuscation technique to thwart removal attack
    Integration (IF 1.214) Pub Date : 2020-05-29
    Vijaypal Singh Rathor, Bharat Garg, G.K. Sharma

    Logic locking has emerged as a prominent technique to protect an integrated circuit from piracy, overbuilding, and hardware Trojans. Most of the well-known logic locking techniques are vulnerable to satisfiability (SAT) based attack. Though several SAT-resistant logic locking techniques such as Anti-SAT block (ASB) are reported that increase the time to decipher the secret key, the existing techniques

  • Verification of a high precision CMOS sensor for angle-of-arrival (AOA) measurement of LED light in ultra-miniaturized applications
    Integration (IF 1.214) Pub Date : 2020-05-26
    André Feiler, Dominik Veit, Lukas Straczek, Jürgen Oehm

    In this study a specially revised version of the concept for measuring the angle-of-arrival (AOA) of incidence light was used, which is particularly well suited for the construction of trigonometric sensor concepts with external dimensions of only a few millimeters. The aim of the study was to break down the interrelationships for the overall systemically achievable accuracies. The study therefore

  • The synthesis method of logic circuits based on the iMemComp gates
    Integration (IF 1.214) Pub Date : 2020-05-22
    Xiaole Cui, Qiujun Lin, Xiaoxin Cui, Feng Wei, Xiaoyan Liu, Jinfeng Kang

    The iMemComp is a family of logic gates based on RRAM devices. It has potential advantage on the design of high-performance logic circuits, since the NAND, AND, NOT and transmission iMemComp gates only consume single cycle, respectively. However, the synthesis method of logic circuits based on the iMemComp gates has not been systematically studied before. This work proposes the synthesis method of

  • A fast approach for bitcoin blockchain cryptocurrency mining system
    Integration (IF 1.214) Pub Date : 2020-05-19
    Le Vu Trung Duong, Nguyen Thi Thanh Thuy, Lam Duc Khai

    The growth of the blockchain-based cryptocurrencies has attracted a lot of attention from a variety of fields, especially in academic research. One of them is Bitcoin, the most popular and highest valued cryptocurrency on the market. The SHA256 is the main processing part in Bitcoin mining, to date the difficulty of which is extremely high and still increases relentlessly. Hence, it is essential to

  • Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training
    Integration (IF 1.214) Pub Date : 2020-05-14
    TaiYu Cheng, Yukata Masuda, Jun Chen, Jaehoon Yu, Masanori Hashimoto

    Recently, emerging “edge computing” moves data and services from the cloud to nearby edge servers to achieve short latency and wide bandwidth, and solve privacy concerns. However, edge servers, often embedded with GPU processors, highly demand a solution for power-efficient neural network (NN) training due to the limitation of power and size. Besides, according to the nature of the broad dynamic range

  • A cellular automata guided two level obfuscation of Finite-State-Machine for IP protection
    Integration (IF 1.214) Pub Date : 2020-05-14
    Rajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay

    A popular countermeasure against IP piracy is to obfuscate the Finite State Machine (FSM) which is assumed to be the heart of a digital system. Most of the existing FSM obfuscation strategies rely on additionally introduced set of obfuscation mode state-transitions to protect the original state-transitions of the FSM. Although these methods assume that it is difficult to extract the FSM behavior from

  • SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage
    Integration (IF 1.214) Pub Date : 2020-05-11
    Taehwan Kim, Kwangok Jeong, Jungyun Choi, Taewhan Kim, Kyumyung Choi

    Low power design by near-threshold voltage (NTV) operation is very attractive since it affords to considerably mitigate the sharp increase of power dissipation. However, one key barrier for the use of NTV operation is the significant increase of the SRAM failure. In this work, we propose an on-chip SRAM monitoring methodology that is able to accurately predict the minimum voltage, Vddmin, on each die

  • PCoSA: A product error correction code for use in memory devices targeting space applications
    Integration (IF 1.214) Pub Date : 2020-05-10
    David Freitas, David Mota, Roger Goerl, César Marcon, Fabian Vargas, Jarbas Silveira, João Mota

    The radiation sensitivity of integrated memory cells increases dramatically as the supply voltage decreases. Although there are some Error Correcting Code (ECC) studies to prevent faults on memories used in space applications, there is no consensus on choosing the best ECC product-type with two-dimensional Hamming to mitigate data faults in memory. This work introduces the Product Code for Space Applications

  • An efficient background calibration technique for analog-to-digital converters based on neural network
    Integration (IF 1.214) Pub Date : 2020-05-07
    Honghui Deng, Yijun Hu, Liang Wang

    This paper introduces a background digital calibration algorithm based on neural network, which can adaptively calibrate multiple non-ideal factors in a single-channel ADC, such as gain error, mismatch, offset and harmonic distortion. It enables an efficient background calibration through a simple feed forward neural network and LM gradient descent algorithm. The simulation results show that in the

  • Yield constrained automated design algorithm for power optimized pipeline ADC
    Integration (IF 1.214) Pub Date : 2020-05-04
    Vala Sadrafshari, Shamin Sadrafshari, Mohammad Sharifkhani

    Pipeline Analog to Digital Converter (ADC) design processes include several redesign steps to achieve the optimum solution. Hence, designers prefer to use automated algorithms for this purpose. In this paper, an automated algorithm for CAD tool is presented considering the trade-off between yield and power consumption for pipeline ADCs. This automated algorithm benefits from multiple degrees of freedom

  • A bulk-driven quasi-floating gate FVF current mirror for low voltage, low power applications
    Integration (IF 1.214) Pub Date : 2020-04-30
    Mounira Bchir, Imen Aloui, Nejib Hassen

    This paper introduces a new low-voltage, low-power FVF current mirror circuit. The bulk-driven (BD) technique is employed to achieve extended input voltage swing and low supply voltage. Besides, the quasi-floating gate (QFG) is used to achieve high frequency performance. The merging of (BD) and (QFG) appear as a good and attractive solution to improve the circuit performance with reduced supply voltage

  • A 0.3nV/√Hz input-referred-noise analog front-end for radiation-induced thermo-acoustic pulses
    Integration (IF 1.214) Pub Date : 2020-04-30
    Elia A. Vallicelli, Davide Turossi, Luca Gelmi, Alessandro Baù, Roberto Bertoni, Walter Fulgione, Alessandro Quintino, Massimo Corcione, Andrea Baschirotto, Marcello De Matteis

    This paper presents the design and the experimental characterization of a complete acoustic analog front-end (A-AFE) read-out channel for detecting thermo-acoustic pulses induced by heavy-charged particles interacting with matter. The most relevant applications are in particle physics experiments (bubble chambers for Dark Matter Weakly Interacting Massive Particles (WIMPs) detection) and biomedical

  • Design of a real-time face detection architecture for heterogeneous systems-on-chips
    Integration (IF 1.214) Pub Date : 2020-04-28
    Fanny Spagnolo, Stefania Perri, Pasquale Corsonello

    Object detection represents one of the most important and challenging task in computer vision applications. Boosting-based approaches deal with computational intensive operations and they involve several sequential tasks that make very difficult developing hardware implementations with high parallelism level. This work presents a new hardware architecture able to perform object detection based on a

  • On the superiority of modularity-based clustering for determining placement-relevant clusters
    Integration (IF 1.214) Pub Date : 2020-04-23
    Mateus Fogaça, Andrew B. Kahng, Eder Monteiro, Ricardo Reis, Lutong Wang, Mingyu Woo

    In advanced technology nodes, IC implementation faces increasing design complexity as well as ever-more demanding design schedule requirements. This raises the need for new decomposition approaches that can help reduce problem complexity, in conjunction with new predictive methodologies that can help avoid bottlenecks and loops in the physical implementation flow. Notably, with modern design methodologies

  • FPGA implementation of high-performance, resource-efficient Radix-16 CORDIC rotator based FFT algorithm
    Integration (IF 1.214) Pub Date : 2020-04-16
    Ankur Changela, Mazad Zaveri, Deepak Verma

    The fast Fourier transform (FFT) is an algorithm widely used to compute the discrete Fourier transform (DFT) in real-time digital signal processing. High-performance with fewer resources is highly desirable for any real-time application. Our proposed work presents the implementation of the radix-2 decimation-in-frequency (R2DIF) FFT algorithm based on the modified feed-forward double-path delay commutator

  • Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC
    Integration (IF 1.214) Pub Date : 2020-04-15
    Sanjay Vidhyadharan, Surya Shankar Dan, S.V. Abhay, Ramakant Yadav, Simhadri Hariprasad

    This paper presents a highly efficient ternary flash ADC, designed using the innovative gate-overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have on-state currents Ion more than double, while the off-state currents Ioff remaining at least an order of magnitude lower than the corresponding values of the standard 45 nm CMOS technology with the same width. Replacing MOSFETs

  • An efficient and reliable MRF-based methodology for designing low-power VLSI circuits
    Integration (IF 1.214) Pub Date : 2020-04-10
    Sayyed Mohammad Razavi, Seyyed Mohammad Razavi

    Noise-interference is one of the major concerns in low-power VLSI circuits. Due to power supply downscaling, these circuits have an extremely limited noise margin that is inadequate for dealing with intrinsic and extrinsic noise. The MRF-based design has been accepted as a highly effective method for designing noise-tolerant low-power circuits. However, the MRF-based circuits suffer from a complex

  • An innovative two-stage data compression scheme using adaptive block merging technique
    Integration (IF 1.214) Pub Date : 2020-03-26
    Harpreet Vohra, Ashima Singh, Sukhpal Singh Gill

    Test data has increased enormously owing to the rising on-chip complexity of integrated circuits. It further increases the test data transportation time and tester memory. The non-correlated test bits increase the issue of the test power. This paper presents a two-stage block merging based test data minimization scheme which reduces the test bits, test time and test power. A test data is partitioned

  • Improving power analysis attack resistance using intrinsic noise in 3D ICs
    Integration (IF 1.214) Pub Date : 2020-03-21
    Zhiming Zhang, Jaya Dofe, Qiaoyan Yu

    Three-dimensional (3D) integration is envisioned as a natural defense to thwart side-channel analysis (SCA) attacks on the hardware implementation of cryptographic algorithms. However, neither physical experiments nor quantitative analysis is available in existing works to study the impact of power distribution network (PDN) on the SCA attacks. Through quantitative analyses and experiments with realistic

  • Methods increasing inherent resistance of ECC designs against horizontal attacks
    Integration (IF 1.214) Pub Date : 2020-03-20
    Ievgen Kabin, Zoya Dyka, Dan Klann, Peter Langendoerfer

    Due to the nature of applications such as critical infrastructure and the Internet of Things etc. side channel analysis attacks are becoming a serious threat. Side channel analysis attacks take advantage from the fact that the behaviour of crypto implementations can be observed and provides hints that simplify revealing keys. A new type of SCA is the so called horizontal differential SCA. In this paper

  • An adaptive simulation framework for AMS-RF test quality
    Integration (IF 1.214) Pub Date : 2020-03-18
    Valentin Gutierrez, Gildas Leger

    Ensuring the quality of a circuit implies ensuring the quality of test. Despite the fact that performance-based testing has been the golden standard for Analog, Mixed-Signal and RF test for decades, high-reliability markets like automotive have found that functional test leaves some potential defects undetected that can produce in-field failure. There is thus a push towards defect-oriented testing

  • In-sensor time-domain classifiers using pseudo sigmoid activation functions
    Integration (IF 1.214) Pub Date : 2020-03-13
    Ethan Chen, Vanessa Chen

    This work presents an ultra-low-power classifier that can be integrated within energy-constrained bio-sensors to enable rapid analysis for continuous health monitoring. The in-sensor classifier saves significant transmission energy by extracting critical information locally to eliminate the need of transmitting raw data to centralized servers for remote signal processing. The convolutional-neural-network

  • Complex exponential functions: A high-precision hardware realization
    Integration (IF 1.214) Pub Date : 2020-03-06
    Adel Hosseiny, Ghassem Jaberipur

    Hardware realization of complex exponential functions (CEF) is not practical for over 16-bit operands. This is due to high cost and delay of the required look-up table (LUT) and arithmetic units. Therefore, we decompose larger (up to 64 bits) operands to three parts (e.g., 11+24+29=64). They are handled by minimax approximation, one-dimensional degree-3 interpolation, and pure LUT approaches, respectively

  • Verification and revision of the power-down mode for hierarchical analog circuits
    Integration (IF 1.214) Pub Date : 2020-03-02
    Maximilian Neuner, Helmut Graeb

    Specialized power-down circuitry can switch off an analog circuit when not required for system operation. When interconnecting sub-circuits with power-down functionality, new design errors, i.e. short-circuit paths, floating nodes and asymmetrical voltages at matched structures, may emerge in the power-down mode of the resulting hierarchical circuit. This paper presents a new method for the verification

  • Boundary scan based interconnect testing design for silicon interposer in 2.5D ICs
    Integration (IF 1.214) Pub Date : 2020-02-22
    Libao Deng, Ning Sun, Ning Fu

    Interposer-based 2.5-dimensional integrated circuit (2.5D IC) is considered as a promising solution to problems like wire delay and power consumption faced by the semiconductor industry today. Since the interconnect wires in the silicon interposer may be defective during fabrication and assembly, they must be adequately tested to ensure product qualification. This paper presents an efficient interconnect

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