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  • Synthesis of representative critical path circuits considering BEOL variations for deep sub-micron circuits
    Integration (IF 1.214) Pub Date : 2021-01-05
    Changho Han; Taewhan Kim

    The proportion of interconnect delay in the critical path on a chip is increasing and becomes over 20% in sub-10nm technologies, which means in order to capture post-Si performance accurately, the representative critical path circuit should reflect not only FEOL (front-end-of-line) but also BEOL (back-end-of-line) variations. Since the number of BEOL metal layers exceeds ten and the layers have variation

    更新日期:2021-01-12
  • Vulnerable objects detection for autonomous driving: A review
    Integration (IF 1.214) Pub Date : 2021-01-08
    Esraa Khatab; Ahmed Onsy; Martin Varley; Ahmed abouelfarag

    Object detection performed by Autonomous Vehicles (AV)s is a crucial operation that comes ahead of various autonomous driving tasks, such as object tracking, trajectories estimation, and collision avoidance. Dynamic road elements (pedestrians, cyclists, vehicles) impose a greater challenge due to their continuously changing location and behaviour. This paper presents a comprehensive review of the state-of-the-art

    更新日期:2021-01-08
  • An ant colony based mapping of quantum circuits to nearest neighbor architectures
    Integration (IF 1.214) Pub Date : 2021-01-08
    Anirban Bhattacharjee; Chandan Bandyopadhyay; Angshu Mukherjee; Robert Wille; Rolf Drechsler; Hafizur Rahaman

    Although this decade is witnessing tremendous advancements in fabrication technologies for quantum circuits, this industry is facing several design challenges and technological constraints. Nearest Neighbor (NN) enforcement is one such design constraint that demands the physical qubits to be adjacent. In the last couple of years, this domain has made progress starting from designing advanced algorithms

    更新日期:2021-01-08
  • High-performance area-efficient polynomial ring processor for CRYSTALS-Kyber on FPGAs
    Integration (IF 1.214) Pub Date : 2021-01-04
    Zhaohui Chen; Yuan Ma; Tianyu Chen; Jingqiang Lin; Jiwu Jing

    The quantum-resistant attribute is a new design criterion for cryptography algorithms in the era of quantum supremacy. Lattice-based cryptography is proved to be secure against quantum computing. CRYSTALS-Kyber is a lattice-based promising candidate in the post-quantum cryptography standardization process. This paper proposes a high-performance polynomial ring processor for the CRYSTALS-Kyber algorithm

    更新日期:2021-01-04
  • A Survey of FIR Filter Design Techniques: Low-complexity, Narrow Transition-band and Variable Bandwidth
    Integration (IF 1.214) Pub Date : 2020-12-23
    Subhabrata Roy; Abhijit Chandra

    In the present century, digital signal processing (DSP) approaches are considered to be one of the most powerful technologies which may shape the science and technology in coming decades. From 1970 onwards, a drastic revolution took place in a wider domain of DSP which has made it popular in several studies such as radar and sonar signal processing, digital televisions, wireless communication scenarios

    更新日期:2020-12-31
  • Efficient hardware task migration for heterogeneous FPGA computing using HDL-based checkpointing
    Integration (IF 1.214) Pub Date : 2020-12-03
    Hoang-Gia Vu; Takashi Nakada; Yasuhiko Nakashima

    Task migration plays an important role in load balancing and energy savings in data centers. It also challenges service providers to minimize service interruptions during task migration. FPGA computing requires checkpointing as an essential function for hardware task migration. However, the current methods of implementing such a function for FPGAs have a high cost in hardware resources and significant

    更新日期:2020-12-25
  • Partial evaluation based triple modular redundancy for single event upset mitigation
    Integration (IF 1.214) Pub Date : 2020-12-02
    Srinivas Katkoori; Sheikh Ariful Islam; Sujana Kakarla

    We present a design technique, Partial evaluation-based Triple Modular Redundancy (PTMR), for hardening combinational circuits against Single Event Upsets (SEU). The basic ideas of partial redundancy and temporal TMR are used together to harden the circuit against SEUs. The concept of partial redundancy is used to eliminate the gates whose outputs can be determined in advance. We have designed a fault

    更新日期:2020-12-18
  • Orthogonal obfuscation based key management for multiple IP protection
    Integration (IF 1.214) Pub Date : 2020-11-28
    Yuejun Zhang; Jiawei Wang; Pengjun Wang; Xiaoyong Xue; Xiaoyang Zeng

    With the development of system-on-chip (SoC) chips, more and more design houses are cooperating with each other's. How to achieve benefit sharing and key management for multiple intellectual properties (IPs) has become an emergency problem. This work proposes an orthogonal obfuscation method to protect multiple IPs. The proposed method permits cooperators to control the project using different security

    更新日期:2020-12-16
  • Real-time automated register abstraction active power-aware electronic system level verification framework
    Integration (IF 1.214) Pub Date : 2020-12-09
    Gaurav Sharma; Lava Bhargava; Vinod Kumar

    All modern low power system on a chip (SoC) architectures are equipped with an in-built power management system. Every new system is expected to have more features and lower power consumption, resulting in a continuous demand to improve energy efficiency. To cope up with the ever increasing demand, an active power-aware management verification architecture is necessary to minimize the power consumption

    更新日期:2020-12-16
  • Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching
    Integration (IF 1.214) Pub Date : 2020-11-07
    Dimitris Konstantinou; Chrysostomos Nicopoulos; Junghee Lee; Giorgos Dimitrakopoulos

    Multicast on-chip communication is encountered in various cache-coherence protocols targeting multi-core processors, and its pervasiveness is increasing due to the proliferation of machine learning accelerators. In-network handling of multicast traffic imposes additional switching-level restrictions to guarantee deadlock freedom, while it stresses the allocation efficiency of Network-on-Chip (NoC)

    更新日期:2020-12-14
  • Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test
    Integration (IF 1.214) Pub Date : 2020-11-19
    Engin Afacan; Nuno Lourenço; Ricardo Martins; Günhan Dündar

    Rapid developments in semiconductor technology have substantially increased the computational capability of computers. As a result of this and recent developments in theory, machine learning (ML) techniques have become attractive in many new applications. This trend has also inspired researchers working on integrated circuit (IC) design and optimization. ML-based design approaches have gained importance

    更新日期:2020-12-14
  • A 25-Gb/s inductorless SiGe BiCMOS receiver for 100-Gb/s optical links
    Integration (IF 1.214) Pub Date : 2020-12-01
    Shuo Li; Junren Pan; Jin He; Zhiyuan Cao; Hao Wang; Sheng Chang; Qijun Huang

    This paper presents the design and measurements of a 25-Gb/s inductorless optical receiver in a 0.25-μm SiGe BiCMOS process for 100-Gb/s (25-Gb/s × 4 lines) Ethernet. As the first stage of the proposed optical receiver, a transimpedance amplifier (TIA) employing a pseudo-differential structure with a feedback resistor incorporates DC offset cancellation (DOC) to enhance the input dynamic range. Cascaded

    更新日期:2020-12-14
  • Low power time-domain rail-to-rail comparator with a new delay element for ADC applications
    Integration (IF 1.214) Pub Date : 2020-11-20
    Roohollah Sanati; Farzan Khatib; Mohammad Javadian Sarraf; Reihaneh Kardehi Moghaddam

    In this paper, a rail-to-rail time-domain comparator with low power supply voltage and low power consumption is introduced. The comparator can be employed in low-power converters and biomedical applications. In the proposed time-domain comparator, a rail-to-rail delay element has been employed to generate a significant voltage-to-time gain for the full range of input signals. This circuit is designed

    更新日期:2020-12-09
  • VLSI mask optimization: From shallow to deep learning
    Integration (IF 1.214) Pub Date : 2020-11-17
    Haoyu Yang; Wei Zhong; Yuzhe Ma; Hao Geng; Ran Chen; Wanli Chen; Bei Yu

    VLSI mask optimization is one of the most critical stages in manufacturability aware design, which is costly due to the complicated mask optimization and lithography simulation. Recent researches have shown prominent advantages of machine learning techniques dealing with complicated and big data problems, which bring potential of dedicated machine learning solution for DFM problems and facilitate the

    更新日期:2020-12-09
  • Fast algorithms for test optimization of core based 3D SoC
    Integration (IF 1.214) Pub Date : 2020-11-30
    Sabyasachee Banerjee; Subhashis Majumder; Debesh K. Das; Bhargab B. Bhattacharya

    The use of 3D-IC technology has become quite widespread in designing core-based systems-on-chip (SoCs). Concomitantly, testing of cores and inter-layer through-silicon-vias (TSVs) spanning through different layers of 3D chips has become an important problem in the manufacturing cycle. Testing 3D-SoCs is more challenging compared to their 2D counterparts because of the complexity of their design and

    更新日期:2020-12-08
  • RESET: A real-time scheduler for energy and temperature aware heterogeneous multi-core systems
    Integration (IF 1.214) Pub Date : 2020-12-02
    Sanjay Moulik

    Nowadays, multi-core processing systems have to perform complex functionalities on densely packed multi-million gate platforms, making design issues like resource usage efficiency, energy consumption, temperature management of cores, etc. more challenging to handle. Since many of these processing platforms use batteries as their primary source of energy and are prone to an uncontrolled surge in temperatures

    更新日期:2020-12-05
  • An automated parallel simulation flow for cyber-physical system design
    Integration (IF 1.214) Pub Date : 2020-11-28
    Seyed-Hosein Attarzadeh-Niaki; Ingo Sander; Mohammad Ahmadi

    Parallel and distributed simulation (PDS) is often employed to tackle the computational intensity of system-level simulation of real-world complex embedded and cyber-physical systems (CPSs). However, CPS models comprise heterogeneous components with diverge semantics for which incompatible PDS approaches are developed. We propose an automated PDS flow based on a formal modeling framework—with necessary

    更新日期:2020-12-04
  • Robust power grid network design considering EM aging effects for multi-segment wires
    Integration (IF 1.214) Pub Date : 2020-10-19
    Han Zhou; Liang Chen; Sheldon X.-D. Tan

    This paper presents a number of power grid network design and optimization techniques that consider the electromigration (EM) effects for multi-segment interconnect wires. First, we consider a new EM immortality constraint due to EM void saturation volume for multi-segment interconnects. It helps reduce conservativeness in the EM-aware on-chip power grid design. Along with the EM nucleation phase immortality

    更新日期:2020-12-01
  • High speed VLSI architecture for improved region based active contour segmentation technique
    Integration (IF 1.214) Pub Date : 2020-11-13
    Radhika V. Menon; Shantharam Kalipatnapu; Indrajit Chakrabarti

    Active contour segmentation is an important stage in image analysis applications. In this article, an improved region based active contour segmentation is proposed. The proposed active contour model speeds up the contour convergence by up to 40% while maintaining the advantages of a local region based active contour model by reducing the number of iterations. Moreover, we propose a low-complexity pipelined

    更新日期:2020-11-27
  • 30 GHz SiGe active inductor with voltage controlled Q
    Integration (IF 1.214) Pub Date : 2020-11-14
    Jorge Alves Torres; J. Costa Freire

    An active inductor (AI) based on a cascade gyrator for 30 GHz applications implemented with a 0.25 μm in SiGe technology is presented. The gyrator converts not only a key capacitor into an inductor, but also an added resistor, into a negative resistor. This gyrator-RC has its losses compensated by the negative resistor improving the active inductor Q factor. Changing the bias voltage and current allows

    更新日期:2020-11-22
  • A novel tunable gain CMOS buffer amplifier for large resistive loads
    Integration (IF 1.214) Pub Date : 2020-11-04
    Jayachandran Remya; P.C. Subramaniam; K.J. Dhanaraj

    An all-OTA analog buffer amplifier configuration capable of driving large resistive loads is presented. The proposed configuration features high input swing, gain tunability, wide-bandwidth, and low design complexity. The concept is validated with simulation results in Cadence Virtuoso using SCL 0.18-μm technology parameters. Using a ±0.9 V power supply, the buffer with a gain of 1, can drive a 1 Vp−p

    更新日期:2020-11-21
  • Compact and efficient structure of 8-bit S-box for lightweight cryptography
    Integration (IF 1.214) Pub Date : 2020-11-05
    Bahram Rashidi

    In this paper, we design an inversion-based S-box with better hardware implementation than the AES S-box with similar cryptographic properties. The proposed S-box computation involves basically two steps, the field inversion, and the affine transformation. The constructed S-box uses a cost-efficient affine transformation with low area resources and low critical path delay (CPD). The sub-blocks of the

    更新日期:2020-11-06
  • Invasive weed optimization based scheduling for digital microfluidic biochip operations
    Integration (IF 1.214) Pub Date : 2020-10-14
    Kolluri Rajesh; Sumanta Pyne

    Digital Microfluidic Biochips (DMFBs) based on electro-wetting-on-dielectric (EWOD) technology are a class of lab-on-a-chip (LOC) devices. DMFBs can efficiently carry out biochemical analysis and have many advantages over the traditional laboratory system. DMFBs offer miniaturization, automation, and programmability. Resource-constrained scheduling is the first and vital step of fluidic-level synthesis

    更新日期:2020-10-30
  • Comments on “Improved designs of digit-by-digit decimal multiplier”
    Integration (IF 1.214) Pub Date : 2020-10-15
    Mojtaba Valinataj; Zahra Yazdanian Amiri

    Decimal multiplication is one of the complex operations in the applications that still radix-10 representations are preferred. To improve the performance, Ahmed et al. proposed some fast and area efficient binary-to-decimal converters to be used for both partial product generation and partial product reduction stages of digit-by-digit decimal multiplication. These converters that transform each binary

    更新日期:2020-10-30
  • A novel approach to fractional-N PLLs generating ultra-fast low-noise chirps for FMCW radar
    Integration (IF 1.214) Pub Date : 2020-10-11
    Frank Herzel; Arzu Ergintav; Gunter Fischer

    This paper presents a novel approach to generate ultra-fast chirps for frequency-modulated continuous wave (FMCW) radar systems. A symmetric triangular frequency chirp is analyzed. A very large loop bandwidth could minimize the PLL settling time, but would result in a high phase noise and in large spurs. This work minimizes the settling times without using an excessive loop bandwidth. Rather, the initial

    更新日期:2020-10-30
  • COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing
    Integration (IF 1.214) Pub Date : 2020-10-20
    Inga Abel; Maximilian Neuner; Helmut Graeb

    This paper presents a new method to automate the sizing of analog circuits. The method emulates the manual design procedure. The sizing task is formulated as a constraint programming problem. Two new algorithms are introduced: First, a hierarchical structural analysis of functional blocks that automatically sets up the analytical equations for the sizing. And second, a heuristic to guide the branching

    更新日期:2020-10-30
  • A PVT aware differential delay circuit and its performance variation due to power supply noise
    Integration (IF 1.214) Pub Date : 2020-10-14
    Anirban Tarafdar; Abir J. Mondal; Uttam K. Bera; B.K. Bhattacharyya

    Delay circuits are one of the key components in time domain blocks such as pulse width modulator. This work describes the working of a differential delay circuit under process, voltage and temperature. The proposed design is also coupled to a typical power delivery network (PDN) and a central processing unit (CPU) core ramping current from 0 A to 10–40A in 10 ns Simulated in a 90-nm CMOS technology

    更新日期:2020-10-30
  • Monolithic 3D stacked multiply-accumulate units
    Integration (IF 1.214) Pub Date : 2020-10-29
    Young Seo Lee; Kyung Min Kim; Ji Heon Lee; Young-Ho Gong; Seon Wook Kim; Sung Woo Chung

    The monolithic 3D stacking (M3D) reduces the critical path delay, leveraging 1) short latency of a monolithic inter-tier via (MIV) and 2) short 2D interconnect and cell delay through smaller footprint. In this paper, we propose M3D stacked multiply-accumulate (MAC) units; MAC units have a relatively large number of long wires. With the Samsung 28 nm ASIC library, the M3D stacked MAC units reduce the

    更新日期:2020-10-30
  • Accelerating Deep Convolutional Neural Network base on stochastic computing
    Integration (IF 1.214) Pub Date : 2020-09-29
    Mohamad Hasani Sadi; Ali Mahani

    Deep Convolutional Neural Networks (DCNNs) are highly computational, and low budget platforms face many restrictions due to their implementation. Recently, Stochastic Computing (SC) demonstrated satisfying solution with simple and low power arithmetic units. In this paper, we present a highly efficient SC-based inference framework of DCNNs. We first propose a new Approximate Parallel Counter (APC)

    更新日期:2020-10-17
  • Electronically tunable third-order dual-mode quadrature sinusoidal oscillators employing VDCCs and all grounded components
    Integration (IF 1.214) Pub Date : 2020-09-15
    Suvajit Roy; Radha Raman Pal

    Two new configurations of third-order dual-mode (i.e. both voltage and current mode) quadrature sinusoidal oscillator using a newly reported active block, called the voltage differencing current conveyor (VDCC) have been presented in this manuscript. Both the proposed oscillators employ two VDCCs, three capacitors, and three resistors. The circuits are suitable for integrated circuit (IC) realization

    更新日期:2020-09-29
  • The Involution Tool for Accurate Digital Timing and Power Analysis
    Integration (IF 1.214) Pub Date : 2020-09-22
    Daniel Öhlinger; Jürgen Maier; Matthias Függer; Ulrich Schmid

    We introduce the prototype of a digital timing simulation and power analysis tool for integrated circuits that supports the involution delay model (Függer et al. 2019). Unlike the pure and inertial delay models typically used in digital timing analysis tools, the involution model faithfully captures short pulse propagation and related effects. Our Involution Tool facilitates experimental accuracy evaluation

    更新日期:2020-09-25
  • Custom NoC topology generation using Discrete Antlion Trapping Mechanism
    Integration (IF 1.214) Pub Date : 2020-09-10
    Poornima Narayanasamy; Seetharaman Gopalakrishnan; Santhi Muthurathinam

    This paper outlines an innovative and creative algorithm known as Discrete Antlion Trapping Mechanism (DATM). It imitates the hunting mechanism of antlions in nature. The proposed DATM is incorporated in Network on Chip (NoC) which is a replacement to standard transmission technique along with the Reliable Reconfigurable Real-Time Operating System (R3TOS) for intertask communications. Though there

    更新日期:2020-09-24
  • 2.3–21 GHz broadband and high linearity distributed low noise amplifier
    Integration (IF 1.214) Pub Date : 2020-09-14
    El Bakkali Moustapha; Elftouh Hanae; Amar Touhami Naima; Elhamadi Taj-eddin

    This paper focuses on the design of a 2.3–21 GHz Distributed Low Noise Amplifier (LNA) with low noise figure (NF), high gain (S21), and high linearity (IIP3) for broadband applications. This distributed amplifier (DA) includes S/C/X/Ku/K-band, which makes it very suitable for heterodyne receivers. The proposed DA uses a 0.18 μm GaAs pHEMT process (OMMIC ED02AH) in cascade architecture with lines adaptation

    更新日期:2020-09-22
  • A low latency modular-level deeply integrated MFCC feature extraction architecture for speech recognition
    Integration (IF 1.214) Pub Date : 2020-09-16
    Bibin Sam Paul S; Antony Xavier Glittas; Lakshminarayanan Gopalakrishnan

    In this paper, a low-complex chip to extract the Mel Frequency Cepstral Coefficient for a speech recognition system is presented. The architecture can operate in a continuous-flow manner to process streaming or the stored speech signal at high speed. The frame-overlap Hamming window, DFT and Mel-filter bank computations are deeply integrated to share memory buffers and avoid bit-reversal circuit to

    更新日期:2020-09-22
  • Low delay non-binary error correction codes based on Orthogonal Latin Squares
    Integration (IF 1.214) Pub Date : 2020-09-09
    Francisco Garcia-Herrero; Alfonso Sánchez-Macián; Juan Antonio Maestro

    Due to the scaling of technology and the environment effects, such as radiation, memory systems that are on board of spacecraft such as satellites, are more sensitive to errors. This kind of error is difficult to predict and its correction in real-time is crucial for the correct behavior of the whole system. In this paper, a low delay fully parallel non-binary decoder based on orthogonal Latin squares

    更新日期:2020-09-21
  • An improved heuristic technique for nearest neighbor realization of quantum circuits in 2D architecture
    Integration (IF 1.214) Pub Date : 2020-09-11
    Anirban Bhattacharjee, Chandan Bandyopadhyay, Philipp Niemann, Bappaditya Mondal, Rolf Drechsler, Hafizur Rahaman

    Last couple of years has witnessed tremendous advancements in the field of quantum computing and even it has started providing technological footprints in the design industry. Though advancements in the physical implementation of quantum circuits has taken a giant leap but it has faced with several design challenges and one such design constraint is Nearest Neighbor (NN) criteria which demands the

    更新日期:2020-09-11
  • MOS based pseudo-resistors exhibiting Tera Ohms of Incremental Resistance for biomedical applications: Analysis and proof of concept
    Integration (IF 1.214) Pub Date : 2020-08-30
    Kulbhushan Sharma, Anisha Pathania, Rahul Pandey, Jaya Madan, Rajnish Sharma

    Performance of biomedical analog circuits vitiates due to non-linear V-R characteristics of Pseudo-resistor (PR) structure, their excess dependency over Process Voltage Temperature (PVT) and common mode variations. In this paper, Incremental Resistance (IR) expressions, V-R curves and statistical results for wider PVT variations for diverse categories of non-tunable and tunable PR structures have been

    更新日期:2020-08-30
  • Power-aware hold optimization for ASIC physical synthesis
    Integration (IF 1.214) Pub Date : 2020-08-28
    Mohamed Chentouf, Foffie Stevmelin, Zine El Abidine Alaoui Ismaili

    Hold timing closure is an important milestone at the physical design phase of every Application Specific Integrated Circuit (ASIC). Many approaches have been proposed by different researchers and commercial Electronic Design Automation (EDA) providers to fix hold timing violations, but there has been no effort to study the impact of each technique on power consumption. Nowadays, the rise of low power

    更新日期:2020-08-28
  • READ: A fixed restoring array based accuracy-configurable approximate divider for energy efficiency
    Integration (IF 1.214) Pub Date : 2020-08-22
    Neelam Arya, Teena Soni, Manisha Pattanaik, G.K. Sharma

    Energy efficiency has emerged as one of the most essential design parameters in contemporary computing system design. Approximate computing is a new computing paradigm to achieve energy efficiency by trading-off energy/area/latency improvements with accuracy for error-resilient applications. This paper proposes Reconfigurable Energy-efficient Approximate Divider (READ) that achieves several energy–quality

    更新日期:2020-08-22
  • On reverse converters for arbitrary multi-moduli RNS
    Integration (IF 1.214) Pub Date : 2020-08-20
    Piotr Patronik

    In this paper, we propose a new design of reverse converters for residue number systems with arbitrary moduli sets consisting of any number of odd moduli and one even modulus of the type 2k. The new converters are arithmetic-based designs, that may be implemented using only arithmetic components without any read-only memories nor lookup tables. We tackle the problem of large modular reduction imposed

    更新日期:2020-08-20
  • Refinement Rules for the Automatic TLM-to-RTL Conversion of Temporal Assertions
    Integration (IF 1.214) Pub Date : 2020-08-17
    Laurence PIERRE

    Today’s systems on chip (SoCs) require a complex design and verification process. In early design stages, high-level debugging of the SoC functionality is feasible on TLM (Transaction-Level Modeling) descriptions. To ease debugging of such SoC’s models, Assertion-Based Verification (ABV) enables the runtime verification of temporal properties. In the last design stages, RTL (Register Transfer Level)

    更新日期:2020-08-17
  • High-throughput architecture for post-quantum DME cryptosystem
    Integration (IF 1.214) Pub Date : 2020-08-02
    José L. Imaña, Ignacio Luengo

    Quantum computers have the potential to solve difficult mathematical problems efficiently, therefore meaning an important threat to Public-Key Cryptography (PKC) if large-scale quantum computers are ever built. The goal of Post-Quantum Cryptography (PQC) is to develop cryptosystems that are secure against both classical and quantum computers. DME is a new proposal of quantum-resistant PKC algorithm

    更新日期:2020-08-02
  • Time-domain writing architecture for multilevel RRAM cells resilient to temperature and process variations
    Integration (IF 1.214) Pub Date : 2020-08-01
    Amadeo de Gracia Herranz, Marisa Lopez-Vallejo

    The high potential of memristors as multilevel resistance devices is undermined by their highly non-linear behaviour and a strong dependency on different sources of variability (process, voltage, temperature…). Temperature fluctuations are specially harmful because small thermal variations may significantly modify the operation point of the device. For these reasons the circuitry required to accurately

    更新日期:2020-08-01
  • Harvester-aware transient computing: Utilizing the mechanical inertia of kinetic energy harvesters for a proactive frequency-based power loss detection
    Integration (IF 1.214) Pub Date : 2020-07-27
    Carl C. Rheinländer, Norbert Wehn

    Power-neutral system design avoids energy buffers by directly powering the load by the energy harvester. In case of a power loss, checkpointing methods ensure forward progress by preserving the volatile system state using non-volatile memories. The timely detection of upcoming power losses is essential for a reliable checkpointing process. Moreover, various applications require early detections to

    更新日期:2020-07-27
  • Area and power efficient hard multiple generator for radix-8 modulo 2n − 1 multiplier
    Integration (IF 1.214) Pub Date : 2020-07-25
    Naveen Kr Kabra, Zuber M. Patel

    In this paper, we introduce an area and power efficient algorithm to design a hard multiple generator for radix-8 modulo 2n − 1 multiplier, which is based on parallel prefix computation of carry propagate. Only odd carry is used to generate hard multiple bits. The proposed architecture uses ⌈log2n⌉-2 prefix level with n2 prefix operators. The Post-synthesis result of proposed architecture shows 27

    更新日期:2020-07-25
  • On the quadrature accuracy of in-phase coupled quadrature LC oscillator
    Integration (IF 1.214) Pub Date : 2020-07-24
    Mahsa Hadjmohammadi, Hossein Miar Naimi, Hojat Ghonoodi

    In this article, closed-form equations are proposed for phase and amplitude errors of an in-phase coupled quadrature LC oscillator. First of all, the injected current from coupling network to switching one is analytically calculated in a novel approach. Then, fundamental equations are obtained to derive phase and amplitude errors which are results of mismatches of the tank's inductors, capacitors and

    更新日期:2020-07-24
  • Investigating the influence of adiabatic load on the 4-phase adiabatic system design
    Integration (IF 1.214) Pub Date : 2020-07-06
    Himadri Singh Raghav, V.A. Bartlett

    This paper investigates the power-clock generation using Step Charging Circuits (SCC). In particular, the impact of the adiabatic load on the energy dissipation of the 4-phase Power-Clock Generator (PCG) and on the overall adiabatic system is investigated. The adiabatic implementations are compared with their conventional CMOS counterparts based on energy dissipation, the number of transistors and

    更新日期:2020-07-06
  • Low-power content addressable memory design using two-layer P-N match-line control and sensing
    Integration (IF 1.214) Pub Date : 2020-07-04
    Sheikh Wasmir Hussain, Telajala Venkata Mahendra, Sandeep Mishra, Anup Dandapat

    Content addressable memory (CAM) is a specialized search engine mostly used for speeding memory lookup in network devices. Despite fast searching, activation of all comparison circuits in every clock cycle costs huge power. Power dissipation is more severe in high capacitive NOR match-line (ML) because of higher precharge activity and multiple transitions in ML. This paper proposes a two-layer ML scheme

    更新日期:2020-07-04
  • An efficient multiple shortest augmenting paths algorithm for constructing high performance VLSI subarray
    Integration (IF 1.214) Pub Date : 2020-07-01
    Junyan Qian, Bisheng Huang, Hao Ding, Zhide Zhou, Lingzhong Zhao, Zhongyi Zhai

    Reconfiguring a high-performance subarray of a VLSI array with faults is to construct a maximum target array with the minimum number of long interconnects, which can reduce communication costs, capacitance and dynamic energy dissipation. An existing work proved that the high performance VLSI subarray can be constructed in polynomial time using network flow algorithm. However, because of the disadvantage

    更新日期:2020-07-01
  • A high-efficiency charge pump with charge recycling scheme and finger boost capacitor
    Integration (IF 1.214) Pub Date : 2020-07-01
    Hui Peng, Herbert De Pauw, Pieter Bauwens, Jan Doutreloigne

    A 16-phase 8-branch charge pump with finger boost capacitor is proposed to increase the power efficiency and it is implemented in a 0.35 μm high-voltage CMOS IC technology. Compared with the standard capacitor, the finger capacitor can significantly reduce the parasitic capacitance. By combining the charge recycling method and the finger capacitor, the proposed four-stage charge pump can achieve an

    更新日期:2020-07-01
  • Design space exploration of low-power flip-flops in FinFET technology
    Integration (IF 1.214) Pub Date : 2020-06-26
    Ehsan Mahmoodi, Morteza Gholipour

    As technology evolves, new devices emerge to overcome the known short-channel effects of conventional MOSFETs. FinFETs, as recent devices, are widely used in modern processor designs. Elaborate design of circuit elements can effectively increase the overall chip performance. In this paper we studied the design of high performance flip-flop (FF) using FinFET devices. We have investigated several transistor

    更新日期:2020-06-26
  • Avoidance vs. repair: New approaches to increasing electromigration robustness in VLSI routing
    Integration (IF 1.214) Pub Date : 2020-06-10
    Steve Bigalke, Jens Lienig

    Studies on further IC development mutually predict that the reliability of future integrated circuits (ICs) will be severely endangered by the occurrence of electromigration (EM). The reason for the increasing number of EM damages are the ongoing structural reductions in the IC. Digital circuits are particularly at risk because they have been neglected in the consideration of EM, resulting in a lack

    更新日期:2020-06-10
  • Graph-based STA for asynchronous controllers
    Integration (IF 1.214) Pub Date : 2020-06-09
    Stavros Simoglou, Nikolaos Xiromeritis, Christos Sotiriou, Nikolaos Sketopoulos

    We present a Graph-based Asynchronous Static Timing Analysis (ASTA) methodology for Asynchronous Control Circuits, which pessimistically computes Critical Cycle(s), instead of Critical Paths, without cycle cutting. Its additional requirement over STA is a graph-based Event Model, Marked Graph or Petri Net. We contrast STA, ASTA results for 23 asynchronous circuit benchmarks, and demonstrate significant

    更新日期:2020-06-09
  • A passive and low-complexity Compressed Sensing architecture based on a charge-redistribution SAR ADC
    Integration (IF 1.214) Pub Date : 2020-05-31
    Carmine Paolino, Luciano Prono, Fabio Pareschi, Mauro Mangia, Riccardo Rovatti, Gianluca Setti

    An innovative analog-to-digital converter (ADC) architecture is proposed, with the aim of acquiring an input signal according to the Compressed Sensing (CS) paradigm and without the need for dedicated active analog blocks. Its core is the capacitive array employed in traditional successive-approximation-register (SAR) ADCs. Introducing only a few additional switches, the array can compute the linear

    更新日期:2020-05-31
  • An ultra-wideband 6–14 GHz frequency modulated continuous wave primary radar with 3 cm range resolution
    Integration (IF 1.214) Pub Date : 2020-05-31
    Tom Drechsel, Niko Joram, Frank Ellinger

    This paper describes the design and verification of an ultra-wideband 6–14 GHz frequency modulated continuous wave (FMCW) primary radar system with very high range resolution. The design and measurement results of the utilized signal generator and receiver are presented. The signal generator features a 86% relative continuous tuning range and average phase noise of −106 dBc/Hz at 1 MHz offset to the

    更新日期:2020-05-31
  • A new realization scheme for dynamic PFSCL style
    Integration (IF 1.214) Pub Date : 2020-05-29
    Ranjana Sivaram, Kirti Gupta, Neeta Pandey

    In this paper, a new scheme of logic function realization in dynamic positive feedback source-coupled logic (D-PFSCL) style is proposed. The existing scheme implements only NOR/OR based realization of a logic function. Thus, a complex function in D-PFSCL has high gate count which degrades the overall circuit performance measured in terms of power and delay. This paper therefore aims to resolve the

    更新日期:2020-05-29
  • Sensor based adaptive voltage scaling on FPGAs: Calibration and parametrization
    Integration (IF 1.214) Pub Date : 2020-05-29
    Christoph Niemann, Munawar Ali, Obaid Ullah Shah, Jakob Heller, Dirk Timmermann

    The impacts of aging and process variations on the performance of VLSI systems is increasing with each process generation. The conventional way to counteract them are extensive guard bands, which are calculated at system design time. Hence, they are necessarily worst case guard bands, i.e., most often too pessimistic. Current research tries to mitigate this by means of in-situ performance measurement

    更新日期:2020-05-29
  • System-level evaluation of dynamic effects in a GaN-based class-E power amplifier
    Integration (IF 1.214) Pub Date : 2020-05-29
    Andrea Minetto, Bernd Deutschmann, Oliver Häberlen, Gilberto Curatola

    Gallium Nitride shows huge potential in power electronics applications thanks to the superior intrinsic material properties which result in improved performance both at device level and system level. Great effort has been taken in recent years to industrialize GaN technology and to solve some of the major drawbacks like reliability issues and dynamic effects. The goal of this work is to propose a novel

    更新日期:2020-05-29
  • New lightweight Anti-SAT block design and obfuscation technique to thwart removal attack
    Integration (IF 1.214) Pub Date : 2020-05-29
    Vijaypal Singh Rathor, Bharat Garg, G.K. Sharma

    Logic locking has emerged as a prominent technique to protect an integrated circuit from piracy, overbuilding, and hardware Trojans. Most of the well-known logic locking techniques are vulnerable to satisfiability (SAT) based attack. Though several SAT-resistant logic locking techniques such as Anti-SAT block (ASB) are reported that increase the time to decipher the secret key, the existing techniques

    更新日期:2020-05-29
  • Verification of a high precision CMOS sensor for angle-of-arrival (AOA) measurement of LED light in ultra-miniaturized applications
    Integration (IF 1.214) Pub Date : 2020-05-26
    André Feiler, Dominik Veit, Lukas Straczek, Jürgen Oehm

    In this study a specially revised version of the concept for measuring the angle-of-arrival (AOA) of incidence light was used, which is particularly well suited for the construction of trigonometric sensor concepts with external dimensions of only a few millimeters. The aim of the study was to break down the interrelationships for the overall systemically achievable accuracies. The study therefore

    更新日期:2020-05-26
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