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  • A passive and low-complexity Compressed Sensing architecture based on a charge-redistribution SAR ADC
    Integration (IF 1.15) Pub Date : 2020-05-31
    Carmine Paolino; Luciano Prono; Fabio Pareschi; Mauro Mangia; Riccardo Rovatti; Gianluca Setti

    An innovative analog-to-digital converter (ADC) architecture is proposed, with the aim of acquiring an input signal according to the Compressed Sensing (CS) paradigm and without the need for dedicated active analog blocks. Its core is the capacitive array employed in traditional successive-approximation-register (SAR) ADCs. Introducing only a few additional switches, the array can compute the linear

  • An ultra-wideband 6–14 GHz frequency modulated continuous wave primary radar with 3 cm range resolution
    Integration (IF 1.15) Pub Date : 2020-05-31
    Tom Drechsel; Niko Joram; Frank Ellinger

    This paper describes the design and verification of an ultra-wideband 6–14 GHz frequency modulated continuous wave (FMCW) primary radar system with very high range resolution. The design and measurement results of the utilized signal generator and receiver are presented. The signal generator features a 86% relative continuous tuning range and average phase noise of −106 dBc/Hz at 1 MHz offset to the

  • A new realization scheme for dynamic PFSCL style
    Integration (IF 1.15) Pub Date : 2020-05-29
    Ranjana Sivaram; Kirti Gupta; Neeta Pandey

    In this paper, a new scheme of logic function realization in dynamic positive feedback source-coupled logic (D-PFSCL) style is proposed. The existing scheme implements only NOR/OR based realization of a logic function. Thus, a complex function in D-PFSCL has high gate count which degrades the overall circuit performance measured in terms of power and delay. This paper therefore aims to resolve the

  • Sensor based adaptive voltage scaling on FPGAs: Calibration and parametrization
    Integration (IF 1.15) Pub Date : 2020-05-29
    Christoph Niemann; Munawar Ali; Obaid Ullah Shah; Jakob Heller; Dirk Timmermann

    The impacts of aging and process variations on the performance of VLSI systems is increasing with each process generation. The conventional way to counteract them are extensive guard bands, which are calculated at system design time. Hence, they are necessarily worst case guard bands, i.e., most often too pessimistic. Current research tries to mitigate this by means of in-situ performance measurement

  • System level evaluation of dynamic effects in a GaN-based class-E power amplifier
    Integration (IF 1.15) Pub Date : 2020-05-29
    Andrea Minetto; Bernd Deutschmann; Oliver Häberlen; Gilberto Curatola

    Gallium Nitride shows huge potential in power electronics applications thanks to the superior intrinsic material properties which result in improved performance both at device level and system level. Great effort has been taken in recent years to industrialize GaN technology and to solve some of the major drawbacks like reliability issues and dynamic effects. The goal of this work is to propose a novel

  • New lightweight Anti-SAT block design and obfuscation technique to thwart removal attack
    Integration (IF 1.15) Pub Date : 2020-05-29
    Vijaypal Singh Rathor; Bharat Garg; G.K. Sharma

    Logic locking has emerged as a prominent technique to protect an integrated circuit from piracy, overbuilding, and hardware Trojans. Most of the well-known logic locking techniques are vulnerable to satisfiability (SAT) based attack. Though several SAT-resistant logic locking techniques such as Anti-SAT block (ASB) are reported that increase the time to decipher the secret key, the existing techniques

  • Verification of a high precision CMOS sensor for angle-of-arrival (AOA) measurement of LED light in ultra-miniaturized applications
    Integration (IF 1.15) Pub Date : 2020-05-26
    André Feiler; Dominik Veit; Lukas Straczek; Jürgen Oehm

    In this study a specially revised version of the concept for measuring the angle-of-arrival (AOA) of incidence light was used, which is particularly well suited for the construction of trigonometric sensor concepts with external dimensions of only a few millimeters. The aim of the study was to break down the interrelationships for the overall systemically achievable accuracies. The study therefore

  • The synthesis method of logic circuits based on the iMemComp gates
    Integration (IF 1.15) Pub Date : 2020-05-22
    Xiaole Cui; Qiujun Lin; Xiaoxin Cui; Feng Wei; Xiaoyan Liu; Jinfeng Kang

    The iMemComp is a family of logic gates based on RRAM devices. It has potential advantage on the design of high-performance logic circuits, since the NAND, AND, NOT and transmission iMemComp gates only consume single cycle, respectively. However, the synthesis method of logic circuits based on the iMemComp gates has not been systematically studied before. This work proposes the synthesis method of

  • A fast approach for bitcoin blockchain cryptocurrency mining system
    Integration (IF 1.15) Pub Date : 2020-05-19
    Le Vu Trung Duong; Nguyen Thi Thanh Thuy; Lam Duc Khai

    The growth of the blockchain-based cryptocurrencies has attracted a lot of attention from a variety of fields, especially in academic research. One of them is Bitcoin, the most popular and highest valued cryptocurrency on the market. The SHA256 is the main processing part in Bitcoin mining, to date the difficulty of which is extremely high and still increases relentlessly. Hence, it is essential to

  • Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training
    Integration (IF 1.15) Pub Date : 2020-05-14
    TaiYu Cheng; Yukata Masuda; Jun Chen; Jaehoon Yu; Masanori Hashimoto

    Recently, emerging “edge computing” moves data and services from the cloud to nearby edge servers to achieve short latency and wide bandwidth, and solve privacy concerns. However, edge servers, often embedded with GPU processors, highly demand a solution for power-efficient neural network (NN) training due to the limitation of power and size. Besides, according to the nature of the broad dynamic range

  • A cellular automata guided two level obfuscation of Finite-State-Machine for IP protection
    Integration (IF 1.15) Pub Date : 2020-05-14
    Rajit Karmakar; Suman Sekhar Jana; Santanu Chattopadhyay

    A popular countermeasure against IP piracy is to obfuscate the Finite State Machine (FSM) which is assumed to be the heart of a digital system. Most of the existing FSM obfuscation strategies rely on additionally introduced set of obfuscation mode state-transitions to protect the original state-transitions of the FSM. Although these methods assume that it is difficult to extract the FSM behavior from

  • SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage
    Integration (IF 1.15) Pub Date : 2020-05-11
    Taehwan Kim; Kwangok Jeong; Jungyun Choi; Taewhan Kim; Kyumyung Choi

    Low power design by near-threshold voltage (NTV) operation is very attractive since it affords to considerably mitigate the sharp increase of power dissipation. However, one key barrier for the use of NTV operation is the significant increase of the SRAM failure. In this work, we propose an on-chip SRAM monitoring methodology that is able to accurately predict the minimum voltage, Vddmin, on each die

  • PCoSA: A product error correction code for use in memory devices targeting space applications
    Integration (IF 1.15) Pub Date : 2020-05-10
    David Freitas; David Mota; Roger Goerl; César Marcon; Fabian Vargas; Jarbas Silveira; João Mota

    The radiation sensitivity of integrated memory cells increases dramatically as the supply voltage decreases. Although there are some Error Correcting Code (ECC) studies to prevent faults on memories used in space applications, there is no consensus on choosing the best ECC product-type with two-dimensional Hamming to mitigate data faults in memory. This work introduces the Product Code for Space Applications

  • An efficient background calibration technique for analog-to-digital converters based on neural network
    Integration (IF 1.15) Pub Date : 2020-05-07
    Honghui Deng; Yijun Hu; Liang Wang

    This paper introduces a background digital calibration algorithm based on neural network, which can adaptively calibrate multiple non-ideal factors in a single-channel ADC, such as gain error, mismatch, offset and harmonic distortion. It enables an efficient background calibration through a simple feed forward neural network and LM gradient descent algorithm. The simulation results show that in the

  • Yield constrained automated design algorithm for power optimized pipeline ADC
    Integration (IF 1.15) Pub Date : 2020-05-04
    Vala Sadrafshari; Shamin Sadrafshari; Mohammad Sharifkhani

    Pipeline Analog to Digital Converter (ADC) design processes include several redesign steps to achieve the optimum solution. Hence, designers prefer to use automated algorithms for this purpose. In this paper, an automated algorithm for CAD tool is presented considering the trade-off between yield and power consumption for pipeline ADCs. This automated algorithm benefits from multiple degrees of freedom

  • A bulk-driven quasi-floating gate FVF current mirror for low voltage, low power applications
    Integration (IF 1.15) Pub Date : 2020-04-30
    Mounira Bchir; Imen Aloui; Nejib Hassen

    This paper introduces a new low-voltage, low-power FVF current mirror circuit. The bulk-driven (BD) technique is employed to achieve extended input voltage swing and low supply voltage. Besides, the quasi-floating gate (QFG) is used to achieve high frequency performance. The merging of (BD) and (QFG) appear as a good and attractive solution to improve the circuit performance with reduced supply voltage

  • A 0.3nV/√Hz input-referred-noise analog front-end for radiation-induced thermo-acoustic pulses
    Integration (IF 1.15) Pub Date : 2020-04-30
    Elia A. Vallicelli; Davide Turossi; Luca Gelmi; Alessandro Baù; Roberto Bertoni; Walter Fulgione; Alessandro Quintino; Massimo Corcione; Andrea Baschirotto; Marcello De Matteis

    This paper presents the design and the experimental characterization of a complete acoustic analog front-end (A-AFE) read-out channel for detecting thermo-acoustic pulses induced by heavy-charged particles interacting with matter. The most relevant applications are in particle physics experiments (bubble chambers for Dark Matter Weakly Interacting Massive Particles (WIMPs) detection) and biomedical

  • Design of a real-time face detection architecture for heterogeneous systems-on-chips
    Integration (IF 1.15) Pub Date : 2020-04-28
    Fanny Spagnolo; Stefania Perri; Pasquale Corsonello

    Object detection represents one of the most important and challenging task in computer vision applications. Boosting-based approaches deal with computational intensive operations and they involve several sequential tasks that make very difficult developing hardware implementations with high parallelism level. This work presents a new hardware architecture able to perform object detection based on a

  • On the superiority of modularity-based clustering for determining placement-relevant clusters
    Integration (IF 1.15) Pub Date : 2020-04-23
    Mateus Fogaça; Andrew B. Kahng; Eder Monteiro; Ricardo Reis; Lutong Wang; Mingyu Woo

    In advanced technology nodes, IC implementation faces increasing design complexity as well as ever-more demanding design schedule requirements. This raises the need for new decomposition approaches that can help reduce problem complexity, in conjunction with new predictive methodologies that can help avoid bottlenecks and loops in the physical implementation flow. Notably, with modern design methodologies

  • Verification and revision of the power-down mode for hierarchical analog circuits
    Integration (IF 1.15) Pub Date : 2020-03-02
    Maximilian Neuner; Helmut Graeb

    Specialized power-down circuitry can switch off an analog circuit when not required for system operation. When interconnecting sub-circuits with power-down functionality, new design errors, i.e. short-circuit paths, floating nodes and asymmetrical voltages at matched structures, may emerge in the power-down mode of the resulting hierarchical circuit. This paper presents a new method for the verification

  • An adaptive simulation framework for AMS-RF test quality
    Integration (IF 1.15) Pub Date : 2020-03-18
    Valentin Gutierrez; Gildas Leger

    Ensuring the quality of a circuit implies ensuring the quality of test. Despite the fact that performance-based testing has been the golden standard for Analog, Mixed-Signal and RF test for decades, high-reliability markets like automotive have found that functional test leaves some potential defects undetected that can produce in-field failure. There is thus a push towards defect-oriented testing

  • FPGA implementation of high-performance, resource-efficient Radix-16 CORDIC rotator based FFT algorithm
    Integration (IF 1.15) Pub Date : 2020-04-16
    Ankur Changela; Mazad Zaveri; Deepak Verma

    The fast Fourier transform (FFT) is an algorithm widely used to compute the discrete Fourier transform (DFT) in real-time digital signal processing. High-performance with fewer resources is highly desirable for any real-time application. Our proposed work presents the implementation of the radix-2 decimation-in-frequency (R2DIF) FFT algorithm based on the modified feed-forward double-path delay commutator

  • Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC
    Integration (IF 1.15) Pub Date : 2020-04-15
    Sanjay Vidhyadharan; Surya Shankar Dan; S.V. Abhay; Ramakant Yadav; Simhadri Hariprasad

    This paper presents a highly efficient ternary flash ADC, designed using the innovative gate-overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have on-state currents Ion more than double, while the off-state currents Ioff remaining at least an order of magnitude lower than the corresponding values of the standard 45 nm CMOS technology with the same width. Replacing MOSFETs

  • An efficient and reliable MRF-based methodology for designing low-power VLSI circuits
    Integration (IF 1.15) Pub Date : 2020-04-10
    Sayyed Mohammad Razavi; Seyyed Mohammad Razavi

    Noise-interference is one of the major concerns in low-power VLSI circuits. Due to power supply downscaling, these circuits have an extremely limited noise margin that is inadequate for dealing with intrinsic and extrinsic noise. The MRF-based design has been accepted as a highly effective method for designing noise-tolerant low-power circuits. However, the MRF-based circuits suffer from a complex

  • An innovative two-stage data compression scheme using adaptive block merging technique
    Integration (IF 1.15) Pub Date : 2020-03-26
    Harpreet Vohra; Ashima Singh; Sukhpal Singh Gill

    Test data has increased enormously owing to the rising on-chip complexity of integrated circuits. It further increases the test data transportation time and tester memory. The non-correlated test bits increase the issue of the test power. This paper presents a two-stage block merging based test data minimization scheme which reduces the test bits, test time and test power. A test data is partitioned

  • Improving power analysis attack resistance using intrinsic noise in 3D ICs
    Integration (IF 1.15) Pub Date : 2020-03-21
    Zhiming Zhang; Jaya Dofe; Qiaoyan Yu

    Three-dimensional (3D) integration is envisioned as a natural defense to thwart side-channel analysis (SCA) attacks on the hardware implementation of cryptographic algorithms. However, neither physical experiments nor quantitative analysis is available in existing works to study the impact of power distribution network (PDN) on the SCA attacks. Through quantitative analyses and experiments with realistic

  • Methods increasing inherent resistance of ECC designs against horizontal attacks
    Integration (IF 1.15) Pub Date : 2020-03-20
    Ievgen Kabin; Zoya Dyka; Dan Klann; Peter Langendoerfer

    Due to the nature of applications such as critical infrastructure and the Internet of Things etc. side channel analysis attacks are becoming a serious threat. Side channel analysis attacks take advantage from the fact that the behaviour of crypto implementations can be observed and provides hints that simplify revealing keys. A new type of SCA is the so called horizontal differential SCA. In this paper

  • In-sensor time-domain classifiers using pseudo sigmoid activation functions
    Integration (IF 1.15) Pub Date : 2020-03-13
    Ethan Chen; Vanessa Chen

    This work presents an ultra-low-power classifier that can be integrated within energy-constrained bio-sensors to enable rapid analysis for continuous health monitoring. The in-sensor classifier saves significant transmission energy by extracting critical information locally to eliminate the need of transmitting raw data to centralized servers for remote signal processing. The convolutional-neural-network

  • Complex exponential functions: A high-precision hardware realization
    Integration (IF 1.15) Pub Date : 2020-03-06
    Adel Hosseiny; Ghassem Jaberipur

    Hardware realization of complex exponential functions (CEF) is not practical for over 16-bit operands. This is due to high cost and delay of the required look-up table (LUT) and arithmetic units. Therefore, we decompose larger (up to 64 bits) operands to three parts (e.g., 11+24+29=64). They are handled by minimax approximation, one-dimensional degree-3 interpolation, and pure LUT approaches, respectively

  • On VLSI Design of Rank-Order Filtering using DCRAM Architecture.
    Integration Pub Date : 2008-02-01
    Meng-Chun Lin,Lan-Rong Dung

    This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture

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