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IEEE Circuits and Systems Society IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2024-03-13
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Guest Editorial: Integrated Devices, Circuits, and Systems for the 6G Era IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2024-03-13 Xi Zhu, Roberto Gómez-García, Chun-Hsing Li, Bryan Schwitter
This Special Issue of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) is dedicated to demonstrating the latest research progress on integrated devices, circuits and systems for the 6G Era. As 5G rolls out worldwide, teams of visionary experts are developing roadmaps and revolutionary applications for the next-generation wireless network: 6G. Indeed, the 6G mobile networks
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TechRxiv: Share Your Preprint Research with the World! IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2024-03-13
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Incoming Editorial IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2024-03-13 Wen-Hsiao Peng
The IEEE Journal On Emerging and Selected Topics in Circuits and Systems (JETCAS) is a periodical sponsored by the IEEE Circuits and Systems Society (CASS). Since its advent about a decade ago, JETCAS has published quarterly special issues on emerging and selected topics that cover the entire field of interest of the CASS. Particular emphasis has been put on emerging areas that are expected to grow
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Enhancing Context Models for Point Cloud Geometry Compression with Context Feature Residuals and Multi-Loss IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2024-02-20 Chang Sun, Hui Yuan, Shuai Li, Xin Lu, Raouf Hamzaoui
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Metamaterial-Enabled Ultrawideband mmWave Antenna-in-Package Using Heterogeneously-Integrated Silicon IPD and HDI-PCB for B5G/ 6G Applications IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2024-01-24 Neda Khiabani, Ching-Wen Chiang, Nai-Chen Liu, Pai-Yen Chen, Yen-Cheng Kuan, Chung-Tse Michael Wu
This work presents the design, creation, and testing of ultrawideband millimeter-wave (mmWave) antennas with a tightly coupled array (TCA) configuration. These antennas are made using metamaterial (MTM) designs and advanced high-density interconnect (HDI) antenna-in-package (AiP) technologies, ideal for beyond-5G (B5G) and 6G networks. The main elements of the MTM antenna array are constructed with
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A 299–315-GHz Dual-Band Radiator Array With Cascaded Transmission Line-Based Feedback Network for Phase Noise Improvement IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2024-01-23 Meng Yang, Chi Zhang, Liang Wu, Quan Xue
This paper presents a THz radiator array integrating two elements, each of which consists of two fundamental oscillators operating at half of the output frequency, a push-push frequency doubler and an on- chip square-shaped loop antenna. To improve the phase noise for the fundamental oscillators, a feedback network containing a long cascaded transmission line featuring high frequency selectivity is
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Millimeter-Wave GaAs Ultra-Wideband Medium Power Amplifier and Broadband High-Power Power Amplifier for 5G/6G Applications IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2024-01-19 Zi-Hao Fu, Ming-Xuan Li, Tzyh-Ghuang Ma, Chan-Shin Wu, Kun-You Lin
This paper presents an ultra-wideband (UWB) medium power amplifier (MPA) and a broadband high-power power amplifier (HPA) operating at the 5G/6G frequency bands. By using $0.15~\mu \text{m}$ GaAs pseudomorphic high electron mobility transistor (pHEMT) technology process, the proposed UWB MPA delivers an average small-signal gain of 16.5 dB, a saturation output power ( $\text{P}_{\mathrm {sat}}$ ) of
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Broadband Millimeter-Wave GaAs Dual-Function Switching Attenuators With Low Insertion Loss and Large Attenuation Range IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2024-01-16 Yutong Wang, Bo Li, Feng Lin, Houjun Sun, Hongjiang Wu, Chunliang Xu, Yuan Fang, Zhiqiang Li
This paper presents millimeter-wave (mmW) wide-band dual-function switching attenuator chips based on gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT). The broadband attenuator chips integrate the function of absorption single-pole-single-throw (SPST) switch by using balanced architecture. By analyzing the effects of transistor size and parasitic couplings from bias lines
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A 185-to-240 GHz SiGe Power Amplifier Using Non-Zero Base-Impedances for Power Gain and Output Power Optimizations IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2024-01-16 Xin Zhang, Nengxu Zhu, Fanyi Meng
It is commonly practiced in millimeter-wave and terahertz cascode amplifiers to enhance the power gain by shorting the base-impedance in the common-base transistor. However, it is found that the merit of high output power is not achieved simultaneously under the zero base-impedance scenarios. This paper theoretically analyzes the optimum designs by varying the base-impedances for power gain and output
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Design of Broadband Doherty Power Amplifier Based on Single Loop Load Modulation Network IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2024-01-15 Ge Bai, Zhijiang Dai, Jingsong Wang, Cheng Bi, Weimin Shi, Jingzhou Pang, Mingyu Li
This paper proposes a Doherty power amplifier (DPA) architecture with potential for wideband and high efficiency, denoted as single-loop load matching network DPA (SL-LMN). The conventional single combination node network is replaced by an SL-LMN, which adds a new current combination node. This architecture can bring new circuit design freedom, which expands the operating bandwidth of the load modulation
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A 39 GHz Doherty-Like Power Amplifier With 22dBm Output Power and 21% Power-Added Efficiency at 6dB Power Back-Off IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2024-01-08 Lang Chen, Lisheng Chen, Depeng Sun, Yichuang Sun, Yulin Pan, Xi Zhu
The design of a Doherty-like power amplifier for millimetre-wave (mm-wave) applications is presented in this work. The designed power amplifier employs a novel symmetrical load-modulated balanced amplifier (S-LMBA) architecture. This design is advantageous in minimizing the undesired impedance interaction often encountered in the classic LMBA approach. Such interactions are typically due to the use
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Guest Editorial Dynamical Neuro-AI Learning Systems: Devices, Circuits, Architecture and Algorithms IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-12-28 Jason K. Eshraghian, Arindam Basu, Corey Lammie, Shih-Chii Liu, Priydarshini Panda
This Special Issue of IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) is dedicated to demonstrating the latest research progress on dynamical neuro-artificial intelligence (AI) learning systems that bridge the gap between devices, circuits, architectures, and algorithms. The growing demand for AI has spurred the development of systems that: 1) co-localize computation and
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Low-Loss and Compact Millimeter-Wave Silicon-Based Filters: Overview, New Developments in Silicon-on-Insulator Technology, and Future Trends IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-12-21 Robert Nericua, Ke Wang, He Zhu, Roberto Gómez-García, Xi Zhu
This paper presents an overview of Silicon-based millimeter-wave (mm-wave) passive devices for bandpass and bandstop filtering applications, while also reporting originally-conceived filter developments and future trends. First of all, the state-of-the-art on mm-wave low-loss bandpass filters (BPFs) is covered, and new BPF designs are shown. The engineered BPFs employ a center-tapped ring architecture
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A 340-GHz THz Amplifier-Frequency-Multiplier Chain With 360° Phase-Shifting Range and its Phase Characterization IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-12-21 Chun Wang, Pin-Chun Chiu, Chun-Lin Ko, Sheng-Hsiang Tseng, Chun-Hsing Li
A 340-GHz compact terahertz (THz) amplifier-frequency-multiplier chain (AMC) offering a full 360° phase shifting range for phased-array applications is proposed in this paper. The AMC comprises an 85 -GHz phase-shifter-embedded ( $\Delta \varphi $ -embedded) power amplifier (PA) and a high-output-power frequency quadrupler (FQ). The PA is equipped with multifunctional impedance matching networks (M-IMNs)
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A 11.3–16.6-GHz VCO With Constructive Switched Magnetic Coupling in 65-nm CMOS IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-12-18 Yuetong Lyu, Changwenquan Song, Pei Qin, Liang Wu
Conventional transformer-based magnetic tuning has demonstrated dual-band or even multi-band operation for voltage-controlled oscillators (VCOs). However, the destructive magnetic coupling employed introduces implicit loss to the transformer thus degrading its quality factor (Q), and achieves a continuous frequency coverage resulting in inferior performance. To address this issue, this paper proposes
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Compact Transverse-Resonance Low-Pass Filter With Wide Stop-Band Rejection Implemented in Gallium Arsenide Technology IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-12-07 Sudipta Chakraborty, Gayatri Neeharika Sreepada, Michael Heimlich, Anand K. Verma
This work reports three designs of transverse resonance (TR)-based high-performance compact 5-pole Butterworth low-pass filters (TR-LPFs) at the cut-off frequency ( $f_{c}$ ) 10.5 GHz in $0.15~\mu \text{m}$ Gallium Arsenide (GaAs) pHEMT technology, with a chip size of 0.82 mm $\times0.87$ mm. Two fabricated TR-LPFs have 20 dB, 30 dB, 40 dB, and 50 dB attenuation levels with rejection bandwidths of
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Building Time-Surfaces by Exploiting the Complex Volatility of an ECRAM Memristor IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-11-16 Marco Rasetto, Qingzhou Wan, Himanshu Akolkar, Feng Xiong, Bertram Shi, Ryad Benosman
Memristors have emerged as a promising technology for efficient neuromorphic architectures owing to their ability to act as programmable synapses, combining processing and memory into a single device. Although they are most commonly used for static encoding of synaptic weights, recent work has begun to investigate the use of their dynamical properties, such as Short Term Plasticity (STP), to integrate
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Low-Area and Low-Power VLSI Architectures for Long Short-Term Memory Networks IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-11-06 Mohammed A. Alhartomi, Mohd Tasleem Khan, Saeed Alzahrani, Ahmed Alzahmi, Rafi Ahamed Shaik, Jinti Hazarika, Ruwaybih Alsulami, Abdulaziz Alotaibi, Meshal Al-Harthi
Long short-term memory (LSTM) networks are extensively used in various sequential learning tasks, including speech recognition. Their significance in real-world applications has prompted the demand for cost-effective and power-efficient designs. This paper introduces LSTM architectures based on distributed arithmetic (DA), utilizing circulant and block-circulant matrix-vector multiplications (MVMs)
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To Spike or Not to Spike: A Digital Hardware Perspective on Deep Learning Acceleration IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-11-06 Fabrizio Ottati, Chang Gao, Qinyu Chen, Giovanni Brignone, Mario R. Casu, Jason K. Eshraghian, Luciano Lavagno
As deep learning models scale, they become increasingly competitive from domains spanning from computer vision to natural language processing; however, this happens at the expense of efficiency since they require increasingly more memory and computing power. The power efficiency of the biological brain outperforms any large-scale deep learning (DL) model; thus, neuromorphic computing tries to mimic
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BioNN: Bio-Mimetic Neural Networks on Hardware Using Nonlinear Multi-Timescale Mixed-Feedback Control for Neuromodulatory Bursting Rhythms IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-11-03 Kangni Liu, Shahin Hashemkhani, Jonathan Rubin, Rajkumar Kubendran
Biological neurons exhibit rich and complex nonlinear dynamics, which are computationally expensive and area/power hungry for hardware implementation. This paper presents a mathematical analysis and hardware realization of neural networks using a nonlinear neuron model that utilizes two excitable systems operating at different timescales. The neuron consists of a mixed-feedback system operating at
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Towards Scalable Digital Modeling of Networks of Biorealistic Silicon Neurons IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-11-02 Swagat Bhattacharyya, Praveen Raj Ayyappan, Jennifer O. Hasler
The study of biorealistic neuron circuits has been limited by the efficiency of digital implementations. Efficient digital approaches generally use I&F variants, losing important neural properties for network computation. In contrast, accurate neuron ODEs tend to utilize computationally intensive operations, causing the overhead to become prohibitive for large spiking neural network applications. This
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Design and Analysis of a V-Band CMOS Sextuple SILVCO Using Transformer and Cascade-Series Coupling With a Frequency-Tracking Loop IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-11-01 Wei-Cheng Chen, Hong-Yeh Chang
A low-phase-noise local oscillator (LO) is a crucial component in communication systems. However, the design challenge of the LO significantly increases as the operating frequency rises. This paper focuses on the design and analysis of a $V$ -band CMOS sextuple sub-harmonically injection-locked voltage-controlled oscillator (SILVCO) with a frequency-tracking loop (FTL). To further enhance the locking
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Programming Weights to Analog In-Memory Computing Cores by Direct Minimization of the Matrix-Vector Multiplication Error IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-11-01 Julian Büchel, Athanasios Vasilopoulos, Benedikt Kersting, Corey Lammie, Kevin Brew, Timothy Philip, Nicole Saulnier, Vijay Narayanan, Manuel Le Gallo, Abu Sebastian
Accurate programming of non-volatile memory (NVM) devices in analog in-memory computing (AIMC) cores is critical to achieve high matrix-vector multiplication (MVM) accuracy during deep learning inference workloads. In this paper, we propose a novel programming approach that directly minimizes the MVM error by performing stochastic gradient descent optimization with synthetic random input data. The
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Spike Timing Dependent Gradient for Direct Training of Fast and Efficient Binarized Spiking Neural Networks IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-10-31 Zhengyu Cai, Hamid Rahimian Kalatehbali, Ben Walters, Mostafa Rahimi Azghadi, Amirali Amirsoleimani, Roman Genov
Spiking neural networks (SNNs) are well-suited for neuromorphic hardware due to their biological plausibility and energy efficiency. These networks utilize sparse, asynchronous spikes for communication and can be binarized. However, the training of such networks presents several challenges due to their non-differentiable activation function and binarized inter-layer data movement. The well-established
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MiCE: An ANN-to-SNN Conversion Technique to Enable High Accuracy and Low Latency IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-10-31 Nguyen-Dong Ho, Ik-Joon Chang
Spiking Neural Networks (SNNs) mimic the behavior of biological neurons. Unlike traditional Artificial Neural Networks (ANNs) that operate in a continuous time domain and use activation functions to process information, SNNs operate discrete event-driven, where data is encoded and communicated through spikes or discrete events. This unique approach offers several advantages, such as efficient computation
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Operating Coupled VO₂-Based Oscillators for Solving Ising Models IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-10-31 Maria J. Avedillo, Manuel Jiménez Través, Corentin Delacour, Aida Todri-Sanial, Bernabé Linares-Barranco, Juan Núñez
Coupled nano-oscillators are attracting increasing interest because of their potential to perform computation efficiently, enabling new applications in computing and information processing. The potential of phase transition devices for such dynamical systems has recently been recognized. This paper investigates the implementation of coupled VO2-based oscillator networks to solve combinatorial optimization
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ESSM: Extended Synaptic Sampling Machine With Stochastic Echo State Neuro-Memristive Circuits IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-10-31 Vineeta V. Nair, Chithra Reghuvaran, Deepu John, Bhaskar Choubey, Alex James
Synaptic stochasticity is an important feature of biological neural networks that is not widely explored in analog memristor networks. Synaptic Sampling Machine (SSM) is one of the recent models of the neural network that explores the importance of the synaptic stochasticity. In this paper, we present a memristive Echo State Network (ESN) with Extended-SSM (ESSM). The circuit-level design of the single
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Benchmarking DNN Mapping Methods for the in-Memory Computing Accelerators IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-10-31 Yimin Wang, Xuanyao Fong
This paper presents a study of methods for mapping the convolutional workloads in deep neural networks (DNNs) onto the computing hardware in the in-memory computing (IMC) architecture. Specifically, we focus on categorizing and benchmarking the processing element (PE)-level mapping methods, which have not been investigated in detail for IMC-based architectures. First, we categorize the PE-level mapping
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GEBA: Gradient-Error-Based Approximation of Activation Functions IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-10-31 Changmin Ye, Doo Seok Jeong
Computing-in-memory (CIM) macros aiming at accelerating deep learning operations at low power need activation function (AF) units on the same die to reduce their host-dependency. Versatile CIM macros need to include reconfigurable AF units at high precision and high efficiency in hardware usage. To this end, we propose the gradient-error-based approximation (GEBA) of AFs, which approximates various
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Neuromorphic Computing With Address-Event-Representation Using Time-to-Event Margin Propagation IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-10-31 R. Madhuvanthi Srivatsav, Shantanu Chakrabartty, Chetan Singh Thakur
Address-Event-Representation (AER) is a spike-routing protocol that allows the scaling of neuromorphic and spiking neural network (SNN) architectures. However, in conventional neuromorphic architectures, the AER protocol and in general, any virtual interconnect plays only a passive role in computation, i.e., only for routing spikes and events. In this paper, we show how causal temporal primitives like
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Dynamic-HDC: A Two-Stage Dynamic Inference Framework for Brain-Inspired Hyperdimensional Computing IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-10-31 Yu-Chuan Chuang, Cheng-Yang Chang, An-Yeu Wu
Brain-inspired hyperdimensional computing (HDC) has attracted attention due to its energy efficiency and noise resilience in various IoT applications. However, striking the right balance between accuracy and efficiency in HDC remains a challenge. Specifically, HDC represents data as high-dimensional vectors known as hypervectors (HVs), where each component of HVs can be a high-precision integer or
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CBP-QSNN: Spiking Neural Networks Quantized Using Constrained Backpropagation IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-10-31 Donghyung Yoo, Doo Seok Jeong
Spiking Neural Networks (SNNs) support sparse event-based data processing at high power efficiency when implemented in event-based neuromorphic processors. However, the limited on- chip memory capacity of neuromorphic processors strictly delimits the depth and width of SNNs implemented. A direct solution is the use of quantized SNNs (QSNNs) in place of SNNs with FP32 weights. To this end, we propose
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Design Space Exploration of Sparsity-Aware Application-Specific Spiking Neural Network Accelerators IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-10-30 Ilkin Aliyev, Kama Svoboda, Tosiron Adegbija
Spiking Neural Networks (SNNs) offer a promising alternative to Artificial Neural Networks (ANNs) for deep learning applications, particularly in resource-constrained systems. This is largely due to their inherent sparsity, influenced by factors such as the input dataset, the length of the spike train, and the network topology. While a few prior works have demonstrated the advantages of incorporating
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HyDe: A Hybrid PCM/FeFET/SRAM Device-Search for Optimizing Area and Energy-Efficiencies in Analog IMC Platforms IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-10-26 Abhiroop Bhattacharjee, Abhishek Moitra, Priyadarshini Panda
Today, there are a plethora of In-Memory Computing (IMC) devices- SRAMs, PCMs & FeFETs, that emulate convolutions on crossbar-arrays with high throughput. Each IMC device offers its own pros & cons during inference of Deep Neural Networks (DNNs) on crossbars in terms of area overhead, programming energy and non-idealities. A design-space exploration is, therefore, imperative to derive a hybrid-device
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Multicore Spiking Neuromorphic Chip in 180-nm With ReRAM Synapses and Digital Neurons IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-10-16 Hao Jiang, Jikai Lu, Chenggao Zhang, Shuangzhu Tang, Junjie An, Lingli Cheng, Jian Lu, Jinsong Wei, Keji Zhou, Xumeng Zhang, Tuo Shi, Qi Liu
Neuromorphic computing based on spike neural networks (SNNs) exhibits great potential in reducing energy consumption in hardware systems. Resistive random-access memory (ReRAM) is regarded as a promising candidate to construct neuromorphic hardware, attributing to their high-density, nonvolatile, and compute-in-memory capability. However, the ReRAM-based neuromorphic chips are still in their infancy
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C-DNN V2: Complementary Deep-Neural-Network Processor With Full-Adder/OR-Based Reduction Tree and Reconfigurable Spatial Weight Reuse IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-10-04 Sangyeob Kim, Hoi-Jun Yoo
In this article, we propose a Complementary Deep-Neural-Network (C-DNN) processor V2 by optimizing the performance improvement from combination of CNN and SNN. C-DNN V1 showcased the potential for achieving higher energy efficiency by combining CNN and SNN. However, it encountered 5 challenges that hindered the full realization of this potential: Inefficiency of the clock gating accumulator, imbalance
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A Low Thermal Sensitivity Subthreshold-Current to Pulse-Frequency Converter for Neuromorphic Chips IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-10-02 Ben Varkey Benjamin, Richelle L. Smith, Kwabena A. Boahen
To convert a subthreshold current to a pulse frequency efficiently and predictably, we designed a silicon soma that conserves energy with current feedback and lessens thermal sensitivity with voltage feedback. When the input current charges a capacitor close to the inversion point of an inverter, its short-circuit current wastes energy. To shorten this period, existing designs accelerate the charging
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Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator With Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Applications IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-10-02 Jingwen Jiang, Keji Zhou, Jinhao Liang, Fengshi Tian, Chenyang Zhao, Jianguo Yang, Xiaoyong Xue, Xiaoyang Zeng
Spiking neural network (SNN)-based compute-in-memory (CIM) accelerator provides a prospective implementation for intelligent edge devices with higher energy efficiency compared with artificial neural networks (ANN) deployed on conventional Von Neumann architectures. However, the costly circuit implementation of biological neurons and the immature training algorithm of discrete-pulse networks hinder
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Corrections to “Digital implementation of Radial Basis Function Neural Networks Based on Stochastic Computing” [Mar 23 257-269] IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-09-13 Alejandro Morán Costoya, Luis Parrilla Roure, Miquel Roca, Joan Font-Rossello, Eugeni Isern, Vincent Canals
In the above article [1] , according to our institution, the text in project funding (bottom left on the first page) requires a minor modification. The following text:
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Guest Editorial Complex Cyber-Multitudinal-Physical Systems: Analysis, Decision-Making, and AI Applications IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-09-13 Xi Zhang, Jiajing Wu, Abraham O. Fapojuwo, Zbigniew Galias, Chi K. Tse
This Special Issue of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) is dedicated to disseminating the latest research results and practical applications on the analysis and decision-making of complex cyber-multitudinal-physical systems (CMPSs).
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Unlocking Efficiency in BNNs: Global by Local Thresholding for Analog-Based HW Accelerators IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-09-14 Mikail Yayla, Fabio Frustaci, Fanny Spagnolo, Jian-Jia Chen, Hussam Amrouch
For accelerating Binarized Neural Networks (BNNs), analog computing-based crossbar accelerators, utilizing XNOR gates and additional interface circuits, have been proposed. Such accelerators demand a large amount of analog-to-digital converters (ADCs) and registers, resulting in expensive designs. To increase the inference efficiency, the state of the art divides the interface circuit into an Analog
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Optimizations for a Current-Controlled Memristor- Based Neuromorphic Synapse Design IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-09-05 Hritom Das, Rocco D. Febbo, Charles P. Rizzo, Nishith N. Chakraborty, James S. Plank, Garrett S. Rose
The synapse is a key element of neuromorphic computing in terms of efficiency and accuracy. In this paper, an optimized current-controlled memristive synapse circuit is proposed. Our proposed synapse demonstrates reliability in the face of process variation and the inherent stochastic behavior of memristors. Up to an 82% energy optimization can be seen during the SET operation over prior work. In addition
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Intralayer Synchronization in Heterogeneous Multiplex Dynamical Networks Based on Spectral Graph Theory IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-07-19 Hui Liu, Shiman Zhang, Chai Wah Wu, Xiaoqun Wu, Zengyang Li, Jiangqiao Xu
This paper studies a heterogeneous multiplex network model that allows different dynamics in different layers. We explore intralayer synchronization of the multiplex network under distinct types of interlayer connections. From the perspective of spectral graph theory, we propose a set of edge weight requirements to synchronize the multiplex network. Focusing on the effect of interlayer connections
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Both Homophily and Heterophily Matter: Bi-Path Aware Graph Neural Network for Ethereum Account Classification IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-07-14 Han Yang, Junyuan Fang, Jiajing Wu, Zibin Zheng
In recent years, the cryptocurrency market has been booming with an ever-increasing market capitalization. However, due to the anonymity of blockchain technology, this market has become a hotbed of financial crimes. As the largest blockchain platform supporting smart contracts, financial crimes including scams and hacking frequently happen on Ethereum and have caused serious losses. Therefore, it is
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EFedDSA: An Efficient Differential Privacy-Based Horizontal Federated Learning Approach for Smart Grid Dynamic Security Assessment IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-07-13 Chao Ren, Tianjing Wang, Han Yu, Yan Xu, Zhao Yang Dong
Enhanced by machine learning (ML) techniques, data-driven dynamic security assessment (DSA) in smart cyber-physical grids has attracted significant research interest in recent years. However, the current centralized ML architectures have limited scalability, are vulnerable to privacy exposure, and are costly to manage. To resolve these limitations, we propose a novel effective and secure distributed
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Modal Analysis-Based Analytical Method for Frequency Estimation During Inertia Response Stage of Power Systems IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-07-03 Tiezhu Wang, Shicong Ma, Shanshan Wang, Weilin Hou, Juncheng Gao, Jianbo Guo, Xiaoxin Zhou
With the increasing adoption of renewable energy and HVDC transmission systems, the power system may experience large power fluctuations due to HVDC faults, potentially causing the rate of change of frequency (RoCoF) or frequency deviation limit to be exceeded during the inertia response phase. The system’s ability to withstand these disturbances primarily depends on the amount of system inertia, making
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Generation Method of Multi-Regional Photovoltaic Output Scenarios-Set Using Conditional Generative Adversarial Networks IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-06-30 Ziyuan Song, Yuehui Huang, Hongbin Xie, Xiaofei Li
The uncertainty of photovoltaic (PV) output power has an increasing impact on power balance with the increase of installed capacity. The construction of day-ahead PV output scenarios-set is an important basis for the stochastic optimal scheduling of the power system. For the uncertainty modeling of multi-regional day-ahead PV output, a scenarios-set generation method based on improved conditional generation
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Canonical Correlation Analysis and Visualization for Big Data in Smart Grid IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-06-28 Zigui Jiang, Qihao Yuan, Rongheng Lin, Fangchun Yang
Electricity consumption behaviors are influenced by various external and internal factors such as climate, location, building type, consumer characteristics and even other energy consumption. In order to investigate the electricity consumption behaviors of diverse consumers, we propose a methodology based on canonical correlation analysis to explore the correlation among electricity consumption, gas
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Optimization of Substation Siting and Connection Topology in Offshore Wind Farm Based on Modified Firefly Algorithm IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-06-28 Zhicong Huang, Canjun Yuan, Hanchen Ge, Ting Hou
To guide the construction of large-scale offshore wind farms, optimization for substation siting and connection topology are both necessary, which is a multiobjective optimization problem. Non-iterative methods are based on greedy strategies and they are only suitable to optimize the connection topology. Iterative methods can update the solutions iteratively to approach the optimum using common optimizers
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DND: Deep Learning-Based Directed Network Disintegrator IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-06-28 Wanchang Zhang, Zhongyuan Jiang, Qingsong Yao
Network disintegration is a fundamental problem in network science, the core of which is how to determine the smallest set of nodes whose removal can weaken the function of the network and quickly paralyze it. It is computationally NP-hard and usually cannot be solved in polynomial time complexity. Many network disintegration methods have been proposed, but they mainly focus on undirected networks
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Virtual Coupling-Based H∞ Active Fault-Tolerant Cooperative Control for Multiple High-Speed Trains With Unknown Parameters and Actuator Faults IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-06-23 Xue Lin, Weiqi Bai, Qianling Wang, Shajia Yu
This paper investigates the cooperative control problem of multiple high-speed trains subject to unknown parameters and actuator faults. The cooperative operation of multiple high-speed trains is modeled as a coupled control system. On the basis of the virtual coupling technique, the $\mathscr {H}_{\infty} $ active fault-tolerant cooperative control scheme is established to guarantee the desired tracking
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Guest Editorial Circuits and Systems for Industry X.0 Applications IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-06-13 Chi-Tsun Cheng, Jörg Wollert, Xi Chen, Abraham O. Fapojuwo
This Special Issue of IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS) is dedicated to showcasing the latest developments and achievements in circuits and systems for Industry X.0 applications.
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Multi-Objective Optimization for DC Microgrid Using Combination of NSGA-II Algorithm and Linear Search Method IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-06-08 Zijun Ren, Xiaohui Qu, Minzhi Wang, Changyue Zou
With the penetration of renewable sources, the DC microgrid is much more efficient and flexible to link renewable power generators and DC loads. Due to the uncertainties in both sources and loads, it is hard to maintain the economic and optimal operation simultaneously in DC microgrids. To solve it, this paper builds a multi-objective optimization model including the operation cost, power loss, and
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Large Scale EV Charging Allocation in Unbalanced Multi-Microgrid System IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-06-07 Yongxiang Xia, Xuan Gu, Dingtao Fu, Xi Chen
The improvement of charging infrastructure has greatly relieved the range anxiety of electric vehicles (EV) drivers, leading to the rapid increase in EV ownership. Due to the uncertainty of EV charging behavior, a large number of EVs connected to microgrids (MGs) without coordination will aggravate the unbalanced load distribution in the multi-microgrid system. Contrariwise, EVs with appropriate coordination
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Investigating Packet Transmission From the Perspective of Complex Networks Composed of Chaotic Circuits IEEE J. Emerg. Sel. Top. Circuits Syst. (IF 4.6) Pub Date : 2023-06-07 Souhei Shima, Tsuyoshi Isozaki, Yoko Uwate, Yoshifumi Nishio
Complex networks have been studied in various fields. In particular, topology and routing algorithms have been studied with the aim of preventing packet dropping and congestion in communication networks. When chaotic circuits are connected together to form complex networks, it is found that the synchronization rates around the high-degree nodes (hubs) are higher than those around low-degree nodes.