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Pinning Impulsive Synchronization of Complex Networks with Multiple Sizes of Delays via Adaptive Impulsive Intervals Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-03-02 Dong Ding; Ze Tang; Yan Wang; Zhicheng Ji
The leader-following issue for a class of nonlinearly coupled complex networks with multiple time-varying delays was investigated in this study. A distributed controller was introduced for realizing the exponential synchronization of the complex network with different delay scales that are known in advance. The Lyapunov stability theorem and mathematical induction method were used to obtain delay-dependent
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Event-Based Transformation of Misarticulated Stops in Cleft Lip and Palate Speech Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-20 Protima Nomo Sudro, C. M. Vikram, S. R. Mahadeva Prasanna
The cleft of the lip and palate (CLP) is a congenital disability affecting the craniofacial region and it impacts the speech production system. The current work focuses on the modification of misarticulations produced for unvoiced stop consonants in CLP speech. Three types of misarticulations are studied: glottal, palatal, and velar stop substitutions. The stop consonants are misarticulated due to
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A Statistical Color Image Watermarking Scheme Using Local QPCET and Cauchy–Rayleigh Distribution Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-19 Panpan Niu, Li Wang, Jialin Tian, Siyu Zhang, Xiangyang Wang
Based on local quaternion polar complex exponential transform (QPCET) and Cauchy–Rayleigh distribution, we propose a statistical color image watermarking scheme in this paper, which can achieve the trade-off among imperceptibility, robustness and data payload. Our color image watermarking scheme consists of two parts, namely embedding and detecting. In the embedding process, we divide the color host
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Blind Reconstruction of Binary Linear Block Codes Based on Association Rules Mining Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-19 Li Dai, Chunhui Ren, Jinhong Guo
In cognitive radio context, the coding parameters are unknown at the receiver. The design of an intelligent receiver is essentially to identify these parameters from the received data blindly. In this paper, we are interested in the blind identification of binary linear block codes from received noisy data. In order to recognize the code length, the concept of the normalized column weight vector is
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MOSTL: An Accurate Multi-Oriented Scene Text Localization Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-19 Fatemeh Naiemi, Vahid Ghods, Hassan Khalesi
Automatic text localization in natural environments is the main element of many applications including self-driving cars, identifying vehicles, and providing scene information to visually impaired people. However, text in the natural and irregular scene has different degrees in orientations, shapes, and colors that make it difficult to detect. In this paper, an accurate multi-oriented scene text localization
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Blind Separation of Instantaneous Mixtures of Independent/Dependent Sources Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-19 Amal Ourdou, Abdelghani Ghazdali, Amine Laghrib, Abdelmoutalib Metrane
Blind Source Separation (BSS) has always been an active research field within the signal processing community; it is used to reconstruct primary source signals from their observed mixtures. Independent Component Analysis has been and is still used to solve the BSS problem; however, it is based on the mutual independence of the original source signals. In this paper, we propose to use Copulas to model
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A Novel Contrast Enhancement Technique using Gradient-Based Joint Histogram Equalization Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-18 D. Vijayalakshmi, Malaya Kumar Nath
Image enhancement by histogram equalization reduces the number of gray levels that lead to information loss and unnatural appearance. This paper aims to improve the contrast and preserve information and edge details by employing gradient-based joint histogram equalization. It is achieved by a multiscale-based dark pass filter, which gives the pixel’s edge information. A joint histogram is computed
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Structured Network Pruning via Adversarial Multi-indicator Architecture Selection Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-17 Yuxuan Wei, Ying Chen
Network pruning offers an opportunity to facilitate deploying convolutional neural networks (CNNs) on resource-limited embedded devices. Pruning more redundant network structures while ensuring network accuracy is challenging. Most existing CNN compression methods iteratively prune the “least important” filters and retrain the pruned network layer-by-layer, which may lead to a sub-optimal solution
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CNFET-Based Ultra-Low-Power Dual- $$V_{DD}$$ V DD Ternary Half Adder Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-16 Abhay S. Vidhyadharan, Kasthuri Bha, Sanjay Vidhyadharan
This paper proposes a carbon nanotube FET (CNFET)-based ultra-low-power dual-\(V_{DD}\) ternary half adder (HA) circuit. The proposed design utilizes both the available ternary power supply voltages (\(V_{DD}\) & \(V_{DD}/2\)) and prevents direct path between the power supplies and ground, thus significantly reducing the power dissipation as compared to the conventional designs. The performance of
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A Multiple Sources Localization Method Based on TDOA Without Association Ambiguity for Near and Far Mixed Field Sources Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-16 Haitao Liu, Yonghua Chen, Yanming Lin, Qian Xiao
A new method for multiple sources localization is proposed to eliminate association ambiguity for near and far mixed field sources. A spatial source localization model in the modified polar representation was constructed without the prior knowledge needed if the source is near-field or far-field. The localization model for multiple sources was deduced by using all the possible permutation of the TDOA
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Orthogonal Least Absolute Value for Sparse Spike Deconvolution Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-16 A. Had, K. Sabri
Several phenomena encountered in nature are characterized by very localized events occurring randomly at given times. Random pulses are an appropriate modelling tool for such events. Usually, the impulses are hidden in the noise due to unwanted convolution. In some cases, the problem is more complex because of the short time lag between the pulses. Considering these problems, the resulting signal is
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High-Performance Carry Select Adders Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-16 R. Jothin, P. Sreelatha, A. Ahilan, M. Peer Mohamed
This research article proposes high-performance square-root carry select adder (SQRT CSLA) architectures with high speed, area and energy efficiency when compared to the existing SQRT CSLA architectures. The first proposed method uses an optimized design of binary to excess-1 converter (BEC)-based SQRT CSLA by incorporating a carry enable binary to excess-1 converter (CEBEC) design that exploits a
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Jitter Modeling in Digital CDR with Quantization Noise Analysis Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-16 Sanaz Salem, Mohsen Saneei, Dariush Abbasi-Moghadam
Phase rotator-based digital clock and data recovery (CDR) using multi-level bang-bang phase detector (ML-BBPD) and time to digital converter (TDC) is analyzed at system and circuit level. A model is proposed for calculating the quantization noise and bit error rate (BER), in order to evaluate the important parameters in CDR design. The jitter analysis is done based on the probability density function
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Deterministic Digital Calibration Technique for 1.5 bits/stage Pipelined and Algorithmic ADCs with Finite op-amp Gain and Large Capacitance Mismatches Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-13 Chinmaye Ramamurthy, Chetan D. Parikh, Subhajit Sen
This paper proposes a high-speed deterministic digital technique to calibrate the errors due to capacitance mismatch and finite op-amp gain. Unlike other calibration techniques, this technique requires neither forcing the inputs of the intermediate stages being calibrated to exact voltages, nor reducing the gains of each stage to avoid saturation of output digital codes. A 1.5 bits/stage, 10 stages
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Performance Analysis in Higher-Order IIR Filter Structures with Application to EEG Signal Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-13 Mahesh Y. Ladekar, Yashwant V. Joshi, Ramchandra R. Manthalkar
This paper investigates the analysis of critical path delay in various infinite impulse response (IIR) digital filter structure implementations. The critical path delay increases with the order of filter increasing in all conventional structures. So, it is needed to reduce the critical path delay for the faster realization of a digital filter in real-time processing. This paper proposed the rules for
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A Hybrid Deep Ensemble for Speech Disfluency Classification Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-11 Sheena Christabel Pravin, M. Palanivelan
In this paper, a novel Hybrid Deep Ensemble (HDE) is proposed for automatic speech disfluency classification on a sparse speech dataset. Categorizations of speech disfluencies for diagnosis of speech disorders have so long relied on sophisticated deep learning models. Such a task can be accomplished by a straightforward approach with high accuracy by the proposed model which is an optimal combination
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Sparse Estimation Technique for Digital Pre-distortion of Impedance-Mismatched Power Amplifiers Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-09 Cyro S. Hemsi, Cristiano M. Panazio
This paper proposes the application of the Wiener–Hammerstein with feedback (WHFB) model as a digital pre-distortion (DPD) behavioural model for power amplifiers (PA) under load impedance mismatch, since more traditional models suffer performance degradation in this condition. Moreover, this paper proposes the use of the least absolute shrinkage and selection operator (LASSO) approach for the sparse
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Stability of Digital Filters with State-Delay and External Interference Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-08 C. G. Parthipan, Priyanka Kokil
This work addresses stability of interfered digital filters with state-delay and saturation arithmetic. By utilizing a quadratic Lyapunov functional and properties of saturation overflow, a new condition is established to ensure stability of interfered digital filters under the influence of saturation arithmetic and state-delay. The criterion is capable of finding minimum \(H_\infty \) norm in the
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Augmented Joint Domain Localized Method for Polarimetric Space–Time Adaptive Processing Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-08 Kang Zhao, Zhiwen Liu, Shuli Shi, Yulin Huang, Yougen Xu
An augmented joint domain localized technique for computationally efficient polarimetric space–time adaptive processing (pSTAP) is proposed. In the proposed method, the signal vector to be detected is first estimated by using a modified least square method, and then the clutter plus noise covariance matrix (CNCM) required by pSTAP is estimated by using a newly developed dimension-reduced (DR) scheme
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Investigation of a Heterogeneous RLC Lattice with Triangular Topology, Excited by a Lumped Voltage Source Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-07 Noemen Ammar, Gabzili Hanen
Heterogeneous triangular network composed of resistors, capacitors and inductors gives a genuine electrical model for analyzing many engineering and physical problems. Here, we discuss various designs of RLC electrical circuits possessing a triangular topology. The theoretical formulation uses the WCIP technique. The proposed method rests on the definition of the incident and reflected waves from the
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Distributed $${H_\infty }$$ H ∞ State Estimation in Sensor Network Subject to State and Communication Delays Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-02-03 Wei Qian, Xianglin Zhang, Yunji Zhao, Xinliang Zhang
The distributed \(H_\infty \) state estimation of delayed sensor network is dealt with in this paper. To deeply reflect the time-delay phenomenon in the process of information fusion, a model containing state time-varying delay and different communication delays is set up. Afterwards, a fresh Lyapunov–Krasovskii functional (LKF) is given, which contains different kinds of time delays, delay-dependent
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A New Low Power Schema for Stream Processors Front-End with Power-Aware DA-Based FIR Filters by Investigation of Image Transitions Sparsity Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-28 Seyedeh Fatemeh Ghamkhari, Mohammad Bagher Ghaznavi-Ghoushchi
Data stream processors and accelerators, due to the outstanding energy performance, run on hardware more than any time in modern designs. The general model for these processors comprises massive shift register arrays with the largest share in energy dissipation and processing elements (PE). In this paper, a new gated flip-flop is designed and utilized in shift register arrays, to decrease power consumption
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DNN-Based Calibrated-Filter Models for Speech Enhancement Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-27 Yazid Attabi, Benoit Champagne, Wei-Ping Zhu
In this paper, we present a new two-stage speech enhancement approach, specially conceived to reduce musical and other random noises without requiring their localization in the time–frequency domain. The proposed method is motivated by two observations: (1) the random scattering nature of the energy peaks corresponding to the musical noise in the spectrogram of the processed speech; and (2) the existence
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Mel Scale-Based Linear Prediction Approach to Reduce the Prediction Filter Order in CELP Paradigm Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-25 M. S. Arun Sankar, P. S. Sathidevi
This paper proposes a novel method to reduce the order of prediction filter from 10 to 7 in Code Excited Linear Prediction (CELP) coding framework by the inclusion of psychoacoustic Mel scale into Linear Predictive Coding (Mel-LPC). Efficient quantization methods using 2-split Vector Quantization (VQ) for Mel-LPC obtained a reduction of 4 bits/frame and resulted in a total bit gain of 200 bps. A weighting
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A Low Area FPGA Implementation of Reversible Gate Encryption with Heterogeneous Key Generation Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-22 K. Saranya, K. N. Vijeyakumar
The reversible computation is the process of designing the architecture with reversible logic gates (RLG) and applicable for optical computing, digital signal processing, nanotechnologies and low-power circuits. In this study, integer wavelet transform (IWT) compression technique is applied to the input image to compress the pixel value. The utilization of the IWT is used to improve the quality of
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Generalized Variable Step-Size Diffusion Continuous Mixed p -Norm Algorithm Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-21 Long Shi, Haiquan Zhao
The generalized variable step-size diffusion continuous mixed p-norm (GVSS-DCMPN) algorithm is proposed in this paper, which is derived based on the improved continuous mixed p-norm (CMPN) strategy. In detail, a linear function is designed for the CMPN strategy. The proposed GVSS-DCMPN algorithm capable of exploiting various error norms to obtain performance improvement in non-Gaussian noise environment
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A Power-Efficient SAR ADC with Optimized Timing-Redistribution Asynchronous SAR Logic in 40-nm CMOS Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-21 Mengying Hu, Jing Jin, Yuekang Guo, Xiaoming Liu, Jianjun Zhou
This paper presents a power-efficient successive-approximation register (SAR) analog-to-digital converter (ADC) with fast response reference buffer (RV-buffer). Several techniques are applied in the system design to improve the performance of the SAR ADC. A novel timing-redistribution SAR logic is proposed to balance the difference between required settling time for the most significant bit and the
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Adapted Jacobi Orthogonal Invariant Moments for Image Representation and Recognition Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-19 Amal Hjouji, Rachid Chakid, Jaouad El-Mekkaoui, Hassan Qjidaa
Images recognition and classification require an extraction technique of feature vectors of these images. These vectors must be invariant to the three geometric transformations: rotation, translation and scaling. Several authors used the theory of orthogonal moments to extract the feature vectors of images. Jacobi moments are orthogonal moments, which have been widely applied in imaging and pattern
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Fast Computation of 3D Discrete Invariant Moments Based on 3D Cuboid for 3D Image Classification Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-16 Hicham Karmouni, Mohamed Yamni, Omar El Ogri, Achraf Daoui, Mhamed Sayyouri, Hassan Qjidaa, Ahmed Tahiri, Mustapha Maaroufi, Badreeddine Alami
The use of 3D discrete orthogonal invariant moments as descriptors of images constitutes one of the hot topics in the field of 3D image analysis, especially in the recognition and classification of deformed objects, due to their high numerical precision and low computing complexity. The TSR (translation, scale and rotation) invariant functions of discrete orthogonal moments can be obtained by expressing
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Asynchronous $$H_{\infty }$$ H ∞ Control of Uncertain Switched Singular Systems with Time-Varying Delays Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-15 Jing Wang, Xingtao Wang
This paper is concerned with the problem of \(H_{\infty }\) control for a class of uncertain switched singular systems with time-varying state delays under asynchronous switching. The asynchronous phenomenon is caused by the choice of controller lagging behind the corresponding subsystem in practice. First, sufficient conditions by finding a novel piecewise Lyapunov–Krasovskii function combining with
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Stochastic Resonance Effect in Optimal Decision Solution Under Neyman–Pearson Criterion Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-13 Ting Yang, Yu Li, Shiju Yang, Shujun Liu
In this paper, stochastic resonance effect on the optimal detection under Neyman–Pearson (NP) criterion is investigated for a general nonlinear system. To this end, a noise enhanced detection optimization problem for maximizing the probability of detection under a constant constraint on the probability of false-alarm is formulated, where an additive noise is added to the nonlinear system input and
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Transformation of 2D Roesser into Causal Recursive Separable Denominator Model and Decomposition into 1D Systems Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-13 Muhammad Imran, Abdul Ghafoor, Muhammad Imran
A transformation for the 2D system is proposed to transform the original 2D systems into causal recursive separable denominator systems. 2D causal recursive separable denominator systems with minimal rank-decomposition can be written into two 1D systems for ease in the analysis and model order reduction.
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Improved Hybrid Block-Based Motion Estimation for Inter-frame Coding Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-11 Yusra Ahmed Salih, Loay Edwar George
Digital video technology has been increasingly needed in various fields, such as telecommunications, entertainment, medicine. Therefore, video compression is required. Motion estimation methods help in improving video compression efficiency by effectively removing the temporal redundancy between successive frames. Several block-based motion estimation (BME) algorithms are being suggested to reduce
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Event-Triggered Finite-Time $$H_{\infty }$$ H ∞ Filtering for a Class of Switched Nonlinear Systems Via the T–S Fuzzy Model Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-11 Hui Gao, Kaibo Shi, Hongbin Zhang
The paper focuses on the finite-time \(H_{\infty }\) filtering (FTHF) design problem for a class of switched nonlinear systems (SNSs) via the T–S fuzzy model method. Different from the traditional FTHF design methods with time-triggered mechanism, a novel event-triggered scheme is proposed for SNSs, which takes full advantage of mixed switching signals. The information of system output and switching
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Realization of a Fourth-Order Linear Time-Varying Differential System with Nonzero Initial Conditions by Cascaded two Second-Order Commutative Pairs Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-11 Salisu Ibrahim, Mehmet Emir Koksal
Decomposition is an important tool that is used in many differential systems for solving real engineering problems and improving the stability of a system. It involves breaking down of high-order linear systems into lower-order commutative pairs. Commutativity plays an essential role in mathematics, and its applications are extended in physical science and engineering. This paper explicitly expresses
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A Novel Closed-Form Estimator for AOA Target Localization Without Prior Knowledge of Noise Variances Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-11 Feifei Pang, Xiangxi Wen
This paper addresses the problem of target localization using angle-of-arrival (AOA) measurements when the prior information of the AOA measurement noise variance is unavailable. At first, a maximum likelihood estimator (MLE) and the Cramér–Rao lower bound are derived for the case where the unknown noise variance is a function of the target-to-sensor distance. Then, a novel estimator is proposed to
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Single-Ended 10T SRAM Cell with High Yield and Low Standby Power Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-11 Erfan Shakouri, Behzad Ebrahimi, Nima Eslami, Mohammad Chahardori
This paper introduces a 10T single-ended SRAM cell with high stability and low static power. The read static noise margin is augmented by using a Schmitt-trigger inverter and decoupling the storage node from the read bitline by adding one transistor. Since writing “1” is difficult in single-ended SRAM cells, using proper capacitive coupling and also extra pMOS transistor as an access transistor mitigates
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Variance Normalised Features for Language and Dialect Discrimination Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-11 Xiaoxiao Miao, Ian McLoughlin, Yan Song
This paper proposes novel features for automated language and dialect identification that aim to improve discriminative power by ensuring that each element of the feature vector has a normalised contribution to inter-class variance. The method firstly computes inter- and intra-class frequency variance statistics and then distributes the overall spectral variance across spectral regions which are sized
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Classic Scaling Fractal Fractance Approximation Circuits: Optimization Principle Analysis and Method Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-07 Yue-Rong Zhang, Qiu-Yan He, Xiao Yuan
This paper presents the optimization principle and law of classic scaling fractal fractance approximation circuits (FACs). The scaling extension of FACs with negative half-order operational performance can facilitate the design of scaling fractal FACs with arbitrary-order fractional operators. This report summarizes the operational performance and mathematics describing of typical scaling fractal FACs
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Matrix Completion Using Graph Total Variation Based on Directed Laplacian Matrix Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-07 Alireza Ahmadi, Sina Majidian, Mohammad Hossein Kahaei
We propose two graph matrix completion algorithms called GMCM-DL and GMCR-DL, by employing a new definition of Graph Total Variation for matrices based on the directed Laplacian Matrix. We show that these algorithms outperform their peers in terms of RMSEs for both cases of uniform and row observations.
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Energy-Efficient and PVT-Tolerant CNFET-Based Ternary Full Adder Cell Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-06 Sepehr Tabrizchi, Fazel Sharifi, Parisa Dehghani
Full adder cell is an important module in arithmetic and processing systems whose performance has a great impact on performance of the whole system. By continuous scaling of the MOS transistors, some challenges and problems appear such as high leakage dissipation for which emerging technologies have been studied as a solution. Carbon nanotube field effect transistor (CNFET) is one of the most potential
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A New Circuit-Level Technique for Leakage and Short-Circuit Power Reduction of Static Logic Gates in 22-nm CMOS Technology Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-05 Mohammad Moradinezhad Maryan, Majid Amini-Valashani, Seyed Javad Azhari
The leakage power, a.k.a. static power, increases in deep-submicron technologies due to short-channel effects. This article proposes a novel input-controlled leakage restrainer transistor (ICLRT)-based technique to reduce leakage power as well as the short-circuit power. The main idea is to place a PMOS and an NMOS ICLRT on top of the pull-up network (PUN) and at the bottom of the pull-down network
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Blind Source Separation Based on Adaptive Artificial Bee Colony Optimization and Kurtosis Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-05 Rongjie Wang
A novel technique is proposed for selecting iterative updates and step sizes based on adaptive function values to compensate for the slow convergence rate of artificial bee colony optimization (ABCO). On this basis, a blind source separation (BSS) algorithm is proposed based on adaptive ABCO and kurtosis, which does not impose any hypothetical requirements on the source signal. By using kurtosis as
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Coefficient-Gradient-Based Individualized Stepsize Adaptation Mechanism for Robust System Identification Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-05 Haider A. Mohamed-Kazim, Ikhlas Abdel-Qader
To efficiently reduce the impact of the trading-off between the convergence rate and the quality of identifying a system, and also to improve the robustness of the algorithm against unknown sparsity levels, a Modified Absolute Weighted Input using Log function (MAWILOG) for NLMS algorithm is proposed. The essence of the proposed algorithm is to assign, individually, each coefficient of the adaptive
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Relaxed Stabilization Conditions for Interconnected Nonlinear Systems Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-05 Souhail Tiko, Fouad Mesquine, Ahmed El Hajjaji
This paper deals with the conservatism reduction of stability and stabilization conditions for nonlinear continuous-time interconnected systems. Based on Takagi–Sugeno modeling, the interconnected system is described by a convex combination of interconnected linear systems. Line integral fuzzy Lyapunov functions are considered to develop stability and stabilizability criteria for the considered class
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A Behavioral SPICE Model of a Binarized Memristor for Digital Logic Implementation Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-05 Xiaoyuan Wang, Chenxi Jin, Jason K. Eshraghian, Herbert Ho-Ching Iu, Congying Ha
In this paper, a behavioral SPICE memristor model for digital logic implementation is presented and demonstrated in LTSpice. We show binarized state switching and voltage thresholding in the model, which are both important features in practical digital systems. The use of this SPICE model is straightforward and intuitive because almost all parameters in the model can be changed according to the application
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Joint 2D-DOD and 2D-DOA Estimation for Coprime EMVS–MIMO Radar Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-05 Xianpeng Wang, Mengxing Huang, Liangtian Wan
The issue of two-dimensional (2D) direction-of-departure and direction-of-arrival estimation for bistatic multiple-input multiple-output (MIMO) radar with a coprime electromagnetic vector sensor (EMVS) is addressed in this paper, and a tensor-based subspace algorithm is proposed. Firstly, the covariance measurement of the received data is arranged into a fourth-order tensor, which can maintain the
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Closed-Form Analytical Formulation for Riemann–Liouville-Based Fractional-Order Digital Differentiator Using Fractional Sample Delay Interpolation Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-03 Anmol Gupta, Sanjay Kumar
This paper intends to apply a new mathematical approach based on Riemann–Liouville fractional–differential operator to the design of fractional-order digital differentiators (FODDs). Under the research area of fractional-order calculus, Grünwald–Letnikov (GL) and Riemann–Liouville (RL) are most widely used fractional–differential operators. The GL-based methods have been extensively investigated by
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Design of a Two-Channel Quadrature Mirror Filter Bank Through a Diversity-Driven Multi-Parent Evolutionary Algorithm Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-03 Sumika Chauhan, Manmohan Singh, Ashwani Kumar Aggarwal
A multi-objective problem-solving technique for designing a two-channel quadrature mirror filter bank is proposed, where the objectives are to minimize the errors of the passband, stopband and transition band. An evolution-based algorithm, “diversity-driven multi-parent evolutionary algorithm with adaptive non-uniform mutation” (DDMPEA), is proposed for this purpose. The proposed algorithm employs
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Flat-High-Gain Design and Noise Optimization in SiGe Low-Noise Amplifier for S–K Band Applications Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-03 Zhenrong Li, Boyu Liu, Yiming Duan, Zeyuan Wang, Zhen Li, Yiqi Zhuang
This paper presents an ultra-wideband (UWB) low-noise amplifier (LNA) with extremely flat-high-gain and low-noise figure (NF). In traditional resistive feedback topology, input matching, gain, and NF cannot be balanced. For better performance trade-offs in UWB design, a novel emitter-follower resistive feedback (EFRFB) is introduced, which utilizes a common-collector amplifier followed by a feedback
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Robust Time-Varying Parameter Proportionate Affine-Projection-Like Algorithm for Sparse System Identification Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-03 Pucha Song, Haiquan Zhao, Xiangping Zeng, Wei Quan, Liping Zhao
Due to its low computational burden, the affine-projection-like (APL) adaptive filtering algorithm has been extensively studied for colored signal input. Recently, a robust APL algorithm was designed by adopting the M-estimate cost function in impulsive noise environment; however, its convergence rate is very slow for sparse system identification. This paper proposed a proportionate APL M-estimate
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Image Super-Resolution Based on the Down-Sampling Iterative Module and Deep CNN Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-03 Xin Yang, Yifan Zhang, Tao Li, Yingqing Guo, Dake Zhou
Most deep learning-based image SR algorithms do not apply the down-sampling to the reconstructed process. Given this fact and inspired by the iteration idea, we propose a novel image SR method based on the down-sampling iterative module and deep CNN, which explores a new basic iterative module combining up- and down-sampling processes. Each iteration of the iterative module generates the intermediate
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Singular Spectrum Analysis-Based Hierarchical Multiresolution Analysis with Exploitation of Frequency Selectivities of Desirable Grouped Functions Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-03 Peihua Feng, Bingo Wing-Kuen Ling
This paper proposes a singular spectrum analysis (SSA)-based hierarchical multiresolution analysis (HMA) with the exploitation of the frequency selectivities of the desirable grouped functions. To perform the HMA, the SSA components are grouped based on the desirable grouped functions. Similar procedures are applied to the sum of the SSA components in a group in the previous level of decomposition
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$$ H_{\infty } $$ H ∞ Filtering for Discrete-Time Singular Markovian Jump Systems with Generally Uncertain Transition Rates Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-03 Anyou Shen, Lin Li, Chunyu Li
This paper is devoted to the problem of \( H_{\infty } \) filtering for a class of discrete-time singular Markovian jump systems with generally uncertain transition rates. Each transition rate of the jumping process is completely unknown or only the estimated value is known. The objective is to design a \( H_{\infty } \) filter such that the resulting filtering error system is stochastically admissible
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Mixing Matrix Estimation Algorithm for Time-Varying Radar Signals in a Dynamic System Under UBSS Model Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-03 Xiaowei Bai, Weihong Fu, Chunhua Zhou, Yongyuan Liu
This paper presents a novel mixing matrix estimation method based on a frame cluster analysis for application to the dynamic system of radar signals under an underdetermined blind source separation. The received signals are first processed using an adaptive denoising method. They are then divided into different appropriate length frames. Next, the frame type is determined and each frame is processed
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Linear System of Order Reduction Using a Modified Balanced Truncation Method Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-03 Santosh Kumar Suman, Awadhesh Kumar
Most of the physical structures may be described in terms of mathematical models. The mathematical methods of system modelling also lead to a thorough explanation of the mechanism in the form of mathematical equations, which are often difficult to use for both analysis and controller synthesis. Consequently, it is useful and very important to determine the likelihood of different calculations of the
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A New Low-Power Charge Pump with a Glitch-Free PFD for Speedup the Acquisition Process of a PLL in 65 nm CMOS Technology Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-03 Hossein Ghasemian, Amin Bahrami, Ebrahim Abiri, Mohammad Reza Salehi
In this paper, a new low-power charge pump (CP) is presented, which includes a switched-capacitor CP (SC-CP) as the main CP and an auxiliary current-steering CP (ACS-CP) to accelerate the lock process. By using a pulse width controller unit, the ACS-CP activates in predefined phase differences and turns off near the lock region. By utilizing the proposed CP, the issue of traditional current-mismatch
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FM Demodulation Using Dynamic Control Action of a Band Pass Filter Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-03 A. Mukherjee, B. N. Biswas
This paper audits FM demodulation using discriminator circuits, and the FM–AM conversion using a conventional single-tuned, double-tuned and staggered-tuned circuit is discussed. The demodulation capabilities of the double- and staggered-tuned circuits are audited in the time domain. It is observed that the conventional single- and double-tuned circuit outputs are highly distorted, in particular, the
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Quadrature Sinusoidal Oscillators Using CDBAs: New Realizations Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-03 Ram Bhagat, D. R. Bhaskar, Pragati Kumar
Four new circuits of fully uncoupled quadrature sinusoidal oscillators, using two current differencing buffered amplifiers (CDBAs), four/five resistors and two capacitors have been presented. In contrast to all previously published CDBA-based, fully decoupled, quadrature sinusoidal oscillators in which one of the input terminals is left unutilized, the presented circuits are realized by utilizing the
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Effect of Sparse Representation of Time Series Data on Learning Rate of Time-Delay Neural Networks Circuits Syst. Signal Process. (IF 1.681) Pub Date : 2021-01-03 Masoumeh Kalantari Khandani, Wasfy B. Mikhael
In this paper, we examine how sparsifying input to a time-delay neural network (TDNN) can significantly improve the learning time and accuracy of the TDNN for time series data. The sparsifying of input is done through a sparse transform input layer. Many applications that involve prediction or forecasting of the state of a dynamic system can be formulated as a time series forecasting problem. Here
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