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The year 2021 is expected to be a turning point, after a challenging year that has unexpectedly impacted our lives and interactions. In 2020, technological and scientific progress in the area of VLSI design has been relentless despite the difficulties that the year has brought. This has been made possible by the ability to adapt to the temporary “new normal” of our community of researchers, designers

This article proposes an encoding method based on a two-step encoding algorithm for the 12 quasi-cyclic (QC)-low-density parity-check (LDPC) (QC-LDPC) codes specified in the IEEE 802.11n/ac/ax standards. The proposed approach jointly considers all codes of the particular set, instead of targeting each code separately. The proposed algorithm performs multiplication by inverse matrices. The complexity

This study presents a technique for designing a multimode configurable weak physically unclonable function (PUF) for security-key generation. The PUF cell is based on the maximum gain point deviations of bias-voltage-controlled inverters. By implementing a preselection strategy, the proposed PUF can simultaneously expose all unstable cells under normal voltage and temperature. Owing to the configurable

This article presents large delay-based analog Trojan circuits, a new class of analog Trojans that can be interfaced with digital and analog macros to launch fabrication-time hardware attacks. Two different circuit topologies of analog Trojan are presented, which can generate a delayed trigger output after two days and 60 ms, respectively, when implemented in 65-nm CMOS technology. The large delay

Due to the fast-growing number of connected tiny devices to the Internet of Things (IoT), providing end-to-end security is vital. Therefore, it is essential to design the cryptosystem based on the requirement of resource-constrained IoT devices. This article presents a lightweight advanced encryption standard (AES), a high-secure symmetric cryptography algorithm, implementation on field-programmable

Counterfeit integrated circuits (ICs) have become a significant security concern in the semiconductor industry as a result of the increasingly complex and distributed nature of the supply chain. These counterfeit chips may result in performance degradation, profit reduction, and reputation risk for the manufacturer. Therefore, developing effective countermeasures against such malpractices is becoming

Memory-augmented neural networks (MANNs) were introduced to handle long-term dependent data efficiently. MANNs have shown promising results in question answering (QA) tasks that require holding contexts for answering a given question. As demands for QA on edge devices have increased, the utilization of MANNs in resource-constrained environments has become important. To achieve fast and energy-efficient

The superiority of convolutional neural network (CNN) has been proven in various object recognition tasks and has received much attention. However, the modern CNN approaches usually that assume the testing data and the training data belong to an identical category. Therefore, the current CNN approaches are not efficient for some applications with multisource data (i.e., the input data come from different

The IP core mapping optimization problem is an NP-hard problem in network-on-chip design. Because of the computational complexity of an IP core mapping, the MPNN-Ptr networks composed of the graph networks and the pointer networks are proposed to model the IP core mapping. The neural network IP core mapping model (NNMM) can effectively evaluate the probability of each mapping solution as the optimal

An integrated circuit that measures time intervals with high precision and accuracy has a wide range of applications including data conversion, ranging, and 3-D imaging. The resolution with which time intervals are quantized by a ring oscillator or delay line is limited by the minimum delay of an inverter in the technology. We propose the use of cyclic-coupled ring oscillators (CCROs) as a time-domain

Transform model estimation (TME) is a geometric operation, widely utilized in real-time imaging systems. Considering the massive computational load of matrix algebra-based TME realizations, most of the imaging systems resort to highly paralleled software-platform-based TME execution, which is power-intensive and expensive. Due to low-speed and power intensiveness, existing hardware for TME is not capable

This brief presents a second-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with two passive integrators. Due to the separation of the preamplifier, these two integrators become independent of each other and the size of the second integrator can be reduced. The NS SAR also realizes the zeros optimization of the noise transfer function (NTF). The analysis

Finite-field multiplication has received prominent attention in the literature with applications in cryptography and error-detecting codes. For many cryptographic algorithms, this arithmetic operation is a complex, costly, and time-consuming task that may require millions of gates. In this work, we propose efficient hardware architectures based on cyclic redundancy check (CRC) as error-detection schemes

Data movement between memory and processing units poses an energy barrier to Von-Neumann-based architectures. In-memory computing (IMC) eliminates this barrier. RRAM-based IMC has been explored for data-intensive applications, such as artificial neural networks and matrix-vector multiplications that are considered as “soft” tasks where performance is a more important factor than accuracy. In “hard”

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

Presents the table of contents for this issue of the publication.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

This year has certainly been peculiar in many respects for our communities across the globe. The challenges and the dramatic changes in the way we conduct our lives and professions have required an unprecedented degree of adaptation at several scales. Quite expectedly, this also applies to our editorial year and our community of readers and contributors to our journal, at the convergence of the sponsoring

Coarse-grained reconfigurable arrays (CGRAs) are used as low-power and high-performance accelerators in the processors of the Internet of Things (IoT) and embedded systems to accelerate the computation of intensive tasks. These accelerators speedup loops, including integer and fixed-point instructions of computation-intensive applications, in multimedia, voice coding, and encryption algorithms. The

Paper-based digital microfluidic biochips (or P-DMFBs) are becoming highly impelling due to its low-cost and in-place fabrication of electrodes and control wiring on a single piece of paper having an inkjet printer and conductive ink. Despite enormous advantages, several complex design rules also subsist, such as avoidance of induced control interference, minimum separation among the control lines

Beamforming technology plays an essential role in the promising millimeter wave (mmWave) massive multiple-input and multiple-output (MIMO) communications for fifth generation (5G) new radio system. Specifically, hybrid analog beamforming and digital precoding scheme can be employed to reduce the excessive radio frequency (RF) chains and data converters in the massive MIMO transceiver while still maintaining

Nonvolatile memory (NVM)-based computing in-memory (CIM) is a promising solution to data-intensive applications. This work proposes a 2T2R resistive random access memory (ReRAM) architecture that supports three types of CIM operations: 1) ternary content addressable memory (TCAM); 2) logic in-memory (LiM) primitives and arithmetic blocks such as full adder (FA) and full subtractor; and 3) in-memory

Cross-point-array nonvolatile ternary content-addressable memory (CPA nvTCAM) has recently emerged as an alternative to static random-access-memory-type TCAM, based on increased demands for high-capacity and low-power attributes. The CPA structure has various structural weaknesses such as the searchline (SL) combining with the dischargeline and the minimum line pitch of the matchline (ML). This study

Postquantum cryptography attracts a lot of attention from the research community recently due to the emergence threat from quantum computer toward the conventional cryptographic schemes. In view of that, NIST had initiated the standardization process in 2017. Bit flipping key encapsulation (BIKE) designed by Aragon et al. is one of the promising code-based schemes among the round-3 candidates. BIKE

The increased use of field-programmable gate arrays (FPGAs) in the cloud and embedded computing environments has led to a number of potential security risks. The sizable amount of logic resources in these devices makes them amenable to sharing across multiple untrusted tenants. However, the co-location of multiple independent circuits presents the possibility of malicious fault injection into an unsuspecting

In this article, a maximum-eye-tracking clock and data recovery (MET-CDR) circuits for minimum bit error rate (BER) are presented. The proposed CDR does not require a BER counter or an eye-opening monitor with any iterative procedure to find the optimal sampling phase. The biased data level obtained from the weighted sum of error sampler outputs provides the actual eye height (EH) information in the

This work demonstrates a dual-core RISC-V system-on-chip (SoC) with integrated fine-grain power management. The 28-nm fully depleted silicon-on-insulator (FD-SOI) SoC integrates switched-capacitor voltage converters and 4-Gb/s off-chip serial links. The SoC runs applications with operating system support on dual RISC-V Rocket cores with vector accelerators. Runtime monitoring of microarchitectural

In this brief, we present FracTCAM, an efficient methodology for ternary content addressable memory (TCAM) emulation on Xilinx field-programmable gate arrays (FPGAs) by leveraging primitive architectural resources. The proposed methodology exploits the fracturable nature of lookup table random access memories (LUTRAMs) and built-in slice flip-flops for deeper pipelining. Multiple slices can be combined

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

Presents the table of contents for this issue of the publication.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

This article describes a wideband low-noise frequency synthesizer implemented in 0.13- $\mu \text{m}$ SiGe BiCMOS process for 5G millimeter-wave applications. To extend the frequency range while reducing the phase noise, a fundamental voltage-controlled oscillator (VCO) array including four Colpitts VCO cores with switchable bias circuits is adopted in the proposed frequency synthesizer. A ring-oscillator-based

This article presents the theoretical analyses and experimental results about jitter tolerance for delay-locked loop (DLL)-based clock and data recovery (CDR), which is generally used in an embedded clock serial link. From the proposed S-domain model, we prove that DLL-based CDR has superior low-frequency jitter tolerance than PLL-based CDR, whereas, assuming the ideal case, high-frequency jitter tolerance

This article presents a discrete-time parametric amplifier (DTPA) as the signal demodulator for chopper amplifier. Unlike the conventional chopper, the DTPA demodulator features noise-efficient gain augmentation while demodulating the chopped signal. The demodulator also enables low-frequency noise cancellation during the inherent track-and-hold (T/H) process of the charge parametrization. The positive

This article presents a novel class of bistable physically unclonable functions (PUFs) for security-oriented applications. The traditional cross-coupled bistable PUF cell is divided into P-net and N-net, wherein the P-net (N-net) multiplexing acts as the shared head (foot), and the N-net (P-net) duplicating multiple acts as the PUF cell. The proposed PUF was fabricated in a Taiwan Semiconductor Manufacturing

Homomorphic encryption (HE) allows direct computations on encrypted data. Despite numerous research efforts, the practicality of HE schemes remains to be demonstrated. In this regard, the enormous size of ciphertexts involved in HE computations degrades computational efficiency. Near-memory processing (NMP) and computing-in-memory (CiM)—paradigms where computation is done within the memory boundaries—represent

Recently, extensive research attention has been drawn to the program executing security of embedded processor since increasing code tamper attacks, as well as transient faults severely affect the safety of embedded systems. The security monitoring and fault recovery technique is one of the effective methods to ensure the security and performance of embedded devices. In this article, an architecture

Thermal issues seriously restrict the quality, reliability, and lifetime of semiconductor chips. To prevent thermal runaway situations, modern processors deploy numerous on-die thermal sensors to collect temperature information, which is then used to guide dynamic thermal management (DTM) mechanisms. Accurate on-chip temperature information is critical for DTM as temperature overestimation will degrade

In this article, we propose a fast thermal modeling tool, 3DSim , using a Green’s-function-based approach. Green’s-function-based approaches have been shown to be faster than the traditional finite-difference-based techniques. Our proposed tool can model steady-state and transient thermal profiles for both 2-D and 3-D chips, which may contain multiple active layers and fluid-carrying microchannels

Nowadays, hyperspectral imaging is recognized as a cornerstone remote sensing technology. Next generation, high-speed airborne, and space-borne imagers have increased resolution, resulting in an explosive growth in data volume and instrument data rate in the range of gigapixel per second. This competes with limited on-board resources and bandwidth, making hyperspectral image compression a mission critical

We report a realization of a mixed-signal, supervised spiking neural network (SNN) architecture utilizing short-term plasticity in synaptic resistive random access memory (RRAM). First, the development of a phenomenological RRAM SPICE model is discussed based on the previously reported device data. Then, the design of the neuroprocessor’s architectural components are described. To achieve learning

Rapid single-flux quantum (RSFQ) circuits have recently attracted considerable attention as a promising cryogenic beyond CMOS technology for exascale computing. Energy-efficient RSFQ (ERSFQ) is an energy-efficient, inductive bias scheme for RSFQ circuits, where the power dissipation is drastically lowered by eliminating the bias resistors, while the cell library remains unchanged. An ERSFQ bias scheme

A new trend in system-on-chip (SoC) design is chiplet-based IP reuse using 2.5-D integration. Complete electronic systems can be created through the integration of chiplets on an interposer, rather than through a monolithic flow. This approach expands access to a large catalog of off-the-shelf intellectual properties (IPs), allows reuse of them, and enables heterogeneous integration of blocks in different

Printed electronics (PE) enables disruptive applications in wearables, smart sensors, and healthcare since it provides mechanical flexibility, low cost, and on-demand fabrication. The progress in PE raises trust issues in the supply chain and vulnerability to reverse engineering (RE) attacks. Recently, RE attacks on PE circuits have been successfully performed, pointing out the need for countermeasures

We continue the study of Mastrovito form of Karatsuba (MK) multipliers under the shifted polynomial basis (SPB). An MK multiplier utilizes Karatsuba algorithm and Mastrovito approach to optimize polynomial multiplication and modular reduction, which lead to a better space and time tradeoff for all trinomials. Based on this work, we make two types of contributions: 1) We derive a new modular reduction

Tabu-list random-penalty gradient descent bit-flipping (TRGDBF) decoder is the state-of-the-art hard-decision low-density parity-check (LDPC) decoder in terms of error-correction performance on binary symmetric channel (BSC). However, the TRGDBF decoder suffers from a long critical path caused by the global maximum-finding operation, limiting the achievable throughput. This brief proposes an information

This study proposed a novel nonvolatile static random access memory (nvSRAM) cell with two ferroelectric capacitors (FeCAPs) embedded inside a 4T SRAM cell, i.e., 4T2C, for minimal area penalty and full logic compatibility. The FeCAP with 10-nm-thick Hf 0.5 Zr 0.5 O 2 film shows excellent ferroelectricity (Pr $= 15\,\,\mu \text{C}$ /cm 2 ) and good memory characteristics (cycles $> 10^{11}$ ). The

A 2.4-GHz area-efficient and fast-locking subharmonically injection-locked type-I phase-locked loop (SIL-TPLL) is presented. A timing-adjusted phase detector (TPD) is proposed to calibrate the injection timing. This TPD also reduces the settling time of the SIL-TPLL. The loop capacitance of the type-I PLL is tiny to save the area. This SIL-TPLL is fabricated in 45-nm CMOS technology. Its active area

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This article proposes reconfigurable maximum a posteriori (MAP) decoding algorithm which operates in multiple radix modes to hard decode the information bits with variable throughput by consuming constant power. Subsequently, a new digital decoder-architecture for this MAP decoding algorithm has been designed that operates in radix-2/4/8 modes. Furthermore, reconfigurable microarchitectures of state-metric

Multicycle tests have several advantages including the ability to support test compaction. By extracting multicycle functional broadside tests from functional test sequences, it is possible to ensure functional operation conditions during the functional capture cycles between the scan operations of a test. The challenge that this article addresses is that the computational effort of extracting $l$

This article presents a novel facial biometrics-based hardware security methodology to secure hardware accelerators [such as digital signal processing (DSP) and multimedia intellectual property (IP) cores] against ownership threats/IP piracy. In this approach, an IP vendor’s facial biometrics is first converted into a corresponding facial signature representing digital template, followed by embedding

When mapping C programs to hardware, high-level synthesis (HLS) tools reorder independent instructions, aiming to obtain a schedule that requires as few clock cycles as possible. However, when synthesizing multithreaded C programs, reordering opportunities are limited by the presence of atomic operations (“atomics”), the fundamental concurrency primitives in C. Existing HLS tools analyze and schedule

Multicycle tests are useful for test compaction even when full scan allows single- or two-cycle tests to be used. To avoid sequential test generation, multicycle tests can use the test data (scan-in states and primary input vectors) from a single- or two-cycle test set, possibly modified to make it more suitable for multicycle tests. However, the modification process requires repeated fault simulation

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This article presents a low-power 1/4-rate four-level pulse amplitude modulation (PAM4) receiver with an adaptive variable-gain rectifier (AVGR)-based decoder in 28-nm CMOS technology. The PAM4 input signal is preconditioned by a continuous-time linear equalizer (CTLE) then sampled into four branches of decoders by 1/4-rate clocks. The proposed AVGR-based PAM4-to-nonreturn-to-zero (NRZ) decoder performs

The SRAM-based field-programmable gate array (FPGA) is extremely susceptible to single event upsets (SEUs) on configuration memory which can lead to soft error and malfunction of the circuit. Facing the ever-growing number of configuration bits in modern FPGAs, traditional scrubbing is getting harder to find errors in time, resulting in mismatching between the SEU sensitivity and scrubbing performance