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This work presents adder and subtracter architectures for stochastic computing (SC). In contrast to standard approaches, the result of their operation is nonscaling, i.e., $X\,\pm \,Y$ , and this is achieved via a deterministic operation based on a counting process. These properties result in an improved tradeoff between accuracy and stochastic sequence length, fast convergence, and the potential for

Radio resource management (RRM) is critical in 5G mobile communications due to its ubiquity on every radio device and its low latency constraints. The rapidly evolving RRM algorithms with low latency requirements combined with the dense and massive 5G base station deployment ask for an on-the-edge RRM acceleration system with a tradeoff between flexibility, efficiency, and cost-making application-specific

In network-on-chip (NoC) designs, the intellectual property (IP) mapping problem is a critical issue and is usually solved by heuristic searches. However, heuristic searches suffer from the problem of easily falling into the local optimum. To tackle this problem, this article proposes a reinforcement learning-based framework (RLF), which enhances the performance of heuristic searches through the neural

High temperature or temperature nonuniformity has become a serious threat to performance and reliability of high-performance integrated circuits (ICs). Since the temperature in a 3-D IC is mainly determined by a power distribution across tiers, this article proposes a novel method to allocate modules to tiers while exploring a better power distribution according to the hyperparameter optimization technique

This brief describes a fully integrated 10-V pulse driver. It comprises a four-stage switched-capacitor voltage multiplier (SCVM) and a dedicated high-voltage output driver (HVOD) with multiband pulse-frequency modulation (MPFM) to generate efficiently 10 V regulated output pulses. Specifically, an analog/digital hybrid-controlled current-starved ring oscillator (HCRO) modulates the switching frequencies

A novel single parity check-multiplicity assignment decoding algorithm based on voltage magnitude (VM_SPC-MA) is proposed, which is applied to the concatenated scheme of single parity check (SPC) inner code and Reed–Solomon (RS) outer code, following the Consultative Committee for Space Data Systems (CCSDS) standard. The algorithm determines whether the SPC code is in error by SPC, then obtains the

Multithreaded applications are capable of exploiting the full potential of many-core systems. However, network-on-chip (NoC)-based intercore communication in many-core systems is responsible for 60%–75% of the miss latency experienced by multithreaded applications. Delay in the arrival of critical data at the requesting core severely hampers performance. This brief presents some interesting insights

In the backpropagation algorithm, the error calculated from the output of the neural network should backpropagate the layers to update the weights of each layer, making it difficult to parallelize the training process and requiring frequent off-chip memory access. Local learning algorithms locally generate error signals which are used for weight updates, removing the need for backpropagation of error

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Printed electronics (PE) is an emerging technology that provides attractive and complementary features compared to traditional wafer-scale silicon fabrication, such as flexible substrate and point-of-use ultralow-cost manufacturing. The low-cost manufacturing and larger feature sizes mandate reduced complexity in circuit size and also limited and transparent printing layers. This enables optical inspection

Emerging nonvolatile memories (NVMs), such as resistive RAM (RRAM) and spin-transfer-torque RAM (STTRAM), present exciting opportunities for data storage applications and offer improved access speeds, retention times, power consumption, and scalability. However, these technologies leak the Hamming weight of data through power side-channel during read and write operations. We propose a technique leveraging

Hardware intellectual property (IP) piracy and misuse have introduced new challenges in the semiconductor industry as untrusted parties in the IP’s life cycle may clone, reverse-engineer, or extract important design secrets from an IP. A promising solution to protect a hardware IP against such attacks is to perform logic locking, where additional logic controlled by a secret key is inserted in strategic

This article presents multiwire phase encoding (MWPE), a transition signaling technique aimed at chip-to-chip communication on silicon interposer technology, where multiple, relatively low-bandwidth transmission lines can be easily routed between high-performance dies. The encoding exploits timing correlation between transitions on multiple band-limited wires to achieve high ensemble bandwidth, potentially

Hybrid test schemes comprising on-chip test compression and logic built-in self-test are expected to play a pivotal role in the design of new integrated circuits and delivering high quality tests. As architectural differences between these two paradigms are gradually blurring, and both schemes efficiently share test logic, they become more vulnerable to unknown (X) states whose sources vary from uninitialized

This article presents an receiver (RX) only equalization (ROE) technique that eliminates feed-forward equalization (FFE) in transmitter (TX) and bandwidth improved output driver without increment of power consumption. With a help of the proposed design technique, the power consumption, circuit complexity, and design cost are improved. The proposed RX with one-tap finite-impulse response (FIR) and second-tap

To minimize the area of analog-to-digital converters (ADCs) for multichannel applications and break the SNDR limitation caused by DAC-induced nonlinearity, a more area-efficient mismatch error shaping (MES) scheme is proposed in noise shaping (NS) successive-approximation (SAR) ADC. By employing a switched-capacitor (SC) voltage divider, the proposed method makes the flash ADC and data weighted averaging

Write assists (WAs), such as negative bitline and collapse supply voltage (VDD), can effectively improve the write $V_{\text {min}}$ of static random access memory (SRAM) cells. The energy overhead associated with such assists is considerable due to the switching activities on high capacitive nodes for every write operation. In this brief, a conditional biasing WA with built-in time-based write-margin-tracking

This brief presents a novel timing mismatch background calibration algorithm for time-interleaved (TI) analog-to-digital converters (ADCs). It can calibrate an arbitrary number of channels with an arbitrary input frequency. It also increases the calibration accuracy by applying the autocorrelation functions with an expanded interval. Besides, the proposed algorithm effectively prevents the small derivative

Single event transients (SETs) have become increasingly problematic for modern CMOS circuits due to the continuous scaling of feature sizes and higher operating frequencies. Especially when involving safety-critical or radiation-exposed applications, the circuits must be designed using hardening techniques. In this brief, we present a new radiation-hardened-by-design full-adder cell on 45-nm technology

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This article focuses on thwarting reverse-engineering attacks and intellectual property (IP) theft by leveraging charge-recycling adiabatic circuits. The adiabatic circuit operation has recently received attention for the Internet-of-Things (IoT) applications due to high energy efficiency and enhanced security characteristics. Such applications typically consist of resource-constrained designs and

This article presents highly optimized implementations of the Ed25519 digital signature algorithm [Edwards curve digital signature algorithm (EdDSA)]. This algorithm significantly improves the execution time without sacrificing security, compared to exiting digital signature algorithms. Although EdDSA is employed in many widely used protocols, such as TLS and SSH, there appear to be extremely few hardware

Semiconductor design companies are integrating proprietary intellectual property (IP) blocks to build custom integrated circuits (ICs) and fabricate them in a third-party foundry. Unauthorized IC copies cost these companies billions of dollars annually. While several methods have been proposed for hardware IP obfuscation, they operate on the gate-level netlist, i.e., after the synthesis tools embed

Operating circuits under cryogenic conditions is effective for a large spectrum of applications. However, the refrigeration requirement for the cooling of cryogenic systems introduces serious issues in terms of power dissipation. Gain-cell embedded dynamic random access memory (GC-eDRAM) is a low-area, logic-compatible embedded memory alternative to static random access memory (SRAM), which has the

As device integration density increases exponentially as predicted by Moore’s law, power consumption becomes a bottleneck for system scaling where leakage power of on-chip cache occupies a large fraction of the total power budget. Spin transfer torque magnetic random access memory (STT-MRAM) is a promising candidate to replace static random access memory (SRAM) as an on-chip last level cache (LLC)

Nowadays, many data are multidimensional, which are called tensors. Tensor computations have been applied in different fields and various software libraries have been developed. However, not much attention has been received for developing a hardware architecture to accelerate the tensor computations. In this article, an efficient and unified processing element (PE) array for the 3-D tensor computation

Physical layer signal processing algorithms in the wireless domain are seeing increased use of machine learning algorithms, especially Bayesian methods. This work presents the hardware architecture and implementation of a vector processor for one such application, Bayesian channel estimation (CE) (BCE). The BCE vector processor supports a generic instruction set with a supplement of specialized instructions

A modified noise/nonlinearity cancellation low-noise transconductance amplifier (LNTA) based on an inductively degenerated common-source stage is proposed to improve linearity. The linearity of the proposed LNTA is analyzed using the Volterra series yielding closed-form equations for the third-order input intercept point (IIP3) that shows excellent matching with the simulation results. The derived

A fast and accurate statistical eye diagram estimation method for high-speed nonlinear links is proposed in this article. Probability density functions (PDFs) of output responses are derived based on multiple edge responses (MERs). According to the property that the influence of nonlinearity will not propagate for a long time in high-speed links, a new scheme for calculating the PDFs of responses is

This article presents a high-sensitivity and high energy efficiency wake-up receiver (WuRx) based on an injection-locked oscillator (ILO) and an envelope detector to provide the capabilities of reliable demodulation for ON–OFF keying (OOK), binary frequency shift keying (BFSK), and differential binary phase shift keying (DBPSK) demodulation schemes. A 54- $\mu \text{W}$ 433-MHz multimode WuRx is implemented

Efficient Kalman filter (KF) designs for real-time mobile applications, such as nano-drones navigation, robots localization, spacecraft orbit control, GPS positioning, image recognition, and multisensor data fusion for wearable systems, are key technology goals. The KF is a compute-intensive kernel composed of consecutive complex matrix operations, like multiplications and matrix inversions. The most

This article describes a gain-stabilized integration time generation technique suitable for the pipelined successive approximation register (SAR) analog-to-digital converter (ADC) utilizing an open-loop integrator-based residue amplifier (RA). The gain variation of RA under different process, voltage, and temperature (PVT) conditions is alleviated by adaptively adjusting the length of the generated

The converter proposed in this article is a new improved voltage-square buck converter using a rail-to-rail OTA-based current-sensing circuit. This circuit architecture used a constant on-time modulation mode and uses a rail-to-rail OTA-based inductor-current-sensing circuit to form a current feedback path. The rail-to-rail OTA-based current sensor has wide input range, so it can be directly connected

In this work, we address the synthesis problem of two-phase bundled-data asynchronous pipeline controllers, in which the insertion of buffers is essential for guaranteeing the correct handshaking operation on every pipeline stage at the expense of considerable area increase. To lighten the pipeline controllers, we introduce a new logic synthesis concept called delay path sharing and reusing , by which

Recent advances in microfluidics and microfabrication technology enabled the emergence of a new microelectrode-dot-array (MEDA) architecture for microfluidic biochips. The MEDA-based design allows dynamic routing with variable-sized droplets. The cross contamination avoidance between droplets of different biomolecules subjected for analysis and detection on MEDA architecture poses a major design challenge

Decision trees (DTs) are profusely used in machine learning (ML) applications on account of their fast execution and high interpretability. As DT training is time-consuming, in this brief, we proposed a hardware training accelerator to speedup the training process. The proposed training accelerator is implemented on the field-programmable gate array (FPGA) having a maximum operating frequency of 62

In this brief, we propose a logarithmic converter for floating-point numbers based on the piecewise linear (PWL) approximation method. The proposed method is applicable to any customized floating-point format with a mantissa length of 16–23 bits and a maximum absolute error (MAE) larger than 10 −6 . The logarithmic function is automatically segmented into several maximal subsections by a software-based

Modern integrated circuits (ICs) include thousands of on-chip instruments to ensure that specifications are met and maintained. Scalable and flexible access to these instruments is offered by reconfigurable scan networks (RSNs), e.g., IEEE Std. 1687. As RSNs themselves can become faulty, there is a need to exclude and bypass faulty parts so that remaining instruments can be used. To avoid keeping track

This brief presents a bidirectional nonlinearly coupled quadrature voltage-controlled oscillator (BNC-QVCO) incorporating passive phase interpolation for the generation of multiphase signals. In addition, to generate multiphase signals, the proposed bidirectional nonlinearly coupling network improves the phase noise performance of the QVCO by producing approximate-in-phase injection-coupling currents

This brief presents a three-stage comparator and its modified version to improve the speed and reduce the kickback noise. Compared to the traditional two-stage comparators, the three-stage comparator in this work has an extra amplification stage, which enlarges the voltage gain and increases the speed. Unlike the traditional two-stage structure that uses pMOS input pair in the regeneration stage, the

This brief presents a novel pipelined VLSI architecture for computing discrete wavelet packet transform (DWPT) with an arbitrary wavelet tree. Coefficients for different levels are computed in a series of stages. Each stage consists of a bypassed wavelet filter and circuit for reordering intermediate coefficients. The proposed lifting-based wavelet filter computes high- and low-pass coefficients in

Embedded static random access memories (SRAMs) with cost-effective test screening circuitry are demonstrated for low-power microcontroller units (MCUs). The probing test step at the low temperature (LT) of −40 °C is obviated by imitating pseudo-LT (PLT) conditions in the package test, where a sample is measured at room temperature (RT). Monte Carlo simulation is carried out considering local $V_{\mathrm

Two-cycle gate-exhaustive faults provide a comprehensive model for delay defects that are localized to gates (cells or subcircuits). However, the number of two-cycle gate-exhaustive faults can be excessive. Cell-aware faults are obtained by performing layout analysis of cells to select faults that are important to detect. This article suggests a complementary view of faults that are important to detect

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This article presents a low-voltage high-transconductance input differential pair for bulk-driven amplifiers. The proposed structure employs two bulk-driven flipped voltage follower (FVF) cells as nonlinear tail current sources to enhance the slewing behavior. This method also increases the transconductance of the proposed amplifier two times against the conventional one. The enhanced topology is merged

Integrated circuits operating in the near/subthreshold region offer low energy consumption. However, due to the constrained voltage scalability of SRAMs, efficient power delivery is difficult to achieve. A traditional implementation would require at least two distinct voltage supplies generated by possibly two power converters. In this article, a new implementation for near/subthreshold operation is

In this work, a generalized power supply induced jitter (PSIJ) model is proposed. The PSIJ sensitivity is obtained based on the evaluation of driver power supply rejection ratio (PSRR) response. The voltage ripple at the driver output is transformed into driver output jitter with the slope of the switching edge. The time-averaged effect of power noise during the time range of driver propagation delay

The security of IoT devices is becoming a major concern in industry. Noninvasive side-channel attacks pose a serious threat as they are capable of extracting secret information from distance while using low-cost equipment. In this article, we propose an efficient countermeasure technique against the electromagnetic (EM) side-channel attacks. The technique is applied to switched-capacitor (SC) dc–dc

Achieving the attractive error-correcting capability with a simple decoder structure, the polar code using successive cancellation (SC) decoding is now expected to be installed at the resource-limited IoT or embedded communications. However, the existing SC decoders normally suffer from the long processing latency caused by the serialized processing steps, limiting the practical applications of polar

In this article, we design a memristive competitive neural network circuit based on the winner-take-all (WTA) mechanism and the online Hebbian learning rule. Each synapse of the network contains two memristors whose terminals of signal inputs are opposite. However, only one memristor participates in the calculation each time, and that one is determined by the original input signal. The competitive

To overcome the “von Neumann bottleneck,” methods to compute in memory are being researched in many emerging memory technologies, including resistive RAMs (ReRAMs). Majority logic is efficient for synthesizing arithmetic circuits when compared to NAND/NOR/IMPLY logic. In this work, we propose a method to implement a majority gate in a transistor-accessed ReRAM array during the READ operation. Together

Aerospace applications are attractive candidates to embed artificial neural networks despite their excellent parallel processing capability and reduced energy consumption. Nonetheless, the long-term exposure to incidence levels of ionizing radiation may degrade their physical components reducing, therefore, their reliability and expected lifetime. Thus, it is mandatory to face the challenge of enhancing

With increasing modulation order, a larger number of parallel source-series-terminated (SST) segments are required to implement precise feedforward equalization (FFE) tap-weight control in SST transmitters (TX). Due to the data routing complexity of the segmented structure, the dynamic power consumption of SST TX has become much more significant causing degradation in energy efficiency. This article