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Mixed-signal components, such as low dropouts (LDOs) and phase locked loops (PLLs), are widely used inside the on-chip power management fabric of low power integrated system-on-chip (SoC) designs. The digital brain of the power management logic that is responsible for regulating the power delivery to different power domains in the chip has to consider the real time latencies of the analog components

This article presents a fully differential (FD) low-voltage (LV) fourth-order Butterworth active- RC low-pass filter (LPF) with a maximum cutoff frequency $(f_{o})$ of 160 MHz, $f_{o}$ programmability, and adaptive power. The proposed filter targets communication systems requiring high and reconfigurable $f_{o}$ at supply voltages $(V_{\mathrm {DD}}s)$ of 0.6 V. The filter is implemented with an active-

This article presents two novel structures for designing current mode logic (CML) digital circuits [MOS CML (MCML) and multiple tail CML (MTCML)] in ultralow-power (ULP) and high-speed (HS) applications. The transistor’s bulk can be used as a digital signal input at a level, where it does not cause a disturbance to the operation of the transistor. Therefore, the number of transistors used in novel

Small-footprint implementations of the advanced encryption standard (AES) algorithm are of interest in resource-constrained applications like Internet of Things (IoT). Symmetries in AES allow the datapath to be scaled down to the S-Box width of 8 bits, but the ShiftRows operation leads to a potential data hazard that must be avoided. The common method for resolving the ShiftRows hazard wastes power

Stochastic computing (SC) in recent years has been defined as a digital computation approach that operates on streams of random bits that represent probability values. SC can perform complex tasks with much smaller hardware footprints compared with conventional binary methods, but previous methods on SC circuits operated on serial bit streams, which leads to high-latency implementations. This article

Data processing on convolutional neural networks (CNNs) places a heavy burden on energy-constrained mobile platforms. This article optimizes energy on a mobile client by partitioning CNN computations between in situ processing on the client and offloaded computations in the cloud. A new analytical CNN energy model is formulated, capturing all major components of the in situ computation, for ASIC-based

This article presents a majority-logic device, called sttMAJ, based on spin-transfer torque magnetic tunnel junctions (STT-MTJs). sttMAJ devices make it possible to build Boolean and non-Boolean circuits without any transistors. We leverage a physics-based model of sttMAJ device to the design of different highly scalable current-mode logic circuits and neuromorphic-computing/image-processing applications

Deconvolutional neural network (DeCNN), such as fully convolutional network (FCN) and generative adversarial network (GAN), has shown great potential in various vision tasks. Convolution and deconvolution, the two major operations of DeCNN, both require real-time hardware acceleration. However, some previous designs for deconvolutions require large memory for overlapped results, while others incur

This article presents a class of integer codes that are suitable for use in optical computer networks in which the data are transmitted serially. The presented codes are constructed with the help of a computer and have three desirable properties. First, they use integer and lookup table operations, which make them suitable for software implementation. Second, depending on the application requirements

Gesture recognition has increasingly become one of the most popular human–machine interaction techniques for smart devices. Existing gesture recognition systems suffer from either excessive power consumption or large size, limiting their applications for ultralow-power wearable devices. This article presents an accurate area-efficient and low-power real-time gesture recognition system for smart wearable

In this brief, a 300-mV, auto shutdown comparator based on a novel clock gating network is proposed. The proposed auto shutdown comparator is further employed to realize a compact, ultralow power continuous-time $\Delta \Sigma $ modulator (CTDSM) with a 300-mV supply voltage for multichannel sensing and biomedical applications. The design was fabricated in standard mixed-mode 180-nm CMOS process. Measurement

Software-defined networks (SDNs) are the future networks that enable the system to be more flexible and programmable using a centralized controller. Field-programmable gate arrays (FPGAs) serve as exemplary hardware to implement these adaptable networks. Ternary content-addressable memory (TCAM) is an essential part of every network to perform packet classification and forwarding, but they are missing

Reverse order fault simulation and its variations provide a test compaction option with a low computational effort that is applicable even when test constraints or complex fault models preclude the application of other conventional test compaction procedures. This is the scenario considered in this brief. Reverse order fault simulation procedures remove unnecessary tests from a test set without otherwise

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

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In this article, we design the first full software/ hardware stack, called Uni-OPU , for an efficient uniform hardware acceleration of different types of transposed convolutional (TCONV) networks and conventional convolutional (CONV) networks. Specifically, a software compiler is provided to transform the computation of various TCONV, i.e., zero-inserting-based TCONV (zero-TCONV), nearest-neighbor

The emergence of hardware accelerators has brought about several orders of magnitude improvement in the speed of the deep neural-network (DNN) inference. Among such DNN accelerators, the Google tensor processing unit (TPU) has transpired to be the best-in-class, offering more than $15\times $ speedup over the contemporary GPUs. However, the rapid growth in several DNN workloads conspires to escalate

The use of lower precision has emerged as a popular technique to optimize the compute and storage requirements of complex deep neural networks (DNNs). In the quest for lower precision, recent studies have shown that ternary DNNs (which represent weights and activations by signed ternary values) represent a promising sweet spot, achieving accuracy close to full-precision networks on complex tasks. We

In this article, the accuracy of inverter-based memristive neural networks (NNs) for function approximation applications is improved under the presence of process variations. The improvement is achieved by using a design approach, called INTERSTICE (Inverter-based Memristive Neural Networks Dis cretization for Function Approximation Applications), which discretizes the output values by employing a

The effects of supply-induced frequency variations on single-ended tuning $LC$ voltage-controlled oscillator (VCO) which degrade the jitter performance of the clock are investigated. The first-order impact on the supply sensitivity is that the varactor’s effective capacitance varies with the supply voltage, with other second-order impacts attributed to commonly used capacitive bank and cross-coupled

This article presents a 32-GHz frequency-modulated continuous wave (FMCW) modulator based on the phase-locked loop (PLL) with nested sub-PLL structure in a 65-nm CMOS process. With the sub-PLL, the low-pass effect in phase domain is realized, reducing the noise folding effect, quantization noise, and spurs due to the delta sigma modulator (DSM). To achieve good stability and phase noise performance

During the past decade, model order reduction (MOR) has become key enabler for the efficient simulation of large circuit models. MOR techniques based on balanced truncation (BT) offer very good error estimates and can provide compact models with any desired accuracy over the whole range of frequencies (from dc to infinity). However, in most applications the circuit is only intended to operate at specific

Multistage amplifiers are a reliable method of achieving high gain in systems where the voltage supply is low. The common practice is to prefer 3-stage amplifiers over 4-stage ones when a gain of < 120 dB is required, since the former are easier to compensate. In this article, we employ four stages to relax the constraints on each stage. An extension of the single-Miller-capacitor compensation and

This article proposes a bit-time-dependent behavioral model of input–output (I/O) drivers for overclocking simulation. The driver behavior under overclocking conditions is investigated, and the corresponding weighting function response surface is demonstrated. In contrast to the previous approaches that use fixed timing signals extracted under normal operating conditions only, the proposed model addresses

As one of the most promising candidates for nonvolatile memory, phase change memory (PCM) technology has shown great performance advantages in market applications. However, the conventional test methods have not kept pace with the development. In this article, focusing on specific PCM faults and others, an enhanced march test algorithm is proposed to achieve 100% fault coverage and diagnostic accuracy

Energy efficiency is a critical design objective in deep learning hardware, particularly for real-time machine learning applications where the processing takes place on resource-constrained platforms. The inherent resilience of these applications to error makes voltage scaling an attractive method to enhance efficiency. Timing error probability models are proposed in this article to better understand

The scheduling of data access plays a prominent part in a memory-based fast Fourier transform (FFT) processor. In this article, a conflict-free data-access scheme is proposed and applied to implement a radix- $2^{k}$ FFT processor with the computing parallelism being the power of 2. The proposed FFT module exploits single-port RAMs to retain the area efficiency, and it has the following hardware-friendly

We present a 64-Gb/s four-level pulse amplitude modulation (PAM-4) optical receiver with the amplitude/phase correction and the threshold voltage/data level calibration, utilizing an inverter-based transimpedance amplifier (TIA). A variable gain amplifier (VGA) with the amplitude/phase correction is also presented. The threshold voltage of the data slicers and the data levels for the error slicers

In this brief, a cobweb-based redundant through-silicon-via (TSV) design is proposed with efficient hardware as well as high repair rate to repair clustered faulty TSVs (FTSVs). The experimental simulation results demonstrate that for highly clustered faults, the repair rate of the proposed RTSV method is 48.59% and 1.75% higher than that of the ring-based and router-based RTSV methods, respectively

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Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

In this article, we propose an efficient circuit reliability analysis infrastructure utilizing on-demand transistor-accurate fault injection based on workload-specific distributional properties. A novel two-phase approach is developed to achieve circuit-level accuracy, via careful transistor-level precharacterization, and gate-level efficiency, via fast runtime fault generation. A time-consuming circuit

Soft error protection is a paramount requirement for memories exposed to radiation environment. To satisfy the demand, a radiation-hardened new-quatro 10T memory cell is proposed in this brief, which is immune to single-node upset and also has high resilience to multinode upset while features read-disturbance-free benefiting from its internal quad-node interlocked feedback mechanism. Simulation results

Test sequences that do not use scan chains have several advantages as manufacturing tests. Test sequences can be produced by sequential test generation procedures, and static test compaction can be applied to reduce the length of the sequence without losing fault coverage. A typical sequential test generation procedure that produces a single test sequence concatenates test subsequences to form the

Due to the rapid advance of integrated circuit (IC)-related technologies, design complexity is dramatically increasing in printed circuit boards (PCBs). Nowadays, a dense PCB contains thousands of pin shapes and signal nets, and such a huge net count makes the manual design of PCBs an extremely time-consuming task, especially in the routing phase. Bus routing, which consists of assigning all the buses

Digital signal processing (DSP) on field-programmable gate arrays (FPGAs) has long been appealing because of the inherent parallelism in these computations that can be easily exploited to accelerate such algorithms. FPGAs have evolved significantly to further enhance the mapping of these algorithms, included additional hard blocks, such as the DSP blocks found in modern FPGAs. Although these DSP blocks

A hybrid Miller-Cascode compensation (HMCC) scheme incorporating Miller compensation (MC) and cascode compensation on a nonsignal path (CCNSP) in the two-stage amplifiers is presented. The proposed HMCC resolves issues in other compensations such as CCNSP, cascode compensation on a signal path (CCSP), and hybrid cascode compensation (HCC) such that the gain peaking near unity gain frequency (UGF) in

Presents the table of contents for this issue of the publication.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

Most very-large-scale integration (VLSI) designs of the global optical flow method focus on reducing external memory accesses due to global and iterative processes for low-power operation in mobile systems. However, to achieve this goal, considerable amounts of resources are used and the throughput is decreased. To address these issues, we propose a multirow-based propagation approach and an efficient

Hardened adder and carry logic is widely used in commercial field-programmable gate arrays (FPGAs) to improve the efficiency of arithmetic functions. There are many design choices and complexities associated with such hardening, including circuit design, FPGA architectural choices, and the computer-aided design (CAD) flow. However, these choices have not been studied much and hence we explore a number

Though belief propagation (BP) polar decoders can achieve higher throughput than successive-cancellation (SC)-based decoders, and how to efficiently generate different belief propagation decoders (BPDs) which can meet various design specifications remains challenging. To this end, an autogeneration, which can translate the generation formula of BPDs to efficient hardware implementations, has been proposed

Presents the table of contents for this issue of the publication.

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Convolutional neural networks (CNNs) have been widely adopted for computer vision applications. CNNs require many multiplications, making their use expensive in terms of both computational complexity and hardware. An effective method to mitigate the number of required multiplications is via the Winograd algorithm. Previous implementations of CNNs based on Winograd use the 2-D algorithm $F(2 \times

This article presents hardware implementation for computing arbitrary roots of a single-precision floating-point number. The proposed architecture is based on Generalized Hyperbolic COordinate Rotation Digital Computer (GH CORDIC) algorithm. Benefiting from the wide range of floating-point numbers, our design is able to compute the ${N}$ th root ( ${N} {\ge 2}$ ) of a single-precision floating-point

In recent years, several approximate adders have been proposed which are targeted for energy-efficient system design specific to error-tolerant applications. An approximate least significant bit (LSB) adder (ALA) is one such class of adder which is composed of two adder segments: one accurate most significant adder segment and one LSB adder segment approximated with inexact adder components. Error

Unlike central processing units (CPUs), field-programmable gate arrays (FPGAs) have conventionally been powered with a fixed supply voltage ( $V_{\text {dd}}$ ). However, recent efforts have shown that adopting dynamic voltage scaling reduces FPGA power consumption significantly. In this article, we analyze the delay sensitivity of different FPGA circuit elements to supply voltage changes and determine

An extremely high-resolution, 2-D Vernier field-programmable gate array (FPGA) time-to-digital converter (TDC) with phase wrapping and averaging has been proposed recently to get an extremely fine resolution of 2.5 ps. However, the cell delays in a delay matrix are not fully controlled so that the TDC performance strongly depends on the stochastic distribution of cell delays, and the input range is

This article presents an approach to providing fault tolerance to permanent effects in the substrate of dynamic, partially reconfigurable field-programmable gate arrays (FPGAs). Our proposal consists of modifying FPGA configuration at runtime to avoid permanently damaged regions of the FPGA. It demands that the circuit design fulfills several requirements regarding the functionality and interfaces

This article presents a high-throughput and low-routing complexity low-density parity check (LDPC) decoder design based on a novel second minimum approximation min-sum (SAMS) algorithm. The routing congestion is mitigated by reducing the required interconnections in the critical path of the routing network. The implementation and postlayout results with 28-nm 1P9M CMOS process show that the proposed

Multichannel active noise control (MCANC) is widely recognized as an effective and efficient solution for acoustic noise and vibration cancellation, such as in high-dimensional ventilation ducts, open windows, and mechanical structures. The feedforward multichannel filtered-x least mean square (FFMCFxLMS) algorithm is commonly used to dynamically adjust the transfer function of the multichannel controllers

State-of-the-art attacks against cyclic logic obfuscation use satisfiability solvers that are equipped with a set of cycle-avoidance clauses. These cycle-avoidance clauses are generated in a preprocessing step and define various key combinations that could open or close cycles without making the circuit oscillating or stateful. In this article, we show that this preprocessing step has to generate cycle-avoidance

Data and information leakage is an important security concern in current systems. Several data leakage prevention (DLP) techniques have been proposed in the literature to prevent external as well as internal data leakage. Most of these solutions try to trace data flow and perform privilege checks to ensure the security of the data at the software and system level. Architecture level leakage vulnerabilities