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  • An integrated multimode battery charger in a Qi compliant wireless power receiver
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2020-01-14
    Chubin Wu, Zhang Zhang, Xin Cheng, Guangjun Xie

    In this paper, an integrated multimode battery charger in a Qi-compliant wireless power receiver is presented. The proposed wireless battery charger includes a synchronous rectifier circuit and a multi feedback low dropout regulator. The charging circuit automatically switches trickle current, constant-current, and constant-voltage mode corresponding to battery voltage. Through control of the target rectified voltage from the perspective of the wireless power receiver, the synchronous rectifier circuit can generate an adaptive rectified voltage to closely track the battery voltage, which significantly reduce the power loss in the charging circuit. The wireless battery charger was implemented with a TSMC 0.18 µm BCD 1P5M process and the experimental results show the charging current of constant-current mode is 1 A and the final voltage of the wireless battery charger is 4.2 V. The maximum efficiency of the overall system is 78%.

    更新日期:2020-01-15
  • A fully differential capacitively-coupled high CMRR low-power chopper amplifier for EEG dry electrodes
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2020-01-14
    Erwin Habibzadeh Tonekabony Shad, Marta Molinas, Trond Ytterdal

    The use of dry electrodes is increasing rapidly. Since their impedance is high, there is a high impedance node at the connecting node between the electrode and amplifier. This leads to absorb powerline signal and high CMRR amplifiers are essential to eliminate this. In this article, we propose a low-power low-noise chopper-stabilized amplifier with high CMRR. In order to minimise the input-referred noise, an inverter-based differential amplifier is utilized. Meanwhile, a DC servo loop is designed to reject the DC offset of the electrode. Since all of the stages required a common-mode feedback, for each of the amplifiers a suitable circuit was used. Furthermore, a chopping spike filter is implemented at the final stage to attenuate the choppers’ spike. Finally, to eliminate the offset effect from the mismatch and post-layout, a DC offset rejection technique is used. The designed circuit is simulated in a standard 180 nm CMOS technology. The designed chopper amplifier consumes just 1.1 \(\upmu \hbox {W}\) at a 1.2 \(\hbox {V}\) supply. The mid-band gain is 40 dB while the bandwidth is from 0.5 to 200 Hz. The total input-referred noise is 1 \(\upmu \hbox {V}_{\mathrm{rms}}\) in its bandwidth. Thus the NEF and PEF of the designed circuit is 2.7 and 9.7, respectively. In order to analyse the performance of the proposed chopper amplifier against process and mismatch variation, Monte Carlo simulation is done. According to 200 Monte Carlo simulations, CMRR and PSRR are 124 dB with 6.9 dB standard deviation and 107 dB with 7.7 standard deviation, respectively. Ultimately, the total area consumption is 0.1 \(\hbox {mm}^2\) without pads.

    更新日期:2020-01-14
  • A 12-bit 120-MS/s SAR ADC with improved split capacitive DAC and low-noise dynamic comparator
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2020-01-09
    Tian-ye Liu, Daiguo Xu, Huifang Niu, Qing Meng

    This paper presents a 12-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with improved split capacitive DAC and low-noise dynamic comparator. A split DAC structure with parasitic capacitance depressed technique is introduced, the top-plate parasitic capacitances of MSB and LSB DAC arrays are both reduced, and the accuracy of split DAC is increased without calibration. Further, an optimized sampling method is used to provide a unit capacitance between the MSB and LSB DAC arrays, the match of DAC is improved. In addition, a high-speed dynamic comparator with input-referred noise reduction technique is proposed, an extra positive feedback loop is provided to reduce the comparison delay and the gain of the comparator is also increased to depress noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 6 mW from 1.2 V power supply with a SNDR > 66.1 dB and SFDR > 81.5 dB. The proposed ADC core occupies an active area of 0.05 mm2, and the corresponding FoM is 30 fJ/conversion-step with Nyquist frequency.

    更新日期:2020-01-09
  • Compact wideband band-stop filter using stepped complementary split ring resonators
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2020-01-03
    Sathish Munirathinam, Amruth Balachandran

    Abstract The objective of this work is to achieve a compact wideband band-stop filter using complementary split ring resonators (CSRR) as the fundamental element. The relation between the geometry and resonances of the CSRR were studied analytically along with their field distribution to determine the factors governing coupling between the rings of the CSRR. The effects of the inner-outer ring orientation on resonances of the CSRR has been studied and the resulting properties have been used to design the proposed compact wideband band-stop filter prototype operating with a center frequency of 2.5 GHz and a bandwidth of 1 GHz. The area of the proposed filter is 0.078 λg2 with a fractional bandwidth of 39.76%. This structure has following advantages: more compact, wide bandwidth and occupies less area. The fabricated prototype was tested and the results were promising representing this works potential.

    更新日期:2020-01-04
  • A novel noise-coupled time-interleaved delta-sigma modulator with analysis of practical limitations
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2020-01-02
    Mahmud Abdoli, Esmaeil Najafi Aghdam, Firoz Hemmati

    Abstract An analog-to-digital converter based on the time-interleaved delta-sigma modulator is a proper method for high-speed ADCs. Time-interleaved delta-sigma modulators (TIDSM) can be successfully implemented with the development of the block digital filtering (BDF) technique. In this method, M mutually cross-connection delta-sigma modulators are used, with each one operating at a sampling rate of \({\text{f}}_{\text{s}}\) hence, the effective sampling rate will be \({\text{M}}*{\text{f}}_{\text{s}}\) However, SNDR is approximately equal to the single path standard structure. In this paper, a new structure based on the Noise Coupled time-interleaved delta-sigma modulator is proposed to increase the overall noise transfer function order without any additional active element. This improvement is analytically verified and then validated using simulations. Also, some practical issues regarding the implementation of the proposed structure, such as, finite op-amp’s gain and mismatching effects are discussed. Also, analyzes and some practical solutions are presented. The results of the simulation at the system level show that the SNDR of the proposed first-order two-channel structure is 18 dB better than its BDF technique counterpart, for the second-order two-channel TIDSM, the SNDR of the proposed structure is 13 dB better than that of the BDF technique.

    更新日期:2020-01-04
  • Enhanced test algorithm for nanoelectronic Resistive Random Access Memory testing using self check write scheme
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2020-01-01
    H. Sribhuvaneshwari, Suthendran Kannan

    Emerging nanoelectronic memories such as PCRAM, STT-RAM, Ferroelectric FET Memory and Resistive Random Access Memory (RRAM) are proficient to substitute the traditional memory technologies such as SRAMs, DRAMs and flash memory in future computers. Among all these nanoelectronic memories RRAM (combines the merits of both RAM and Flash memories) is exceptionally fast, cost-effective which is capable of accomplishing the requirements of immense growth in data and storage. Despite the fact that it suffers by various faults, more specifically Write Disturbance Fault (WDF) and Read Disturbance Fault (RDF) has huge effect on system performance and reliability. Different algorithms are designed to identify specific kind of faults and the main drawback of all existing algorithm is redundancy (repeated March elements with write and read operations) it will increase the test complexity and time. Moreover, this repeated write and read operation will leads to endurance degradation. To circumvent this pitfall, a self-checking write circuit is adapted where the accuracy of every write operation is verified at the end of write cycle by means of a write verification signal in the write circuit (acts as in built read circuit). Hence, this self checking write method offers a combined “write and read” operation (wr) that detects the faulty write operation (main reason for read fault) and avoids the data corruption in memory system. To the best of our knowledge, we are the first one to propose March algorithm with “wr” element hence it is named as novel ‘March WR’ testing algorithm which detects WDF and RDF effectively with 4n test complexity which is very less than all other existing test algorithms. Thus it reduces 63.63% of the test time. Due to keen monitoring of each operation 100% fault coverage is achieved that results in enhanced performance and reliability.

    更新日期:2020-01-04
  • Two wide-tuning-range mm-wave VCOs with SCTL and SCCPW in 45 nm SOI CMOS for 5G applications
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2019-12-24
    Hui Yang, Tianye He, Rumeng Wang, Runxi Zhang, Chunqi Shi

    Abstract A switched coupled transmission line (SCTL) method with high Q and flexible structure is proposed for mm-wave VCO to improve tuning range (TR), meanwhile maintaining low phase noise, low power dissipation and zero additional area. This TR extension method is also proved effective in a switched coupled coplanar waveguide (SCCPW) VCO. Fabricated in 45 nm SOI CMOS, the SCTL-VCO achieves 38.74% TR from 39.46 to 58.42 GHz, increased by 29.2% compared to the reference TL-VCO. The SCCPW-VCO achieves 38.83% TR from 38.69 to 57.33 GHz, increased by 31.9% compared to the reference CPW-VCO. The measured phase noise of SCTL-VCO and SCCPW-VCO over the entire frequency tuning range is from \(-\) 106 to \(-\) 116.8 and \(-\) 106.1 to \(-\) 116 dBc/Hz at 10 MHz offset, while the corresponding FOM\(_T\) is from \(-\) 181.7 to \(-\) 192.5 and \(-\) 181.6 to \(-\) 191.5 dBc/Hz, respectively. Each VCO dissipates 8.6–10.8 mW from 0.7 V power supply.

    更新日期:2020-01-04
  • A VDTA-based robust electronically tunable memristor emulator circuit
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2019-12-23
    Indrajit Pal, Vikash Kumar, Nilay Aishwarya, Abhijeet Nayak, Aminul Islam

    In this paper, a fully-integrated tunable grounded memristor emulator circuit based on voltage differencing transconductance amplifier (VDTA) has been proposed. The proposed memristor emulator circuit utilizes two VDTA active building blocks, two grounded resistors, a grounded capacitor and a four-quadrant analog multiplier. The working concept along with the detailed derivation of the mathematical model of the circuit has been discussed numerically and analytically to validate the operation of the proposed emulator. The operations of the proposed emulator circuit, as governed by the established model, have been verified by performing simulations in Cadence Virtuoso at 45 nm technology node. Robustness analyses performed, reveal significant process-variation tolerance at deep sub-micron technology node.

    更新日期:2020-01-04
  • CMOS integrated delay chain for X-Ku band applications
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2019-12-20
    Mohammad Hossein Ghazizadeh, Fateme Daryabari, Ali Medi

    A wideband integrated delay chain chip with 5-bit delay control, maximum delay of 120 ps and 3.9 ps delay resolution, designed and fabricated in 0.18 \(\upmu \hbox {m}\) CMOS technology is presented. Second-order all pass networks (APN) are used as delay structures in this delay circuit. In the design of the two MSB bits of the fabricated chip, a new design approach is used which allows higher group delay to be achieved with fewer number of passive second-order APN circuits. This would in turn reduce insertion loss of the designed delay control chain. Measurement results of the fabricated delay chain show 12.6–20.5 dB insertion loss and less than 3.3 ps RMS delay error over the intended frequency band from 8 to 18 GHz. The fabricated chip occupies an area of \(1.2\times 2.7\) mm\(^{2}\) and has no DC power consumption.

    更新日期:2020-01-04
  • 2nd-Order shaping technique of the DAC mismatch error in noise shaping SAR ADCs
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2019-12-16
    Peng Wang, Jie Sun

    Abstract A switching scheme to realize 2nd-order digital-to-analog converter (DAC) mismatch error shaping (MES) technique in the high-resolution noise shaping successive approximation register analogue-to-digital converters (NS SAR ADCs) is proposed. By feeding back the combination of the least significant bit (LSB) DAC mismatch errors in two previous cycles, the DAC mismatch error is 2nd-order shaped. The scheme only requires an extra reference voltage and triples LSB DAC, which leads to simple control logic. According to the simulation, the spurious-free dynamic range is improved 10 dB more than the 1st-order MES.

    更新日期:2020-01-04
  • Efficient design of QCA based hybrid multiplier using clock zone based crossover
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2019-12-16
    K. Pandiammal, D. Meganathan

    Abstract Quantum-dot cellular automata (QCA) is an emerging trend in nanotechnology and appropriate for the development of high performance and low power integrated circuit design. Dadda and Wallace tree multipliers are designed by employing CZBCO technique to overcome the crossover issues of geometric design complexity and alignment accuracy and also to achieve high device density. The proposed design of QCA-based Hybrid parallel multiplier consists of decomposing structure that adopts Dadda and Wallace algorithms to optimize the design. In this proposal, N-bit multiplier array is decomposed into four N/2-bit multiplier arrays that are easily constructed by employing both Wallace and Dadda multipliers. The Hybrid multiplier comprising dadda and Wallace tree multiplier uses less number of majority gates and inverters and hence minimizes area, cell count and delay. It has been observed that the QCA cost function of the proposed multiplier better than existing multiplier referred in the literature in terms of energy and speed. Furthermore, the proposed multiplier significantly achieves high device density, lessened clock delay, area and cell count and also to eliminate fabrication difficulty of crossover.

    更新日期:2020-01-04
  • Design, FPGA implementation and statistical analysis of chaos-ring based dual entropy core true random number generator
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2019-12-14
    İsmail Koyuncu, Murat Tuna, İhsan Pehlivan, Can Bülent Fidan, Murat Alçın

    In this paper, a novel chaos-ring based dual entropy core TRNG architecture on FPGA with high operating frequency and high throughput has been performed and presented. The design of dual entropy core TRNG has been generated by uniting the chaotic system-based RNG and the RO-based RNG structures on FPGA. The chaotic oscillator structure as the basic entropy source has been implemented in VHDL using Euler numerical algorithm in 32-bit IQ-Math fixed point number standart on FPGA. The designed chaotic oscillator has been synthesized for the FPGA chip and the statistics related to chip resource consumption and clock frequencies of the units have been presented. The RO-based RNG structure has been designed as the second entropy source. Chaos-ring based dual entropy core novel TRNG unit have been created by combining of these two FPGA-based structures in the XOR function used at the post processing unit. The throughput of the designed dual entropy core TRNG unit ranges 464 Mbps. The output bit streams obtained from FPGA-based novel TRNG have been subjected to NIST 800-22 test suites.

    更新日期:2020-01-04
  • Designing programmable current-mode Gaussian and bell-shaped membership function
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2019-12-09
    S. M. Azimi, H. Miar-Naimi

    Abstract In this paper, a procedure is proposed to implement a novel and effective Gaussian-shaped and Bell-shaped membership function. The circuit is designed in a current mode. Therefore, the power consumption has been decreased. Higher power supply rejection ratio is also achieved by the use of a differential structure. The most important aims are to design simple, accurate and low power consumption circuits. The proposed circuit operates in the saturation region. Therefore, high-accuracy, as well as the high-speed performance and independency to the temperature variations, are obtained. Programmability, power consumption and parameters variations of the proposed circuit are also presented. The simulations are done in 0.18 µm CMOS technology.

    更新日期:2020-01-04
  • Improved phase aware speech enhancement using bio-inspired and ANN techniques
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2019-12-07
    Tusar Kanti Dash, Sandeep Singh Solanki, Ganapati Panda

    The phase modification of noisy speech signal plays a crucial role in speech enhancement (SE). In the recent past, many speech denoising algorithms have been proposed using the modification of phase information which depends on the scaling factor computed from the noise level. The performance measures of SE is significantly affected by this scaling factor and noise level estimation. However, in these algorithms, the parameters are not optimally tuned for the different noise conditions and also in some cases, the background noise is presumed to be stationary. Further, no earlier attempt has been made to obtain adaptive models which can establish the relationship between noise levels and scaling factor. Being motivated by these observations an attempt has been made in this paper to develop a neural network based model which is capable of properly estimating this scaling factor from the noise level. In the current work, a popular and efficient bio-inspired technique known as firefly algorithm is employed to determine the best possible scaling factor for each noise level. In addition, a relationship is established between noise level and scaling factor using trigonometric functional expansion based artificial neural network. An effective nonstationary noise estimation strategy is also incorporated in the proposed algorithm. Simulation-based experiments are performed to evaluate the effectiveness of the proposed SE algorithm and compared with other six standard SE algorithms using standard database. The analysis of the simulation results demonstrates that the proposed method outperforms the others in terms of both subjective and objective evaluation measures.

    更新日期:2020-01-04
  • Less complex solutions for active noise control of impulsive noise
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2019-12-05
    Alina Mirza, Ayesha Zeb, Mir Yasir Umair, Danish Ilyas, Shahzad Amin Sheikh

    Abstract All adaptive algorithms suffer stability issues when employed for the impulsive noise control under the domain of active noise control (ANC) systems. There is a dire need of investigations to overcome this limitation for the impulsive noise, a robust adaptive algorithm is proposed in literature. In the first part of paper, this robust adaptive algorithm is tested for the first time under ANC environment for impulsive noise cancellation and thus, a new ANC algorithm named filtered-x least cosine hyperbolic (FxLCH) algorithm is presented. Simulations are carried out to validate the improved performance of proposed FxLCH algorithm where the impulsive noise realizations are generated by symmetric α-stable distributions. Moreover, the proposed solutions perform better than the standard filtered-x least mean square (FxLMS) algorithm including its variants, and it shows better stability and converges faster than its competitors. Robustness of the algorithm is a constraint in the presence of high impulsive noise. To overcome this problem and to enhance the robustness of proposed FxLCH algorithm, two modifications are suggested. First proposed modification clips the reference and error signals (CFxLCH algorithm), while the second modification integrates already reported normalized step size with FxLCH (MFxLCH) algorithm. The performance of suggested MFxLCH algorithm is validated by extensive simulations. The results exhibited that MFxLCH algorithm acts as a trade-off between FxLMS and filtered-x recursive least square (FxRLS) family algorithms. It has shown better convergence speed than that of FxLMS family algorithms and can approach steady state error as of FxRLS family with almost same computational complexity as of FxLMS family algorithms.

    更新日期:2020-01-04
  • Fuzzy controller based design of 125 level asymmetric cascaded multilevel inverter for power quality improvement
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2019-06-19
    C. Dhanamjayulu, S. Meikandasivam

    This paper implements a 125 level asymmetric cascaded multilevel inverter using fuzzy logic which is used in the dynamic voltage restorer. The inverter is designed with a reduced number of switches. The higher switching frequency is defined for the better performance of the multilevel inverter. The 125 level output is obtained in this proposed approach with only twelve switches and six voltage sources. By changing the switching frequency, the proposed output voltage level is obtained in the inverter. The paper is organized into two phases. In the first step the design of 125 level inverter is proposed, and in the second phase, the power quality improvement using the designed inverter is discussed. The proposed design of an inverter is implemented for dynamic voltage restorer solves the power quality problems such as are voltage sag, voltage swell, and harmonics. The power quality issue mitigation performance is increased with the proposed 125 level inverter. The enrichment of the proposed design is investigated using the comparison of existing works. The proposed work is implemented in the Matlab/Simulink environment.

    更新日期:2020-01-04
  • A modified Dickson’s charge pump circuit with high output voltage and high pumping efficiency
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2019-09-05
    Liang Zhang, Xu Cheng, Xianjin Deng

    A modified Dickson’s charge pump circuit with high output voltage and high pumping efficiency fabricated by IHP’s 130 nm SiGe BiCMOS process is proposed. Instead of traditional on-chip metal–insulator–metal capacitor, a modified vertical parallel plate capacitor is utilized as the pumping capacitor, which owns a breakdown voltage higher than 84 V and an improved capacitance density of 1.92 fF/μm2. Thus, the output voltage and chip size of charge pump circuit are not limited by the pumping capacitor. To further improve the voltage pumping efficiency and make the circuit suitable for low voltage operation, the threshold voltage and the body effect coefficient is eliminated by using a dynamic control to both the charge transfer switches and the MOSFETs body voltages. Simulated result of a 35-stage charge pump circuit with an output voltage higher than 100 V is demonstrated. A 7-stage charge pump circuit with an output voltage of 13.8 V and a pumping efficiency of 75%, higher than the traditional Dickson’s charge pump circuits, is fabricated and measured.

    更新日期:2020-01-04
  • Reversals of period doubling, coexisting multiple attractors, and offset boosting in a novel memristive diode bridge-based hyperjerk circuit
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2018-12-03
    Jacques Kengne, Gervais Dolvis Leutcho, Adélaïde Nicole Kengnou Telem

    Abstract In this paper, a new memristive diode bridge-based RC hyperjerk circuit is proposed. This new memristive hyperjerk oscillator (MHO) is obtained from the autonomous 4-D hyperjerk circuit (Leutcho et al. in Chaos Solitons Fractals 107:67–87, 2018) by replacing the nonlinear component (formed by two antiparallel diodes) with a first order memristive diode bridge. The circuit is described by a fifth-order continuous time autonomous (‘elegant’) hyperjerk system with smooth nonlinearities. The dynamics of the system is investigated in terms of equilibrium points and stability, phase portraits, bifurcation diagrams and two-parameter Lyapunov exponents diagrams. The numerical analysis of the model reveals interesting behaviors such as period-doubling, chaos, offset boosting, symmetry recovering crisis, antimonotonicity (i.e. concurrent creation and destruction of periodic orbits) and several coexisting bifurcations as well. One of the most attractive features of the new MHO considered in this work is the presence of several coexisting attractors (e.g. coexistence of two, three, four, five, six, seven, or nine attractors) for some suitable sets of system parameters, depending on the choice of initial conditions. Accordingly, the distribution of initial conditions related to each coexisting attractor is computed to highlight different basins of attraction. Laboratory experimental measurements are carried out to verify the theoretical analysis.

    更新日期:2020-01-04
  • An autonomous chaotic and hyperchaotic oscillator using OTRA
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2019-02-04
    Manoj Joshi, Ashish Ranjan

    Abstract This research paper reports a novel design for third order chaotic and hyperchaotic oscillator with cubic nonlinearity using single operational trans-resistance amplifier (OTRA) and few passive elements. The key nonlinear dynamical characteristics in terms of sensitivity, divergence, equilibrium point and Lyapunov exponent are recorded in this literature. The operational activity of the proposed oscillator based on OTRA is integrated using 0.25 µm TSMC CMOS parameter. For the generation of hyperchaotic oscillator, an external capacitor is added to the third order chaotic oscillator. To justify the theoretical nonlinear dynamics of proposed chaotic oscillator, PSPICE simulation by using CMOS based OTRA and experimental investigation using IC AD844 based OTRA are well implemented.

    更新日期:2020-01-04
  • Effect of jitter on the settling time of mesochronous clock retiming circuits
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2018-10-15
    Naveen Kadayinti, Amitalok J. Budkuley, Maryam S. Baghini, Dinesh K. Sharma

    Abstract It is well known that timing jitter can degrade the bit error rate of receivers that recover the clock from input data. However, timing jitter can also result in an indefinite increase in the settling time of clock recovery circuits, particularly in low swing mesochronous systems. Mesochronous clock retiming circuits are required in repeaterless low swing on-chip interconnects. We first discuss how timing jitter can result in a large increase in the settling time of the clock recovery circuit. Next, the circuit is modelled as a Markov chain with absorbing states. The mean time to absorption of the Markov chain, which represents the mean settling time of the circuit, is determined. The model is validated through behavioural simulations of the circuit, the results of which match well with the model predictions. We consider circuits with (1) data dependent jitter, (2) random jitter, and (3) combination of both of them. We show that a mismatch between the strengths of up and down corrections of the retiming can reduce the settling time. In particular, a 10% mismatch can reduce the mean settling time by up to 40%. We leverage this fact toward improving the settling time performance, and propose useful techniques based on biased training sequences and mismatched charge pumps. We also present a coarse+fine clock retiming circuit, which can operate in coarse first mode, to reduce the settling time substantially. These fast settling retiming circuits are verified with circuit simulations.

    更新日期:2020-01-04
  • A 10 Gb/s noise-canceled transimpedance amplifier for optical communication receivers
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2019-10-14
    Seyed Ruhallah Qasemi, Maryam Rafati, Parviz Amiri

    This study presents a noise-canceled transimpedance amplifier (TIA) for optical receivers. The proposed structure consists of a shunt feedback common source amplifier as an input stage followed by two regulated cascodes (RGC) and finally a differential to the single-ended amplifier at the output stage. By exploiting the noise-canceling technique at the input stage, 31.8% of the total output noise is canceled. In addition, the auxiliary path’s RGC circuit, as it has a low input impedance, is utilized to cancel out the photodiode (PD) large parasitic capacitance at the input stage. The proposed TIA along with post amplifiers, including packaging components, are simulated in TSMC 90 nm RF CMOS technology at the post-layout level. The TIA average input-referred current noise is equal to \(9.5\;{\text{pA}}/\sqrt {\text{Hz}}\). The PD capacitance is considered as 325 fF for all simulations. The transimpedance gain is equal to 60 dBΩ and the 3-dB bandwidth is equal to 7 GHz. The power consumption of the proposed TIA is 3.6 mW from a 1.2 V supply voltage. The TIA occupies a chip area of 0.036 mm2.

    更新日期:2020-01-04
  • A peak efficiency tracking technique to improve the efficiency of switched capacitor DC–DC converters
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2019-07-26
    Stefano D’Amico, Carlo Veri, Giuseppe Tau, Mirko Pasca

    In this paper, a peak efficiency tracking technique to improve the efficiency of switched capacitor (SC) DC–DC converters as the load varies is presented. A peak efficiency tracking circuit based on feedback control over the switching frequency is implemented for this scope. The basic idea of the proposed technique is to adjust the switching frequency according to the load. The technique is successfully implemented in a SC DC–DC converter to be embedded in detector pixels for the Large Hadron Collider (LHC) experiment at the Conseil Européen pour la Recherche Nucléaire (CERN) of Geneve. It is realized in 65 nm bulk CMOS technology with an occupied area of 1.31 mm2. This converter provides an 800 mV output voltage from a 1.2 V supply. The load of the DC–DC converters is modeled as a resistor, RLOAD, that has 4 Ω nominal value but it can range from 2.67 up to 10 Ω. At 10 Ω RLOAD, a 6% efficiency improvement is reached with respect to the typical approach consisting in keeping constant the switching frequency at the optimum value for RLOAD nominal value.

    更新日期:2020-01-04
  • Optimization and development of the RF MEMS structures for low voltage, high isolation and low stress
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2019-10-12
    Hamid Reza Ansari, Mojtaba Behnam Taghaddosi

    Abstract MEMS capacitive switches have longer lifetimes compared to other types of metal-to-metal switches, and when placed on the membrane on the transmission line, they can easily return to the up-state due to a dielectric layer. They also transmit the input signal with more power and frequency and therefore, they are better than metal-to-metal switches. In this paper, first three switches were considered as the basic structures. Then, in order to demonstrate the credibility and high quality of the simulations, the same switches were simulated. The obtained results are very close to the results of fabrication of these switches. In the next step, with the presentation of three new structures, stimulation voltage, stress, switching time and isolation were improved in four steps. The mechanical simulation of the switch was performed to determine the amount of displacement, the amount of stress and the resonant frequency using the COMSOL software. In addition, electrical simulation of the switch was performed to obtain the S-parameter using the HFSS software. The simulation results demonstrate that the isolation is 57–66 dB and the insertion loss is 0.3–2 dB in the desired frequency band (1–50 GHz). Using new spring structures, the actuation voltage was reduced from 4.8 V in basic structures (the smallest in three structures) to 2.4 V in new structures, which is considered excellent. In order to increase the lifetime of the switch, the stress in the new switches is reduced from 12 to 4.5 MPa compared to the basic switches.

    更新日期:2020-01-04
  • A 13-bit Noise Shaping SAR-ADC with Dual-Polarity Digital Calibration.
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2013-05-18
    Hangue Park,Maysam Ghovanloo

    We present a new noise shaping method and a dual polarity calibration technique suited for successive approximation register type analog to digital converters (SAR-ADC). Noise is pushed to higher frequencies with the noise shaping by adding a switched capacitor. The SAR capacitor array mismatch has been compensated by the dual-polarity digital calibration with minimum circuit overhead. A proof-of-concept prototype SAR-ADC using the proposed techniques has been fabricated in a 0.5-μm standard CMOS technology. It achieves 67.7 dB SNDR at 62.5 kHz sampling frequency, while consuming 38.3μW power with 1.8 V supply.

    更新日期:2019-11-01
  • A Low-Power Thermal-Based Sensor System for Low Air Flow Detection.
    Analog Integr. Circ. Signal Process. (IF 0.823) Pub Date : 2017-04-25
    Akm Arifuzzman,Mohammad Rafiqul Haider,David B Allison

    Being able to rapidly detect a low air flow rate with high accuracy is essential for various applications in the automotive and biomedical industries. We have developed a thermal-based low air flow sensor with a low-power sensor readout for biomedical applications. The thermal-based air flow sensor comprises a heater and three pairs of temperature sensors that sense temperature differences due to laminar air flow. The thermal-based flow sensor was designed and simulated by using laminar flow, heat transfer in solids and fluids physics in COMSOL MultiPhysics software. The proposed sensor can detect air flow as low as 0.0064 m/sec. The readout circuit is based on a current- controlled ring oscillator in which the output frequency of the ring oscillator is proportional to the temperature differences of the sensors. The entire readout circuit was designed and simulated by using a 130-nm standard CMOS process. The sensor circuit features a small area and low-power consumption of about 22.6 µW with an 800 mV power supply. In the simulation, the output frequency of the ring oscillator and the change in thermistor resistance showed a high linearity with an R2 value of 0.9987. The low-power dissipation, high linearity and small dimensions of the proposed flow sensor and circuit make the system highly suitable for biomedical applications.

    更新日期:2019-11-01
Contents have been reproduced by permission of the publishers.
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