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Model and design of an efficient controller for microgrid connected HRES system with integrated DC–DC converters: ATLA-GBDT approach Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-03-12 Kamaraju Vechalapu, Chintapalli V. V. S. Bhaskara Reddy
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An improved blind Gaussian source separation approach based on generalized Jaccard similarity Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-03-05
Abstract Blind source separation (BSS) consists of recovering the independent source signals from their linear mixtures with unknown mixing channel. The existing BSS approaches rely on the fundamental assumption: the number of Gaussian source signals is no more than one, this limited the use of BSS seriously. To overcome this problem and the weakness of cosine index in measuring the dynamic similarity
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An optimization approach control of EV solar charging system with step-up DC–DC converter Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-28 R. J. Venkatesh, R. Priya, P. Hemachandu, Chinthalacheruvu Venkata Krishna Reddy
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Design and analysis of a low phase noise, wide tunable CMOS based low power VCO with active inductor Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-28 Isha Kadyan, Manoj Kumar
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Novel high-gain narrowband antenna based on ENZ SIW structure and shorting pin Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-26
Abstract This paper provides an idea for designing a high-gain narrow-band substrate integrated waveguide (SIW) antenna. The high gain is achieved due to the epsilon-near-zero (ENZ) technique, and narrow-band performance is achieved due to impedance matching provided by a pair of symmetric shorting pins. In this paper, SIW is used near its cut-off frequency to realize the ENZ characteristics. Further
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A novel wide-band, small size and high gain patch antenna array for 5G mm-wave applications using adaptive neuro-fuzzy inference system Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-25 Lahcen Sellak, Samira Chabaa, Saida Ibnyaich, Lahcen Aguni, Ahmad Sarosh, Abdelouhab Zeroual, Atmane Baddou
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Scalable intelligent median filter core with adaptive impulse detector Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-25
Abstract This paper introduces a reconfigurable AI-enabled scalable median filter with an adaptive impulse detector designed for FPGA-based real-time imaging systems. Its primary objective is to address the degradation of image quality caused by mixed impulsive noise during real-time image transmission and reception. Existing median filters often struggle to provide real-time image processing results
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An 80–84.8 GHz PLL with auto-tracking Miller divider for FMCW applications Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-24 Popong Effendrik, Wei-Zen Chen
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A 4-D four-wing chaotic system with widely chaotic regions and multiple transient transitions Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-23 Lingyun Li, Zhijun Chai, Yunxia Wang
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Chip implementation of low-power high-efficient buck converter for battery-powered IOT applications Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-22 Shih-Chang Hsia, Ming-Ju Hsieh
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Thermally-aware circuit model and performance analysis of MLGNR for nano-interconnect application Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-21 Himanshu Sharma, Karmjit Singh Sandha
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Integration of cascaded controllers for super-lift Luo converter with buck converter in solar photovoltaic and electric vehicle Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-20 B. Ashok, Prawin Angel Michael
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A floating meminductor emulator using modified differential voltage current conveyor transconductance amplifier and its application Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-20
Abstract In this paper, a modified differential voltage current conveyor transconductance amplifier (MDVCCTA) based meminductor emulator has been proposed. The proposed meminductor is realized using one MDVCCTA, one resistor, and two grounded capacitors that leads to a very simple configuration. The emulator is working for a significant range of frequencies up to 80 MHz. The transient and non-volatility
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Signal dynamic range expansion and power supply voltage reduction for an exponentiation conversion IC Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-19
Abstract In order to compensate for the non-linearity of an electronic device, an exponentiation conversion circuit that can change the power exponent to any value has been proposed. The exponentiation conversion circuit multiplies the logarithmically converted input signal by a power exponent value to perform exponential conversion. As a result, we can obtain the power function characteristic of a
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Experimental Investigation on the Side Mode Injection Locking of a Single-loop OEO under RF Signal Injection Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-18 Jayjeet Sarkar, Abhijit Banerjee, Gefeson Mendes Pacheco, Nikhil Ranjan Das
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Estimation of polarization diversity in CPW fed compact dual band dual sense antenna with horn slot structure: 5G and WLAN applications Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-12 Krishna Chennakesava Rao Madaka, Pachiyannan Muthusamy
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A design approach for class-AB operational amplifier using the gm/ID methodology Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-11 Chen Chen, Jinxing Cheng, Hongyi Wang, Youyou Fan, Kaikai Wu, Tao Tao, Qingbo Wang, Ai Yu, Weiwei Wen, Youpeng Wu, Yue Zhang
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A bidirectional four-port DC–DC converter for grid connected and isolated loads of hybrid renewable energy system using hybrid approach Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-10
Abstract Most four-port converters typically enable bidirectional power flow through the low-voltage side battery port, which is used to discharge to the high-voltage side DC-link and charge from energy sources. However, system-level power management is restricted by the DC-link’s absence of bidirectional power transmission. This manuscript proposes a hybrid approach utilizing a four-port DC–DC converter
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Design of area-speed efficient Anurupyena Vedic multiplier for deep learning applications Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-09
Abstract Hardware such as multipliers and dividers is necessary for all electronic systems. This paper explores Vedic mathematics techniques for high-speed and low-area multiplication. In the study of multiplication algorithms, various bits-width ranges of the Anurupyena sutra are used. Parallelism is employed to address challenging problems in recent studies. Various designs have been developed for
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Electromagnetic coupling suppression of circularly polarized mimo antenna with novel loop parasitic for UWB communication Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-08 Muhammad Irshad Khan, Shaobin Liu, Saeed Ur Rahman, Muhammad Kabir Khan, Muhammad Sajjad, Abdul Basit, Jianliang Mao, Amil Daraz
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Design an energy efficient pulse triggered ternary flip flops with Pseudo NCFET logic Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-06 Sudha Vani Yamani, M. V. S. RamPrasad, Gundala Dinesh, Eegala Yamini Yeshaswila, Chelluri Ravi Teja, Botta Lokesh
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An all-digital low-power, low-frequency GRO-based time to digital converter for biomedical applications Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-06 Elnaz Zafarkhah, Maryam Zare, Nima S. Anzabi-Nezhad, Zahra Sohrabi
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A phase noise filter for RF oscillators Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-05
Abstract In this work, a phase noise reduction architecture for standalone oscillators is presented. The oscillator phase is divided and a voltage is generated by a type-I phase detector, which is compared with an ideal voltage to change the phase of the oscillator. Analysis shows that the loop parameters aid in phase noise suppression. The design is done in CMOS 90 nm technology for a 1 GHz ring oscillator
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A 12.5 Gb/s 1.38 mW all-inverter-based optical receiver with multi-stage feedback TIA and continuous-time linear equalizer Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-03 Peng Yan, Chaerin Hong, Po-Hsuan Chang, Hyungryul Kang, Dedeepya Annabattuni, Ankur Kumar, Yang-Hang Fan, Ruida Liu, Ramy Rady, Samuel Palermo
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Frequency reconfigurable antenna array modelling based on MoM-GEC method for RFID, WiMax and WLAN applications Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-02-03 Heithem Helali, Mourad Aidi, Taoufik Aguili
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Design and simulation of a new current mirror circuit with low power consumption and high performance and output impedance Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-31 Yuping Li, Haihua Wang, Mohammad Trik
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An improved 1.8 V 4.05 ppm/°C curvature corrected bandgap reference circuit Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-30 Anushree, Jasdeep Kaur
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A programmable gain amplifier based on a two-level CNTFET op amp with optimized trans-conductance to drain current ratio Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-28
Abstract A cardiac biomarker (CB) is an important substance released into the blood during heart damage. CB measurements help in the detection of concentric levels in cardiac troponin I. The increased troponin level in the blood can lead to the major cause of cardiac injury. Hence it is necessary to monitor the troponin level of blood. Accurate troponin I detection sensors detect the troponin level
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A low-power 10Gb/s CMOS clock and data recovery circuit with a quarter-rate phase detector Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-25 Hamed Safari, Hassan Faraji Baghtash, Esmaeil Najafi Aghdam
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A hybrid ensemble voting-based residual attention network for motor imagery EEG Classification Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-24
Abstract Multi-class motor imagery Electroencephalography (EEG) activity decoding has always been challenging for the development of Brain Computer Interface (BCI) system. Deep learning has recently emerged as a powerful approach for BCI system development using EEG activity. However, the EEG activity analysis and classification should be robust, automated and accurate. Currently, available BCI systems
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Performance analysis of DD-DPMZM based RoF link for emerging wireless networks Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-22
Abstract This paper demonstrates the analytical approach of Linearized Radio over Fiber (RoF) link based on Dual-Drive Dual Parallel Mach Zehnder Modulator (DD-DPMZM) by properly adjusting the phase shifters and biasing of the Mach Zehnder Modulator (MZM). Two input RF Source at 7 and 8 GHz applied in the used RoF link. The proposed RoF link consists of Mach Zehnder Modulator (MZM), Parallel combination
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An 18–28 GHz dual-mode down-converter IC for 5G applications Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-21 Saeed Naghavi, Kaisa Ryynänen, Mahwish Zahra, Aleksi Korsman, Kari Stadius, Marko Kosunen, Vishnu Unnikrishnan, Lauri Anttila, Mikko Valkama, Jussi Ryynänen
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A broadband low profile SIW cavity-backed antenna loaded with hexagonal and rectangular slots for ‘X’ band application Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-18
Abstract This article manifests a straight-forward design technique to obtain a broad bandwidth for a substrate integrated waveguide (SIW) cavity-backed slot antenna suitable for ‘X’ band applications. The combination of hexagonal and rectangular slots significantly expands the bandwidth, unlike conventional slots (circle, square, and triangle). They induce two closely spaced modes in the rectangular
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DTMOS based four-quadrant multiplier/divider with voltage difference transconductance amplifier Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-17 Motkuri Krishna, Bal Chand Nagar
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A compact dual-feed wide-band slotted antenna for future wireless applications Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-12 D. Siva Sundhara Raja, D. Rajesh Kumar, N. Santhiyakumari, S. Kumarganesh, K. Martin Sagayam, B. Thiyaneswaran, Binay Kumar Pandey, Digvijay Pandey
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Low power adders using asynchronous pipelined modified low voltage MCML for signal processing and communication applications Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-11 T. KalavathiDevi, K. S. Renuka Devi, S. Umadevi, P. Sakthivel, Seokbum Ko
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Hardware optimized digital down converter for multi-standard radio receiver Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-11
Abstract This paper presents a novel approach to the reconfigurable digital down converter (DDC) reducing the sampling frequency from 3.64 GHz to 28.4375 MHz on the field-programmable gate array (FPGA) device. The proposed DDC consists of a polyphase mixer and a resampling filter. The polyphase mixer can reduce the high-speed sampling rate signal and generates a complex baseband signal having sufficient
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A novel intelligent optimization-based maximum power point tracking control of photovoltaic system under partial shading conditions Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-10 Mary Beula Aron, Josephine Rathinadurai Louis
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Memristive discrete chaotic neural network and its application in associative memory Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-09 Fang Zhiyuan, Liang Yan, Wang Guangyi, Gu Yana
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A low power arithmetic unit driven motion estimation and intra prediction accelerators with adaptive Golomb–Rice entropy encoder for H.264 encoders on FPGA Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-05 L. Vigneash, H. Azath, Lakshmi R. Nair, Kamalraj Subramaniam
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Design and simulation of assorted functional QQCA circuits Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-04 Alireza Navidi, Milad Khani, Reza Sabbaghi-Nadooshan
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Spectral efficiency of hybrid precoding and combining design for mm-Wave multi-user massive MIMO systems Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-04 Krupali Umaria, Shweta Shah
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A fractional order HP memristive system with a line of equilibria, its bifurcation analysis, circuit simulation and ARM-FPGA-based implementation Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2024-01-03 Tantoh Bitomo Francis Richard, Kammogne Soup Tewa Alain, Sundarapandian Vaidyanathan, Daniel Clemente-Lopez, Jesus M. Munoz-Pacheco, Siewe Siewe Martin
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A non-isolated high step-up converter with TID controller for solar photovoltaic integrated with EV Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2023-12-31 B. Ashok, Prawin Angel Michael
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Power reduction using Unified techniques in Switch-tail Ring counter for sequential circuits Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2023-12-30 L. Angel Prabha, N. Ramadass
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Design a novel 1-bit full adder with hybrid logic for full-swing, area-efficiency and high-speed Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2023-12-29 A. Arul, M. Kathirvelu
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A high-speed MCML charge pump design at 10 GHz frequency in 45 nm CMOS technology for PLL application Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2023-12-29 M. Sivasakthi, P. Radhika
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Quad broadband circularly polarized CPW FED cleaver shaped extended UWB MIMO antenna for 5G,C, K and millimeter wave applications Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2023-12-28 Ravi Mali, Deepshikha Lodhi, Sarthak Singhal
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Design and implementation of high-performance 20-T hybrid full adder circuit Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2023-12-27 Jyoti Kandpal, Abhishek Tomar
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A high-precision frequency measurement method combining π-type delay chain and different frequency phase coincidence detection Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2023-12-26
Abstract A high-precision frequency measurement method combining π-type delay chain and different frequency phase coincidence detection is proposed based on different frequency phase comparison. A delay chain is used to delay the frequency standard signal. The coarse delay can generate more phase coincidence points at the key position of the reference gate, which can easily form a high-precision actual
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A novel reversible gate and optimised implementation of half adder, subtractor and 2-bit multiplier Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2023-12-24 Siddhesh Soyane, Ajay Kumar Kushwaha, Dhiraj Manohar Dhane
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Design and modeling of film bulk acoustic resonator considering temperature compensation for 5G communication Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2023-12-21 Xiushan Wu, Lin Xu, Ge Shi, Xiaowei Zhou, Jianping Cai
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Realization of a pseudo-random number generator utilizing two coupled Izhikevich neurons on an FPGA platform Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2023-12-20 Mohammad Saeed Feali
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Design of a delay locked loop with low power and high operating frequency range characteristics in 180-nm CMOS process Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2023-12-19 Fatemeh Esmaili Saraji, Alireza Ghorbani, Seyed Mahmoud Anisheh
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A novel memristor-based method to compute eigenpairs Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2023-12-19
Abstract Although digital processors offer high computing accuracy, they suffer enormously from lengthy execution times and high energy consumption as a result of the numerous communications between the processors and storage units. The disadvantage is especially acute when performing data-intensive operations, such as deep neural networks and matrix operations. To address this, several novel ideas
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A floating memristor emulator for analog and digital applications with experimental results Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2023-12-19
Abstract This paper presented a flux controlled memristor using the most versatile analog block, a single Operational Amplifier (Op-Amp), an N-channel metal–oxide–semiconductor field-effect transistor (MOSFET), and four passive elements. The following benefits are offered by the suggested memristor design: (1) a lesser number of active and passive elements; (2) floating nature of the circuit; (3) wide-operating
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Hard-disk drive read-channel design trade-offs for areal densities beyond 2 Tb/in2 Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2023-12-18 Tertulien Ndjountche
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Energy efficient enhanced all pass transformation fostered variable digital filter design based on approximate adder and approximate multiplier for eradicating sensor nodes noise Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2023-12-17 M. Ramkumar Raja, R. Naveen, C. Anand Deva Durai, Mohammed Usman, Neeraj Kumar Shukla, Mohammed Abdul Muqeet
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Design of a CMOS based ring VCO using particle swarm optimisation Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2023-12-16 Aditya Raj, Saikat Majumder, Guru Prasad Mishra
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Low voltage high bandwidth FVF current mirror using quasi floating self-cascode output stage Analog Integr. Circ. Signal Process. (IF 1.4) Pub Date : 2023-12-16
Abstract Current mirrors with ideal performance are widely in demand for realizing low power applications. In this paper, an FVF current mirror is proposed to have high bandwidth, low input, and boosted output resistance. The low voltage operation is confirmed using flipped voltage follower at the input. Also at the input, a local negative feedback loop is created which reduces the input node resistance