This study presents the algebraic cryptanalysis of a continuous-time chaotic random number generator (RNG) based on a Zhongtang chaotic system. The chaos-based RNG provides key values for logic encryption, round key formation and the substitution box (S-box) generation steps in AES (advanced encryption standard). In this study, an attack method is proposed to exploit the weaknesses of the chaos-based

A technique to extract statistical model parameters for skewed Gaussian process variations is proposed. Statistical compact model extraction traditionally assumes that underlying process variations are Gaussian in nature. ON currents in certain high voltage technologies, which are linear in process deviations, show skew in their distribution and hence is indicative of skew in the underlying process

Here, the critical path of ripple carry adder (RCA)-based binary tree adder (BTA) is analysed to find the possibilities for delay minimisation. Based on the findings of the analysis, the new logic formulation and the corresponding design of RCA are proposed for the BTA. The comparison result shows that the proposed RCA design offers better efficiency in terms of area, delay and energy than the existing

Quantum-dot cellular automata (QCA) is a novel nanodevice that implements logic circuits at the nanoscale. Information encryption is a key issue in nanocommunications. This article proposes a new method ‘select, cross, variation’ (SCV) for data encryption. This work also implements the QCA layout of this method for the first time. The QCA-based SCV circuit uses 71 cells. The circuit is composed of

This work presents an analogue equaliser with digital tuning. It compensates the losses introduced by up to 120 m long category 5 unshielded twisted pair cables and baseline wander (BLW). The equaliser is designed for Fast Ethernet with a symbol rate of 125 MHz. A g m -C filter, based on three first-order high pass filters, is used to compensate the cable loss. To minimise power consumption, three

Alternate testing techniques have been progressively adopted as a promising solution due to their effectiveness against classical specification-based test methods. This work presents a built-in test system, which adaptively generates an indirect digital signature characterising the circuit under test, which is later used to diagnose the actual performances relying on a statistical dictionary-based

This study proposes vertical sidewall implantation for noise reduction of CMOS image sensor pixel employing a vertical transfer gate (VTG). The pixel performance is evaluated by 3D device-level simulation. It is concluded that the proposed pixel's output is less sensitive to interface traps compared to similar previous work. In previous back-side-illuminated shared VTG pixel, which lacks the sidewall

Quantum cellular automata (QCA) enables performing logic operations at the sub-nm scale. The clock field provides energy gain in QCA circuits, and the energy is dissipated while data flow from inputs to outputs during clock time slots. The authors start from a quantum mechanical model and end in a simple electrostatic model for energy calculation of molecular QCA systems, where the cells are fully

The design of a 4-bit encoder with a bubble error correction of first order is described in this study. Since encoder restricts speed of the flash analogue-to-digital converter (ADC), therefore, an improved and faster encoder is an essential requirement to push its limits. Encoder is divided into two parts: one-hot code generator [or bubble error corrector (BEC)] and binary encoder. Binary encoder

Differential power analysis (DPA) has become an efficient side channel attack that obtains a secret key from the extracted power traces. Several traditional CMOS-based DPA countermeasures resulted in high area overhead and performance degradation. This study presents low area overhead DPA countermeasure exploring tunnel field effect transistors (TFET) based random number generator (RNG). TFET exhibits

The study presents a hardware-based approach to modelling and design of time-predictable electronic embedded systems. It addresses multithread and multitask problems of contemporary real-time systems. Authors propose a universal template of the reconfigurable system architectures that can be flexibly accommodated to a given application. The synthesisable and parametrised model of the system architecture

Recent applications in terahertz imaging, spectroscopy, and communications have been driving the need to increase the operation frequency of field-effect transistors (FETs). However, beyond their cutoff, FETs where recently shown to operate as a second-order rectifier. Despite the developments in this field, the physical models for this phenomenon are mostly ideal and limited in their scope. This has

This study investigates the analogue performance of a III–V tunnelling field-effect transistor (TFET). To explore the circuit performance of the TFET, a T-shaped TFET (TTFET) structure is investigated and its performance parameters are compared with a 14 nm simulation program with integrated circuit emphasis (SPICE)-based predictive technology model FinFET. The advantages and limitations of TTFET technology

A novel systematic technological process for ZnO-thin-film transistors (TFTs) fabrication was developed which turned out to achieve near-zero threshold voltage devices with good performance and stability. A deuterium implantation method was realised as well to fabricate depletion n-type ZnO TFTs. The inverters based on enhancement/depletion ZnO TFTs reached nearly full swing (0.01–5 V at 5 V V DD )

In this study, a continuous-time delta-sigma modulator (CTDSM) is developed using a Gm-C based noise-shaping quantiser (Gm-C-NSQ) with an improved dynamic element matching (i-DEM) algorithm. Here, a Gm-C integrator is used to develop NSQ, since it increases the effectiveness of the proposed modulator in terms of power consumption and die area. This Gm-C-NSQ uses only three dynamic latches to provide

This study presents the analysis and design of reduced switching (RSw) activity mode successive approximation register (SAR) analogue-to-digital (A-to-D) algorithm. For given analogue-to-digital converter (ADC) specifications, RSw mode design is based on the observation that the signal variation in two successive samples becomes linear over a certain range of input frequencies. Hence, dispensable switching

Tunnel field effect transistors (TFETs) have been exhibiting an enticing performance to succeed in metal–oxide–semiconductor technology. However, TFET also possesses several challenges such as low drive current, ambipolarity, and requirement of abrupt doping profiles for the occurrence of band-to-band tunnelling (BTBT) conduction mechanism at the junction. To overcome these challenges, the authors

Simultaneous measurement of neural bio-potentials from a large number of neurons is finding applications in a diverse range of areas such as healthcare and brain-machine interfacing. Neural amplifiers used for these measurements have a tight specification of low-power, low-noise and small area. Most of the reported neural amplifiers use operational transconductance amplifier (OTA) based capacitive

Here, a new design of a variable micro electromechanical system (MEMS) capacitor is introduced to use in telecommunication systems. For the first time, an on-chip MEMS component has been used in the substrate integrated waveguide (SIW) structures to avoid discrete and non-integrated connection problems and high noise levels and affects the operating frequency of telecommunication systems. The behaviour

This study presents a measurement method for a bike frame to solve a problem that usually relies on the digimatic callipers or mechanical molds handled by a human, therefore avoiding a long time process and measurement errors. In such a mechanism, the measured data is based on the handwritten record, and thus a difficulty may occur in further data analysis using the computer. For this reason, this

Physical unclonable function (PUF) is hardware-specific security primitive for providing cryptographic functionalities that are applicable for secure communication among the embedded devices. The physical structure of PUF is considered to be easy to manufacture but hard or impossible to replicate due to variations in its manufacturing process. However, a large community of analytics believes hardware-based

In this study a new structure was presented to design and simulate a considerably low power and high-speed 4-bit flash analogue to digital converter based on TSMC 0.18 μm complementary metal-oxide semiconductor (CMOS) technology. In this structure, in order to reduce the power consumption in the proposed comparator, the reference voltage was removed and replaced with the threshold voltage of CMOS transistors

The conventional approach to implementing analogue integrated circuits in nano-scale complementary metal oxide semiconductor (CMOS) technologies relies basically on circuit simulations using the SPICE models provided by the foundries. Depending on the circuit complexity, the designer should, however, spend a significant amount of time sizing the metal oxide semiconductor field effect transistors such

Temperature sensitivity is one of the major concern in conventional stacked gate-oxide junctionless tunnel-field-effect transistor (SGO-JL-TFET). In this regard, the authors have investigated the sensitivity toward the temperature variation of the SGO-JL double-gate TFET with low work-function live strip (LWLS-SGO-JL-TFET) and without LWLS-SGO-JL-TFET (SGO-JLTFET). Furthermore, they have analysed and

An area-efficient N-bit digital comparator with high operating speed and low-power dissipation is presented in this work. The proposed comparator structure consists of two separate modules. The first module is the comparison evaluation module (CEM) and the second module is the final module (FM). Independent from the input operand bitwidths, stages present in CEM involve the regular structure of repeated

A high-precision measurement method, based on multiple sampling, is proposed for the time interval of two signals in this study. A time interval measurement circuit integrated into the time-to-digital converter (TDC), is designed based on this high-precision measurement method. In the TDC, the authors use two identical delay lines as the holding module to ensure the two signals with a constant time

In this study, an InAs channel-based triple gate spin-field effect transistor (FET) model is proposed. The proposed triple-gate spin-FET offers a high density of integration, consumes low power and offers very high switching speed. By incorporating the suitable parameters like channel length, spin diffusion length, channel resistance and junction polarisation, the modelled triple gate spin-FET is then

The lower photo-generated current in a top cell limits the performance of the tandem solar cell by restricting the short circuit current density. To overcome this, the top cell must be suitably designed which can utilise the excess photo-generated current of the bottom cell. In this proposed work, an InGaP/GaSb tandem cell is designed by incorporating one-dimensional (1D) GaAs quantum superlattice

The versatility of the use of zinc oxide in numerous applications has attracted the attention of various academic research workers and industries. Various micro and nanostructures of zinc oxide have been explored owing to different growth methods and applications. In this research work, zinc oxide nanoflower is grown on a glass substrate using un-complicated and a low-cost hydrothermal method. Hydrolysis

Independent component analysis (ICA) is an unsupervised learning approach for computing the independent components (ICs) from the multivariate signals or data matrix. The ICs are evaluated based on the multiplication of the weight matrix with the multivariate data matrix. This study proposes a novel Pt/Cu:ZnO/Nb:STO memristor crossbar array for the implementation of both ACY ICA and Fast ICA for blind

The study presents two new realisations of bipolar two-quadrant implicit RMS-to-DC converter and four-quadrant multiplier/divider employing two VDTAs (voltage differential transconductance amplifier) and grounded passive elements. The converters provide the operating frequency of up to 10 MHz with increased precision in the processing of input currents signals, when compared to known realisations.

The crossbar array implementing the weighted sum computation and weight update operation is a promising hardware accelerator for neuromorphic computing. However, the voltage drop caused by the current flowing through the access lines could be aggressive for the resistive crossbar array in a fully parallel fashion. In this study, the authors analysed the impact of the line resistance on the crossbar

A fixed-width multiplier receives two n-bit operands and generates an approximate n-bit product as the output. It truncates part of the partial products and employs an appropriate error compensation circuit in order to reduce the approximation error. In this study, a new error compensation circuit for the fixed-width multiplier has been proposed which utilises the correction vector (CV) and modified

A novel high-frequency lossy uniform transmission line model is presented in this study. Novel features include a compactness of form and a level of simplicity that confers enhanced simulation efficiency in practical applications. Although specifically developed to target implementation in generic versions of SPICE, the compact high-frequency model can be implemented using only four lines of netlist

An impulse radio ultra-wideband (IR-UWB) transmitter (TX) consuming ultra-low power is presented. The low-complexity topology features control of the power spectral density (PSD) and central frequency for a broad range of applications. The PSD and frequency adjustment are accomplished by employing a tunable pulse generator and an adjustable driver. The IR-UWB TX suitable for on-off keying coding is

Multivalued logic (MVL) is an effective way to increase device integration in semiconductor circuits. The major problem for MVL implementation is the availability of proper semiconductor devices. Different quantum structures and their application in different semiconductor devices help them implement the MVL circuit. In this work, the designed graphic user interface will provide more flexibility to

An adaptive multi-resolution simulation (AMRS) framework for fast and accurate simulation of high-fidelity models of power electronic circuits (PECs) is presented in this study. The wide span of eigenvalues makes PEC simulation prohibitively slow. This problem can be tackled using the proposed approach. Singular perturbation approximation is used to extract simplified models by ignoring the transient

Portable automatic seizure detection systems can greatly improve the quality of life of epileptic patients. To improve the performance of seizure detection, independent component analysis (ICA) is implemented in these systems to extract artefacts of electroencephalogram (EEG), and then wavelet denoising method is used to remove the artefacts. However, classical ICA requires post-identification of the

This study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T-static random access memory (6T-SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizing the nMOS access transistors of the cell to alleviate NBTI ageing occurring in its pMOS pull-up transistors threatening the cell stability. Once the access transistors

An in-depth circuital analysis of an energy-efficient high peak power impulse radio ultra-wideband (IR-UWB) pulse generator monolithic microwave integrated circuit (MMIC) design is presented. The proposed IR-UWB pulse generation process is explained in detail. A trade-off between the peak output power level and the frequency of operation is discussed. The proposed circuit is optimised for the highest