Ternary content addressable memory (TCAM) is a high-speed memory employed in network search engines which consume significant power. Many authors have provided efficient power solutions by proposing different match line schemes. This study proposes the use of energy recovering adiabatic logic scheme in the design of power-efficient TCAM. Two different innovative quasi-adiabatic TCAM (QATCAM) core cells

In recent years, due to the high ability of the multi-valued logic design in nanotechnology, the interest in the design of it has been renewed. Using multi-valued logic can lead to reduction of interconnections in the chip. This study presents two novel designs of a ternary memory cell using carbon nanotube field effect transistors (CNFETs) with only one supply voltage. In the previous works, a ternary

This study presents a low-cost multi-throughput true random number generator (TRNG) intellectual property (IP) based on a variable-length multi-mode ring oscillator. The proposed TRNG implements a multi-throughput feature by bypassing inverter cells in the ring oscillator for reducing the loop delay. This multi-throughput feature offers the advantage of high-performance or low-power operation when

Open-circuit voltage decay (OCVD) is a method to characterise minority carrier effective lifetime ( ). It is non-destructive, simple and low-cost. It has been mainly used in silicon p-n junctions. is not only a very important parameter to optimise device design but also to supervise process steps. It is not the only parameter we can obtain by OCVD. Due to the intrinsic space charge region capacitance

This work provides a new simultaneous noise and impedance matching (SNIM) methodology for designing a 3–5 GHz ultrawideband low-noise amplifier (LNA) in 0.18 μm complementary metal–oxide–semiconductor (CMOS) process using the advanced design system platform. To justify the proposed method, common gate (CG)- and common source (CS)-input-matched LNAs are designed where the variation of input impedance

This study reports an analysis of noise figures (NFs) in a reflection-type microwave amplifier using resonant tunnelling diodes (RTDs). The minimum NF for the RTD amplifier based on 0.9 μm InP process technology, featuring a power gain ( S 21 ) of 10.4 dB and a dc-power consumption of 133 μW at a centre frequency of 5.7 GHz, is measured to be 5.08 dB at a bias voltage of 0.355 V. The estimated NF characteristic

In this study, the design of digital logic gates and circuits in ternary logic is presented. The ternary logic is observed to be a better alternative to the traditional binary logic because it offers faster computations, smaller chip area, and lesser interconnects. Thus, it allows designing the low-complex, high-speed, and energy-efficient circuits in future digital design. A novel technique is proposed

Electronic systems’ growth causes complexity and increases the risk of failure. Fault tolerance structures are one of the useful ideas for resolving this problem. In this paper, a fault tolerant approach to digital electronic modules is introduced, using hardware redundancy to make those modules fault tolerant. The proposed structure of hardware redundancy has a voter unit that can mask and detect

In a recent work on multiple constant multiplication (MCM) problems, a fully predictable sub-linear runtime heuristic was introduced, called Radix-2 r MCM. This method shows competitive results in speed, power and area, comparatively with the leading algorithms. In this study, the authors combine Radix-2 r MCM with an exact common subexpression elimination (CSE) algorithm. The resulting algorithm denoted

Fast Fourier transform (FFT) is utilised to minimise the complexity of discrete Fourier transform by converting signals from frequency domain to time domain and conversely. Digital signal processing systems like image processing, general filtering, sonar, spread-spectrum communications and convolutions use this FFT operations. Radix-2 decimation in frequency (R2DIF) method is designed to execute an

This study introduces the design of true random number generator (TRNG) using jitter, metastability and current starved topology. The proposed design consisted of a current starved inverter-based ring oscillator (RO) with a high-frequency divider block (designed by T-FF followed by D-FF to address setup and hold time issues), jitter extraction and metastable block followed by two sampling blocks. The

Radio frequency (RF) coaxial connectors are important constituents of modern communication systems. The degraded electrical contacts may adversely affect the signal transmission efficiency particularly in the case of loose connections. In this study, a distributed equivalent model of a coaxial connector with degraded receptacle and the loose connection was developed. The scattering parameters were

In this study, a 60   nm gate length double-gate AlGaN/GaN/AlGaN metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT) is proposed and different electrical characteristics, such as DC, small-signal, radio-frequency (RF) and high-frequency noise performances of the devices are characterised through TCAD device simulations. The results of double-gate MOS-HEMT are compared with the TCAD

In this paper, we have designed and realized a two-stage low-noise power amplifier (LNPA) with resistive feedback network targeting for Ka-band compact RF front-end applications. Featuring the characteristics of both low noise and high power at the same time, the LNPA is expected to be a possible one-chip replacement of power and low noise amplifiers integrated in a conventional transceiver/receiver

In this study, channel potential for silicon-based doped dual-metal double-gate tunnel field-effect transistor structure is analytically solved using the evanescent-mode approach in the sub-threshold region. This method generally describes short channel effects in the entire channel region of the device structure and predicts different characteristic length which depends on tunnel current and does

Mathematical modelling of non-linearity due to charge injection phenomenon with variation in desired characteristics of complementary metal oxide semiconductor (CMOS) image sensor (CIS) and correlated double sampling (CDS) circuits is presented. Existing suppression strategies of charge injection effect for CIS and CDS circuits lack in accuracy because of the absence of knowledge of its effect with

In recent past, the cross-coupling crosstalk becomes a dominating factor due to the closer proximity of wire that reduces the performance of coupled interconnects at lower technology. To overwhelm interconnect problems, this work demonstrates a comprehensive study of unshielded and active shielded spatially arranged mixed carbon nanotube (CNT) bundle (SMCB) and randomly distributed mixed CNT bundle

In this work, the authors demonstrate the realisation of metal controlled (MC) dopingless (DL) metal oxide semiconductor field-effect transistor (MOSFET) on a selective buried oxide (SELBOX). The different doped regions of the proposed device, such as source/drain and metal partial ground plane, have been realised with different metal work functions and the device is being named as MC-DL-SELBOX-MOSFET

This study presents two configurations to realise the behaviour of a floating memristor and an inverse memristor. The modified version of VDCC (voltage differencing current conveyor) termed as MVDCC (modified VDCC) is used to develop the presented emulators. The floating memristor emulator uses a single MVDCC and two grounded passive elements while the configuration of floating inverse memristor emulator

Differential cascode voltage switch (DCVS) is a static technique which offers the advantages of layout density, logic flexibility together with improved delay and power consumption. In this study, DCVS-based ternary logic gates and unary operators are reported using static diode voltage divider topology. The main focus of the proposed ternary designs using DCVS logic style is to provide minimum energy

This study proposes a design of a maximum power point tracking (MPPT)-based DC–DC boost converter for an radio frequency (RF) energy harvester. The MPPT technique has been implemented in the converter using an adaptable load tracking mechanism with variable input RF power to meet the supply voltage tolerance limits. The proposed MPPT scheme is implemented using a sample-and-hold circuit in the tracking

One selector-one resistor (1S-1R) configuration is desirable to use in conductive bridge resistive random-access memory (CBRAM) and resistive random-access memory (RRAM) crossbar arrays (CBAs) to reduce sneak path current. In this study, an analytical model of Ta2O5/TaOx/TiO2 selector device is developed and is integrated with RRAM model to demonstrate the acquired features of 1S-1R to reduce the sneak

This study presents a self-sustainable soil energy harvesting system with a rapid startup circuit. The proposed system enables the operation from input voltage as low as 0.3 V, and to up-convert the output to 3.3 V. The system is capable of extracting maximum power from the soil energy source. An efficient startup circuit that performs low initial charging time for a supercapacitor is presented. Experimental

In this study, a new tier partitioning algorithm for three-dimensional integrated circuits (3D ICs) using a genetic algorithm (GA) is presented. Design parameters for the proposed 3D IC partitioning method are average layer power density and number of through-silicon vias (TSVs) subject to fixed-outline constraint. The GA with newly introduced crossover and mutation operation, termed as even crossover

This study describes a field-programmable gate arrays (FPGAs) based technique, which aims to significantly improve the resolution of complementary drivers in full-bridge DC–DC converters. An algorithm for precise adjustment of both the duty cycle and the frequency of the pulse width modulator (PWM) is presented. It is experimentally verified by software simulation and FPGA hardware implementation.

Interval observer design and related techniques have been researched and applied in many engineering fields and continue to be an active research area in the estimation and control society for the last two decades. An Interval observer is a special class of observers that generates a bounded interval vector for the real state vector in a guaranteed way under the assumption that the uncertainties are

In this study, the authors have proposed both field-programmable gate array (FPGA) and application specific integrated circuit (ASIC) based realisation of the empirical mode decomposition (EMD) algorithm for the real-time signal processing. Here, a single module is used for the calculation of maxima and minima, and another single module is used for the calculation of upper and lower envelopes instead

This study presents a novel implementation technique for linear phase variable bandwidth finite impulse response (FIR) filters with a noticeable reduction in transition bandwidth as well as hardware complexity. In this proposition, concept of Farrow structure based design technique is effectively utilised; whereas the fixed sub-filters are constructed from a generalised interpolated bandpass method

This study introduces a new approach for realising a sinusoidal oscillator with three outputs, using an active-resistor-capacitor (RC) approach. Using the proposed approach, a new circuit employing three current feedback operational amplifiers and passive components is further introduced. The circuit employs two grounded capacitors and four resistors, out of which one is grounded. The new circuit based

Simple and efficient frequency compensation technique for a four-stage amplifier is presented in this study. Using a differential feedback stage and a single Miller capacitor on its output, the frequency compensation network is formed. The proposed configuration is described via matrix description. Meanwhile, an analytical transfer function is calculated. The proposed amplifier demonstrates low die

Emerging devices such as double gate carbon nanotube field effect transistors (DG CNTFETs) have opened up manifold possibilities for reconfigurable logic design. The thickness of gate oxide and the employment of inhomogeneous dielectrics over and under the carbon nanotubes (CNTs) impact the operation of DG CNTFETs. In this work, the dielectric constant and the thickness of the gate oxide are optimised

The authors propose a hybrid transceiver and an energy-efficient link architecture for bidirectional multipoint-to-multipoint signalling across on-chip global interconnect. The proposed link architecture eliminates the need for passive termination for bandwidth enhancement by means of active termination, reducing the required transmitter signalling current drastically and hence, improving the overall

In wireline communication systems, InterSymbol Interference (ISI) may also occur by termination mismatch at either end of a long channel. Termination resistors, characteristic channel impedance, and connectors may get altered by temperature and supply voltage variations during operation. Wireline front-ends may exercise on-the-fly termination calibration to mitigate ISI during operation. Here the authors

Three simulated floating inductor (SFI) circuits containing a single DDCC− called as minus-type differential difference current conveyor are proposed. These SFIs are series lossy, parallel lossy and negative lossless ones. The used DDCC− in each of the proposed SFIs has a single Z terminal. Without needing any passive element matching constraints, each of the proposed SFIs is composed of a minimum

This study presents firstly, experimental results through an innovative reliability bench of pulsed RF life test in a radar application for device lifetime under pulse conditions, then the physical clarifications of the failure phenomenon. The results of accelerated aging stress relative to various temperatures (3000 h at 150 and 10°C) are presented. Based on the radio-frequency (RF) behaviour parameters

Memristor-based stateful logic circuits can perform logic operations and logic value storage, which creates an intriguing opportunity for the implementation of an advanced computational architecture. This study proposes a novel memristor-based stateful logic implementation. Specifically, the presented approach is capable of realising two-input or multi-input AND, OR, NAND and NOR operations, and single-input

Due to feedback amplifier analysis simplification, Miller theorem, feedback theorem and Gray–Searle theorem are the most used tools on the calculation of the frequency response. However, they are only approximated results and then are invalid for overall closed-loop voltage gain of the frequency response. The traditional feedback theory, Miller theorem and Gray–Searle theorem are troublesome due to

Voltage sag and short interruption lead to the tripping of sensitive equipment and cause the economic loss of the industry users. A programmable logic controller (PLC) is essential equipment used in the industrial process. However, there is no detailed understanding of the sensitivity of PLC under voltage sag and short interruption. The response characteristic of PLC under voltage sag is studied. This

This study proposes an input interface based on a magnetic tunnel junction (MTJ) to initialise the magnetisation directions of all-spin logic (ASL) circuits. It is convenient to input logic 0 and logic 1 to ASL circuits by changing the current direction into the MTJ. The impacts of current density, tunnel magneto-resistance (TMR), and resistance–area product (RA) on the input interface are studied

This study presents a compact wide stopband microstrip diplexer which is designed based on a novel resonator structure. This novel resonator consists of a main hairpin cell loaded by a smaller hairpin and T-shaped cells. The presented diplexer operates at 3.46 and 4.75 GHz for IEEE 802.16 worldwide interoperability for microwave access (WiMAX) and IEEE802.11a Wireless LAN applications, respectively

In this study, an improved capacitor-less flipped voltage follower (FVF) low drop-out regulator (LDO) with active feed-forward compensation (AFFC) and an efficient slew-rate enhancer (SRE) circuit is presented. In capacitor-less FVF LDOs, the dominant pole is placed at the gate of the power metal oxide semiconductor field effect transistor (MOSFET) which demands minimum load current for the feedback-loop

This study presents a robust design of a trigger pulse generator that produces trigger pulses of variable widths/durations that are tuned using an external control as per the requirements. The proposed design comprises two elementary modules: a delay element and an XOR circuit. The proposed circuit is implemented using a 16 nm CMOS technology node and simulation results have been verified using the

In this study the authors propose a novel and straightforward design procedure for the single-ended ring oscillator (SERO). This procedure determines the values of the circuit parameters to reach the desired oscillation frequency while the power consumption and the area are minimised and the noise is kept below the desired value. Furthermore, the authors analyse the SERO and suggest a practical formula

This study presents a novel voltage-programmed, amorphous-indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT)-based active-matrix organic light-emitting diode (AMOLED) pixel circuit. The circuit utilises the threshold voltage ( V TH ) sensing ability of a diode-connected transistor to compensate for the spatial as well as the temporal variation of the threshold voltage of the driving transistor

This paper presents a single loop 3 rd order discrete-time Sigma–Delta Modulator ( ) using a single operational amplifier (Op-Amp). The proposed utilises delay-based discrete-time integrators and a single Op-Amp is used to implement all the integrators of the proposed design. The delay-based design helps in relaxing the settling time requirement of an integrator, also the error due to slewing in the

A dual-frequency band low input power rectenna is proposed in this study. The rectenna is comprised of a co-planar waveguide (CPW) rectifier integrated with a rectangular split ring antenna loaded by a spiral strip line. A single diode series connection topology is used to miniaturise the losses at low input power. A spiral coil in addition to two short circuit stubs are used as a matching network

This study proposes a new scheme for rail-to-rail input StrongARM latch comparator. Additional differential input p-type metal-oxide-semiconductor (PMOS) and cross-coupled n-type metal-oxide-semiconductor (NMOS) transistors have been introduced to achieve the rail-to-rail input range. The proposed scheme offers low-energy consumption of 15.2 fJ and a high speed of 3 GHz, which makes it attractive for

A new plus-type second-generation voltage conveyor (VCII+) based first-order mixed-mode (MM) all-pass (AP) filter is proposed in this study. The proposed MM AP filter employs two VCII+s, three resistors and one grounded capacitor. It has low input and high output impedances for the current-mode selection while it has low input and low output impedances for the transimpedance-mode selection. The AP

In this study, we compared the timing and its random dopant fluctuation (RDF)-induced variations in nanometre conventional and negative-capacitance CMOS (NC-CMOS) inverters. The authors found that the transition delay in the NC-CMOS inverter exhibits a strongly dependence on the viscosity coefficient ( ρ ) of the ferroelectric (FE). Only NC-CMOS using sufficiently low ρ with smaller response time to

This study presents numerical simulation of a novel gallium nitride buffered trench gate (GaN-BTG) metal oxide semiconductor field effect transistor (MOSFET) for high-speed and low-power applications. The electrical characteristics of GaN-BTG-MOSFET are compared with BTG MOSFET and conventional trench gate MOSFET. A comparative study of different performance factors such as electric field, electron

This study presents the algebraic cryptanalysis of a continuous-time chaotic random number generator (RNG) based on a Zhongtang chaotic system. The chaos-based RNG provides key values for logic encryption, round key formation and the substitution box (S-box) generation steps in AES (advanced encryption standard). In this study, an attack method is proposed to exploit the weaknesses of the chaos-based

A technique to extract statistical model parameters for skewed Gaussian process variations is proposed. Statistical compact model extraction traditionally assumes that underlying process variations are Gaussian in nature. ON currents in certain high voltage technologies, which are linear in process deviations, show skew in their distribution and hence is indicative of skew in the underlying process

Here, the critical path of ripple carry adder (RCA)-based binary tree adder (BTA) is analysed to find the possibilities for delay minimisation. Based on the findings of the analysis, the new logic formulation and the corresponding design of RCA are proposed for the BTA. The comparison result shows that the proposed RCA design offers better efficiency in terms of area, delay and energy than the existing

Quantum-dot cellular automata (QCA) is a novel nanodevice that implements logic circuits at the nanoscale. Information encryption is a key issue in nanocommunications. This article proposes a new method ‘select, cross, variation’ (SCV) for data encryption. This work also implements the QCA layout of this method for the first time. The QCA-based SCV circuit uses 71 cells. The circuit is composed of

This work presents an analogue equaliser with digital tuning. It compensates the losses introduced by up to 120 m long category 5 unshielded twisted pair cables and baseline wander (BLW). The equaliser is designed for Fast Ethernet with a symbol rate of 125 MHz. A g m -C filter, based on three first-order high pass filters, is used to compensate the cable loss. To minimise power consumption, three

Alternate testing techniques have been progressively adopted as a promising solution due to their effectiveness against classical specification-based test methods. This work presents a built-in test system, which adaptively generates an indirect digital signature characterising the circuit under test, which is later used to diagnose the actual performances relying on a statistical dictionary-based

This study proposes vertical sidewall implantation for noise reduction of CMOS image sensor pixel employing a vertical transfer gate (VTG). The pixel performance is evaluated by 3D device-level simulation. It is concluded that the proposed pixel's output is less sensitive to interface traps compared to similar previous work. In previous back-side-illuminated shared VTG pixel, which lacks the sidewall

Quantum cellular automata (QCA) enables performing logic operations at the sub-nm scale. The clock field provides energy gain in QCA circuits, and the energy is dissipated while data flow from inputs to outputs during clock time slots. The authors start from a quantum mechanical model and end in a simple electrostatic model for energy calculation of molecular QCA systems, where the cells are fully

The design of a 4-bit encoder with a bubble error correction of first order is described in this study. Since encoder restricts speed of the flash analogue-to-digital converter (ADC), therefore, an improved and faster encoder is an essential requirement to push its limits. Encoder is divided into two parts: one-hot code generator [or bubble error corrector (BEC)] and binary encoder. Binary encoder

Differential power analysis (DPA) has become an efficient side channel attack that obtains a secret key from the extracted power traces. Several traditional CMOS-based DPA countermeasures resulted in high area overhead and performance degradation. This study presents low area overhead DPA countermeasure exploring tunnel field effect transistors (TFET) based random number generator (RNG). TFET exhibits