This study proposes an analytical drain model of the strained junctionless nanowire tunnel field-effect transistor fabricated on the Si 1 -x Ge x virtual substrate. The surface potential is derived by solving Poisson's equation in the channel region. Effects of the strained silicon on the potential profile can be expressed as a function of the Ge concentration in the Si 1 -x Ge x virtual substrate

Induction heating is regarded as a clean cooking technology, whose prominent advantages include contactless energy transfer, controllable heating rate, and safety. In household applications, it is expected that this approach is supposed to replace conventional gas stoves aiming at a more sustainable future. The increase of energy consumption associated with this trend cannot be neglected, while distributed

Lithium battery has become the main power source of new energy vehicles due to its high energy density and low self-discharge rate. In the actual use of the series battery pack, due to the internal resistance and self-discharge rate of batteries and other factors, inconsistencies between the individual cells are unavoidable. Such inconsistencies will reduce the energy utilisation rate and service life

In this work, a frequency reconfigurable broadband radio frequency-predistorter (BB RF-PD) is proposed that can effectively suppress the power amplifier (PA) intermodulation distortion from 200 MHz to 2.5 GHz. It is an attractive lineariser solution for radio repeaters in long distance communication, where baseband information is not readily available. For broadband signals, existing linearisation

A small-signal model is established for the basic constant voltage (CV) flyback converter firstly. Then the phase margin and the bandwidth, which can reflect the system stability and rapidity, are deduced through transfer function. The parameters affecting the stability of the system can be obtained by the model's derivation to confirm the appropriate external capacitance value. To improve the precision

This study presents an all-digital power-efficient integrating frequency difference-to-digital converter (iFDDC) and explores its applications in gigahertz (GHz ) frequency-locking. The iFDDC utilises a bi-directional gated delay line (BDGDL) to detect and accumulate the frequency difference between two GHz signals and digitises the result with ultra-low power consumption. The built-in integration

Vedic algorithm is beneficial for the application in the design of high-speed computing and hardware. This study presents a fast signed binary multiplication structure based on Vedic Nikhilam algorithm. The authors explored the Nikhilam sutra for unsigned decimal numbers to both signed decimal and binary operands. The proposed multiplier leads to significant gains in speed by converting a large operand

In this work, the authors study the performance of black phosphorus double gate MOSFET (BP-DGMOSFET) within the ballistic limit. A hybrid simulation technique involving both atomistic and technology computer-aided design (TCAD) tool has been used for the first time to simulate the device characteristics. First, the density functional theory has been used to simulate the electrical characteristics of

In this work, a new fractional-order sinusoidal oscillator is proposed. The proposed oscillator consists of one fractional-order all-pass filter and one fractional-order lossless integrator blocks. In order to emulate fractional-order capacitors, three different approximation methods the R – C pair, Matsuda and Oustaloup are employed and the results are compared. Three sinusoidal voltage signals with

Accelerators that utilise the sparsity of both activation data and network structure of convolutional neural networks (CNNs) have demonstrated efficient processing of CNNs with superior performance. Previous research studies have shown three critical design concerns when designing accelerators for sparse CNNs, including data reuse, parallel computing performance, and effective sparse computation. These

Asynchronous quasi-delay-insensitive (QDI) circuits have recently become an active research area in digital logic design. In contrast with synchronous paradigms, QDI approaches utilise threshold gates with hysteresis, such as Muller C-element and null convention logic (NCL) gates. However, there are no existing methods to explicitly describe these hysteretic logic gates in Boolean algebra. Therefore

This study presents a novel high gain operational amplifier (op-amp) and a comparator using n -type all enhancement amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). The proposed op-amp employs regulated cascode topology in conjunction with capacitive bootstrap load, which enhances the gain to 159.87% (V/V) as compared to op-amp with bootstrapping load. In addition, common

This study deals with a single soft fault diagnosis of non-linear circuits having multiple DC solutions. The key problem of the diagnosis is arranging a measurement test. Creation of the test for the above-defined class of circuits is discussed in detail. It is assumed that only input and output terminals are accessible in the circuit. The test is created based on some single-valued input or transfer

This study presents the performance of differential cascode balun low noise amplifier (DCBLNA) with ultra-wideband (UWB) for human breast cancer diagnosis. The proposed DCBLNA design-I with bulky spiral inductors achieves insufficient bandwidth with large power consumption of 10.8 mW. To attain the proper UWB band of operation, suspended strip line (SSLIN) radiators have employed in the proposed design-I

In this study, the design routine of a novel phase frequency detector and charge-pump (PFD-CP) is discussed. The main advantage of the proposed circuit is its improved dead zone performance as the circuits of PFD-CP have been merged to reduce the latency of the structure. To justify this, by means of a reconfigurable loop filter, a fast-locking low-power phase-locked loop (PLL) has been implemented

In this study, a method for fine adjustment of Xilinx field programmable gate array (FPGA) routing delays is proposed and applied to improve the linearity of an unbalanced multi-measurement time-to-digital converter (TDC). The delay control method increases load capacitances of interconnect points of switch matrices by small amounts using additional connections to unused interconnects in the FPGA fabric

The increasing demand for high-performance computing has emphasised the invocation of sophisticated multi/many-core computing architecture. Graphical Processing Unit (GPU) is considered to be an essential innovation in this regard as GPU offers a significant amount of parallelism in the execution of complex computing applications. The performance of GPUs in reducing the computational time of such applications

Recently, the wireless sensor networks have rapidly emerged into agriculture and greenhouse because of owing many advantages than the traditional methods. However, some subjects such as cost and power are being brought up as a controversial issue. This study presents a developed wireless sensor network based on a proposed algorithm to improve tomato crop in a greenhouse. The developed sensor nodes

Electrical tuning of bandwidth is critical for microelectromechanical system (MEMS) resonator-based narrowband filters especially at ultra-high frequency ranges and beyond. The resonance frequency of MEMS resonators is highly susceptible to fabrication process uncertainties and very small fabrication variations could result in significant shift in their resonance frequency. Although, disk resonators

The study discusses selected issues of modelling and designing current-mode devices. The authors propose the design flow that covers abstract behavioural models, the schematic and SPICE-level netlists and the post-layout parasitic parameters. The considerations related to the analogue functional blocks with a dual-stage complexity. The theoretical backgrounds of the current-mode basic building blocks

A novel double-trench superjunction SiC metal–oxide–semiconductor field-effect transistor (MOSFET) with an integrated Schottky contact at the drain side is proposed in this study. Results indicate an improvement of 58% in reverse recovery current /charge and 22% in the trench corner electric field compared to the device without Schottky and without superjunction, respectively. This comparison became

A split gated silicon nanotube field-effect transistor (FET) biosensor has been proposed for the label free detection of the biomolecules for the first time in literature. The sensitivity of the sensing device has been analysed considering the on current ( I ON ) and the threshold voltage ( V th ) variation. Sub-threshold regime has been considered here to detect the charged/neutral biomolecules. Extensive

A novel scheme for tunable complementary metal–oxide–semiconductor (CMOS) transconductor robust against process and temperature (PT) variations is presented. The proposed configuration is a voltage controlled circuit based on a double negative channel-metal-oxide-semiconductor (NMOS) transistor differential pairs connected in parallel, which has low power and high linearity. The PT compensation is

Approximate computing provides a promising way to achieve low power design at the cost of acceptable error. As a core component in a processor, the performance of the multiplier is important. This study presents designs of approximate-truncated Booth multipliers (ATBMs) using proposed approximate modified radix-4 Booth encoders (AMBEs), approximate 4-2 compressors (ACs) and gradually truncated partial

Approximate computing is a novel approach to design area-efficient arithmetic units for portable error resilient applications. In this work, the authors have proposed a parallel architecture for median filter targeting digital image processing. Proposed parallel median filter (PMF) uses pre-sorter and post-merge units to replace corrupted processing pixel (PP) with a median of pixels in the 3X3 processing

Ternary content addressable memory (TCAM) is a high-speed memory employed in network search engines which consume significant power. Many authors have provided efficient power solutions by proposing different match line schemes. This study proposes the use of energy recovering adiabatic logic scheme in the design of power-efficient TCAM. Two different innovative quasi-adiabatic TCAM (QATCAM) core cells

In recent years, due to the high ability of the multi-valued logic design in nanotechnology, the interest in the design of it has been renewed. Using multi-valued logic can lead to reduction of interconnections in the chip. This study presents two novel designs of a ternary memory cell using carbon nanotube field effect transistors (CNFETs) with only one supply voltage. In the previous works, a ternary

This study presents a low-cost multi-throughput true random number generator (TRNG) intellectual property (IP) based on a variable-length multi-mode ring oscillator. The proposed TRNG implements a multi-throughput feature by bypassing inverter cells in the ring oscillator for reducing the loop delay. This multi-throughput feature offers the advantage of high-performance or low-power operation when

Open-circuit voltage decay (OCVD) is a method to characterise minority carrier effective lifetime ( ). It is non-destructive, simple and low-cost. It has been mainly used in silicon p-n junctions. is not only a very important parameter to optimise device design but also to supervise process steps. It is not the only parameter we can obtain by OCVD. Due to the intrinsic space charge region capacitance

This work provides a new simultaneous noise and impedance matching (SNIM) methodology for designing a 3–5 GHz ultrawideband low-noise amplifier (LNA) in 0.18 μm complementary metal–oxide–semiconductor (CMOS) process using the advanced design system platform. To justify the proposed method, common gate (CG)- and common source (CS)-input-matched LNAs are designed where the variation of input impedance

This study reports an analysis of noise figures (NFs) in a reflection-type microwave amplifier using resonant tunnelling diodes (RTDs). The minimum NF for the RTD amplifier based on 0.9 μm InP process technology, featuring a power gain ( S 21 ) of 10.4 dB and a dc-power consumption of 133 μW at a centre frequency of 5.7 GHz, is measured to be 5.08 dB at a bias voltage of 0.355 V. The estimated NF characteristic

In this study, the design of digital logic gates and circuits in ternary logic is presented. The ternary logic is observed to be a better alternative to the traditional binary logic because it offers faster computations, smaller chip area, and lesser interconnects. Thus, it allows designing the low-complex, high-speed, and energy-efficient circuits in future digital design. A novel technique is proposed

Electronic systems’ growth causes complexity and increases the risk of failure. Fault tolerance structures are one of the useful ideas for resolving this problem. In this paper, a fault tolerant approach to digital electronic modules is introduced, using hardware redundancy to make those modules fault tolerant. The proposed structure of hardware redundancy has a voter unit that can mask and detect

In a recent work on multiple constant multiplication (MCM) problems, a fully predictable sub-linear runtime heuristic was introduced, called Radix-2 r MCM. This method shows competitive results in speed, power and area, comparatively with the leading algorithms. In this study, the authors combine Radix-2 r MCM with an exact common subexpression elimination (CSE) algorithm. The resulting algorithm denoted

Fast Fourier transform (FFT) is utilised to minimise the complexity of discrete Fourier transform by converting signals from frequency domain to time domain and conversely. Digital signal processing systems like image processing, general filtering, sonar, spread-spectrum communications and convolutions use this FFT operations. Radix-2 decimation in frequency (R2DIF) method is designed to execute an

This study introduces the design of true random number generator (TRNG) using jitter, metastability and current starved topology. The proposed design consisted of a current starved inverter-based ring oscillator (RO) with a high-frequency divider block (designed by T-FF followed by D-FF to address setup and hold time issues), jitter extraction and metastable block followed by two sampling blocks. The

Radio frequency (RF) coaxial connectors are important constituents of modern communication systems. The degraded electrical contacts may adversely affect the signal transmission efficiency particularly in the case of loose connections. In this study, a distributed equivalent model of a coaxial connector with degraded receptacle and the loose connection was developed. The scattering parameters were

In this study, a 60   nm gate length double-gate AlGaN/GaN/AlGaN metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT) is proposed and different electrical characteristics, such as DC, small-signal, radio-frequency (RF) and high-frequency noise performances of the devices are characterised through TCAD device simulations. The results of double-gate MOS-HEMT are compared with the TCAD

In this paper, we have designed and realized a two-stage low-noise power amplifier (LNPA) with resistive feedback network targeting for Ka-band compact RF front-end applications. Featuring the characteristics of both low noise and high power at the same time, the LNPA is expected to be a possible one-chip replacement of power and low noise amplifiers integrated in a conventional transceiver/receiver

In this study, channel potential for silicon-based doped dual-metal double-gate tunnel field-effect transistor structure is analytically solved using the evanescent-mode approach in the sub-threshold region. This method generally describes short channel effects in the entire channel region of the device structure and predicts different characteristic length which depends on tunnel current and does

Mathematical modelling of non-linearity due to charge injection phenomenon with variation in desired characteristics of complementary metal oxide semiconductor (CMOS) image sensor (CIS) and correlated double sampling (CDS) circuits is presented. Existing suppression strategies of charge injection effect for CIS and CDS circuits lack in accuracy because of the absence of knowledge of its effect with

In recent past, the cross-coupling crosstalk becomes a dominating factor due to the closer proximity of wire that reduces the performance of coupled interconnects at lower technology. To overwhelm interconnect problems, this work demonstrates a comprehensive study of unshielded and active shielded spatially arranged mixed carbon nanotube (CNT) bundle (SMCB) and randomly distributed mixed CNT bundle

In this work, the authors demonstrate the realisation of metal controlled (MC) dopingless (DL) metal oxide semiconductor field-effect transistor (MOSFET) on a selective buried oxide (SELBOX). The different doped regions of the proposed device, such as source/drain and metal partial ground plane, have been realised with different metal work functions and the device is being named as MC-DL-SELBOX-MOSFET

This study presents two configurations to realise the behaviour of a floating memristor and an inverse memristor. The modified version of VDCC (voltage differencing current conveyor) termed as MVDCC (modified VDCC) is used to develop the presented emulators. The floating memristor emulator uses a single MVDCC and two grounded passive elements while the configuration of floating inverse memristor emulator

Differential cascode voltage switch (DCVS) is a static technique which offers the advantages of layout density, logic flexibility together with improved delay and power consumption. In this study, DCVS-based ternary logic gates and unary operators are reported using static diode voltage divider topology. The main focus of the proposed ternary designs using DCVS logic style is to provide minimum energy

This study proposes a design of a maximum power point tracking (MPPT)-based DC–DC boost converter for an radio frequency (RF) energy harvester. The MPPT technique has been implemented in the converter using an adaptable load tracking mechanism with variable input RF power to meet the supply voltage tolerance limits. The proposed MPPT scheme is implemented using a sample-and-hold circuit in the tracking

One selector-one resistor (1S-1R) configuration is desirable to use in conductive bridge resistive random-access memory (CBRAM) and resistive random-access memory (RRAM) crossbar arrays (CBAs) to reduce sneak path current. In this study, an analytical model of Ta2O5/TaOx/TiO2 selector device is developed and is integrated with RRAM model to demonstrate the acquired features of 1S-1R to reduce the sneak

This study presents a self-sustainable soil energy harvesting system with a rapid startup circuit. The proposed system enables the operation from input voltage as low as 0.3 V, and to up-convert the output to 3.3 V. The system is capable of extracting maximum power from the soil energy source. An efficient startup circuit that performs low initial charging time for a supercapacitor is presented. Experimental

In this study, a new tier partitioning algorithm for three-dimensional integrated circuits (3D ICs) using a genetic algorithm (GA) is presented. Design parameters for the proposed 3D IC partitioning method are average layer power density and number of through-silicon vias (TSVs) subject to fixed-outline constraint. The GA with newly introduced crossover and mutation operation, termed as even crossover

This study describes a field-programmable gate arrays (FPGAs) based technique, which aims to significantly improve the resolution of complementary drivers in full-bridge DC–DC converters. An algorithm for precise adjustment of both the duty cycle and the frequency of the pulse width modulator (PWM) is presented. It is experimentally verified by software simulation and FPGA hardware implementation.

Interval observer design and related techniques have been researched and applied in many engineering fields and continue to be an active research area in the estimation and control society for the last two decades. An Interval observer is a special class of observers that generates a bounded interval vector for the real state vector in a guaranteed way under the assumption that the uncertainties are

In this study, the authors have proposed both field-programmable gate array (FPGA) and application specific integrated circuit (ASIC) based realisation of the empirical mode decomposition (EMD) algorithm for the real-time signal processing. Here, a single module is used for the calculation of maxima and minima, and another single module is used for the calculation of upper and lower envelopes instead

This study presents a novel implementation technique for linear phase variable bandwidth finite impulse response (FIR) filters with a noticeable reduction in transition bandwidth as well as hardware complexity. In this proposition, concept of Farrow structure based design technique is effectively utilised; whereas the fixed sub-filters are constructed from a generalised interpolated bandpass method

This study introduces a new approach for realising a sinusoidal oscillator with three outputs, using an active-resistor-capacitor (RC) approach. Using the proposed approach, a new circuit employing three current feedback operational amplifiers and passive components is further introduced. The circuit employs two grounded capacitors and four resistors, out of which one is grounded. The new circuit based

Simple and efficient frequency compensation technique for a four-stage amplifier is presented in this study. Using a differential feedback stage and a single Miller capacitor on its output, the frequency compensation network is formed. The proposed configuration is described via matrix description. Meanwhile, an analytical transfer function is calculated. The proposed amplifier demonstrates low die

Emerging devices such as double gate carbon nanotube field effect transistors (DG CNTFETs) have opened up manifold possibilities for reconfigurable logic design. The thickness of gate oxide and the employment of inhomogeneous dielectrics over and under the carbon nanotubes (CNTs) impact the operation of DG CNTFETs. In this work, the dielectric constant and the thickness of the gate oxide are optimised

The authors propose a hybrid transceiver and an energy-efficient link architecture for bidirectional multipoint-to-multipoint signalling across on-chip global interconnect. The proposed link architecture eliminates the need for passive termination for bandwidth enhancement by means of active termination, reducing the required transmitter signalling current drastically and hence, improving the overall

In wireline communication systems, InterSymbol Interference (ISI) may also occur by termination mismatch at either end of a long channel. Termination resistors, characteristic channel impedance, and connectors may get altered by temperature and supply voltage variations during operation. Wireline front-ends may exercise on-the-fly termination calibration to mitigate ISI during operation. Here the authors

Three simulated floating inductor (SFI) circuits containing a single DDCC− called as minus-type differential difference current conveyor are proposed. These SFIs are series lossy, parallel lossy and negative lossless ones. The used DDCC− in each of the proposed SFIs has a single Z terminal. Without needing any passive element matching constraints, each of the proposed SFIs is composed of a minimum

This study presents firstly, experimental results through an innovative reliability bench of pulsed RF life test in a radar application for device lifetime under pulse conditions, then the physical clarifications of the failure phenomenon. The results of accelerated aging stress relative to various temperatures (3000 h at 150 and 10°C) are presented. Based on the radio-frequency (RF) behaviour parameters