A novel carrier stored trench bipolar transistor (CSTBT) with split gate (SG) and recessed emitter trench (SGRET CSTBT) is proposed. The proposed device features a SG structure with thicker oxide layer under the trench gate and recessed trench emitter, respectively. Compared with the conventional CSTBT with recessed emitter trench (RET CSTBT), the proposed device not only significantly reduces the

A novel high performance SiC asymmetric cell trench MOSFET with split gate (SG) and integrated junction barrier schottky (JBS) diode (SGS-ATMOS) is proposed for the first time. The shielding effect provided by the SG structure not only reduces the gate-drain capacitance ( ${C}_{\mathrm{gd}}$ ) but also alleviates the electric field crowding in the dielectric layer at trench corner. The integrated trench

A modified NMOS inverter employing output feedback theme has been proposed in this paper. The feedback structure can guarantee high voltage output at a wider range of low voltage input. The proposed inverter and the conventional pseudo-CMOS inverter are both fabricated by top gate coplanar In-Zn-O thin film transistors (IZO TFTs) for comparing. The experimental results show that the proposed inverter

Currently, low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), which are characterized by high mobility of electrons, are fabricated by excimer laser annealing. High mobility in low-temperature polycrystalline silicon is achieved by controlling the grain size to approximately 300 nm. However, with future potential growth of active-matrix organic light-emitting diodes in terms

Negative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device $V_{t}$ menu enablement. Contrary to conventional MOSFET design, increased junction overlap is beneficial to NCFETs, provided the remnant polarization ( $P_{r}$ ) is high enough. Combining broad junctions with complementary capacitance

In this study, p-GaN HEMTs with an indium-tin-oxide (ITO) electrode fabricated on the two different Mg concentration, i.e., $1 \mathbf {\mathrm {\times }} 10 ^{19}$ cm −3 and $8 \mathbf {\mathrm {\times }} 10 ^{19\,\,}$ cm −3 ,in p-GaN layer are investigated for the first time under the forward gate bias to understand the stability of the forward gate bias breakdown and ${\mathrm {V}}_{TH}$ shift stability

Redox-based random-access memory (ReRAM) has the potential to successfully address the technological barriers that today’s memory technologies face. One of its promising features is its fast switching speed down to 50 ps. Identifying the limiting process of the switching speed is, however, difficult. At sub-nanosecond timescales three candidates are being discussed: An intrinsic limitation, being the

A self-aligned fabrication process for top-gate amorphous zinc-tin oxide (a-ZTO) thin-film transistors (TFTs) is developed, in which the source/drain (S/D) doping is realized through depositing a thin aluminum (Al) film on S/D regions and performing a thermal annealing. Results indicate that a chemical oxidation-reduction reaction between Al and a-ZTO films takes place during the thermal annealing

The electrical performance of Z 2 -FET and memory operations of matrix are demonstrated at high temperatures up to 125 °C. The sharp subthreshold slope is maintained and the reliable operation is ensured within the memory window of 229 mV even though the turn on voltage of ‘0’- and ‘1’-states are shifted to lower voltage. The ‘0’-state current remains low while the ‘1’-state current gradually increases

We put forward a non-contact method for determining the transient two-dimensional (2D) temperature distribution of light emitting diodes (LEDs). A high-speed camera is employed to acquire the 2D reflective light of blue LED under test (468 nm) illuminated by a red LED (690 nm) as the incident light source to avoid the band-gap modulation effect. The 2D transient temperature distribution is derived

Resistive switching random access memory (RRAM) shows its potential to be a promising candidate as the basic in-memory computing unit for deep neural networks (DNN) accelerator design due to its non-volatile, low power, and small footprint properties. The RRAM based crossbar array (RRAM CBA) is usually employed to accelerate DNN because of its intrinsic characteristic of executing multiplication-and-accumulation

Constant-voltage time-dependent dielectric breakdown (TDDB) measurements are performed on recently manufactured commercial 1.2 kV 4H-SiC power metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs) from three vendors. Abrupt changes of the electric field acceleration parameters ( $\gamma $ ) are observed at oxide electric fields ( $E_{ox}$ ) around 8.5 MV/cm to 9 MV/cm for all commercial

Early retention or initial threshold voltage shift (IVS) is one of the key reliability challenges in charge trapping memory (CTM) based 3D NAND flash. Re-program scheme was introduced in quad-level-cell (QLC) NAND (Shibata et al. , 2007, Lee et al. , 2018, Shibata et al. , 2019, and Khakifirooz et al. , 2021), and the IVS improvement by re-program scheme was reported. In this work, it is found that

The failure behavior and the corresponding physical mechanism of the AlGaN/GaN high electron mobility transistors (HEMTs) under transmission line pulse (TLP) stress were investigated in this paper. The result shows that the output and transfer characteristics of the AlGaN/GaN HEMTs after 90 cycles begin to degrade by comparing with the fresh ones under 40 V TLP voltage, and the gate leakage current

We present a systematic study of how graphitic carbon nitride (g-C 3 N 4 ) in combination with Al 2 O 3 can be used as a double dielectric to control threshold and flat band voltage in capacitance-voltage (C-V) characteristics of an a-IGZO metal-insulator-semiconductor (MIS) device fabricated on ITO substrate. We study temperature dependence of C-V characteristics for Al 2 O 3 based MIS structures

A highly sensitive piezoresistive tactile sensor combined with the thin-film transistors (TFTs) is produced in this letter. The sensor uses two-dimensional Ti 3 C 2 -MXenes as piezoresistive material which is one type of transition metal carbide, nitride and/or carbonitride with a lamellar structure. A voltage divider circuit is designed by connecting piezoresistive material with TFT technology. TFT

N-channel thin film transistors (TFTs) fabricated with hydrogenated low temperature polycrystalline silicon (LTPS) were exposed to ultraviolet (UV) radiation to a cumulative dose up to 16 J/cm 2 . The effect of radiation on the electrical characteristics of the devices was monitored after the irradiation steps and in a prolonged period after irradiation. The main monitoring parameter was the threshold

In this work, the influence of the acceptor-type trap on the threshold voltage and short-channel effect is analyzed and modeled for the short-channel GaN MOS-HEMT. Particularly, the analysis and modeling are carried out with the dependences of the traps’ ionization condition on the gate voltage and drain voltage considered. From the calculated results based on the proposed threshold voltage model,

We have systematically examined electrical characteristics of ultra-thin body (UTB) (111) Ge-on-insulator (GOI) n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) fabricated by the smart-cut process and have compared their electrical properties with those of (100) ones. The (111) GOI thickness was varied from 29.4 to 7.3 nm. The normal MOSFET operation of a 7.3 nm-thick (111)-oriented

This paper presents a single-event burnout (SEB) resistance method for 4H-SiC Junction Barrier Schottky Diode (JBS) under high bias voltage and linear energy transfer (LET) conditions. The method is validated via two-dimensional numerical simulations. The analysis and comparison of conventional 4H-SiC JBS and 4H-SiC Multi-Buffer Layer JBS (MBL-JBS) diodes verify the resistance tolerance of the latter

This paper presents an electrical characterization and a compact modeling of FD-SOI four-gate qubit MOS devices, carried out at room temperature and in linear regime. The main figures of merit are extracted from average drain current curves using Y – function method. Poisson solver-based simulations are performed to interpret the experimental data, in particular the influence among gates and the effective

Traditional lumped small signal equivalent circuit models of AlGaN/GaN metal oxide semiconductor high electron mobility transistors (MOS-HEMTs) are made up of constant valued circuit elements. Such models are unable to capture the high frequency behavior (above 20 GHz) of the device. In this work, a modified small signal equivalent circuit model of AlGaN/GaN MOS-HEMTs is presented. The key feature

A new low-voltage power MOSFET is proposed to improve the figure-of-merits (FOMs) for power loss reduction. Slit field plate (Slit FP) structure is effective to cope with both the on-resistance $R_{on}$ A reduction and high speed switching due to flat electric field distribution and low gate density by the slit oxide. Therefore, Slit FP power MOSFET achieves better $R_{on}A-R_{on}$ $Q_{sw}$ and $R_{on}A-R_{on}$

The dynamic on-resistance increase during power switching is one of the challenges of GaN-based HEMTs (high-electron-mobility transistors) for power electronic applications. Both the surface traps and buffer traps reduce channel carriers, resulting in decreased operating current during power switching. In this work, we propose a source metal trench toward the buffer region to alleviate channel carriers’

For dense very large scale integration (VLSI) of high performance, multibit resistive memory (RRAM), scalability of material dimensions, as well as the operational sensitivity of the RRAM to voltage fluctuations, have to be considered. This report presents the benefits of adding 0.5-nm thick AlO x diffusion barriers at the different electrode interfaces of HfO x . It is found that implementing AlO

AC positive bias temperature instability (PBTI) of germanium nMOSFETs with GeO 2 /Ge and Si-cap/Ge gate stack was investigated in this brief. AC-DC-AC alternating PBTI stress tests were conducted on both types of devices, the experiment data shows the inserted DC stress phase has little impact on the following AC stress kinetics on GeO 2 /Ge nMOSFETs but introduce a significant “additional DC generation”

A discrete GaN power transistor’s substrate is typically connected to its source electrode. However, on the GaN-on-Si power IC platform, the high-side transistor (HS-transistor) and low-side transistor (LS-transistor) share a common substrate that cannot be simultaneously connected to both source electrodes of the two transistors. Thus, the termination of the common substrate remains an undecided issue

The wide bandgap material, Gallium Nitride (GaN), has emerged as the dominant semiconductor material to implement high-electron mobility transistors (HEMTs) that form the basis of RF electronics. GaN is also an excellent material to realize photoconductive switches (PCSS) whose high-frequency performance could exceed that of RF HEMTs. In this paper, we numerically model the output characteristics of

A thin-film transistor (TFT) integrated gate driver is proposed for compact in-cell touch display, where one capacitor is reused for both turning on low-level maintaining transistors via voltage coupling and maintaining the re-start charge during the touch sensing period. The gate terminal of buffer transistor is thus free of electrical stress during touch sensing period, and can be re-charged for

In the fierce market competition of different biometric methods in smartphones, where consumers are pursuing a high screen ratio, optical fingerprint recognition under OLED screen is a well-established approach. However, using thin-film transistor (TFT) technology to make large-area optical sensors generally has the issue of low sensitivity, which will make the signal difficult to be read out. In this

1/f noise provides essential information on the interface trapping effect as well as the scattering mechanism in transistors. In this work, a systematic 1/f noise study has been carried out on the recessed-gate enhancement-mode (E-mode) GaN MOS-HEMTs under electrical and thermal stress together with the depletion-mode (D-mode) counterpart. Low-frequency (1–1000 Hz) measurement has been performed at

A phenomenological model, accounting for interface states at metal-semiconductor contacts, is proposed to explain particular gate-bias-dependent kinking in I-V characteristics sometimes observed in MoS 2 FETs. The effect is studied in double-gate FETs by varying top-gate voltage (V TG ) and bottom-gate voltage (V BG ), with the MoS 2 semiconductor layer overlying source/drain (S/D) metal contacts in

This Special Issue is devoted to research and development in the field of electron devices science and technology. We have selected a number of high quality papers presented at the $2^{nd}$ Latin American Electron Device Conference (LAEDC 2020). The $2^{nd}$ LAEDC was held in San Jose, Costa Rica from the $25^{th}$ to 28 February, 2020 and was sponsored by the IEEE Electron Devices Society.

As scaling of the feature size - the main driving force behind an outstanding increase of the performance of modern electronic circuits - displays signs of saturation, the main focus of engineering research in microelectronics shifts towards finding new paradigms. Any future solution must be scalable and energy efficient while delivering high performance, superior to that of CMOS-based circuits. In

Barrier height ( $\phi _{b}$ ), trap state, bandgap ( $E_{g}$ ), and band alignment information of the metal–ZrO 2 –metal capacitor have been extracted using internal photoemission (IPE) system. By correlating the IPE analysis with I-V and C-V characteristics obtained before and after rapid thermal annealing, origin and transformation of defect states have been successfully investigated. Our analysis

In recent years the Journal of the Electron Device Society (J-EDS) has experienced an increasing number of submissions of “simulation only” manuscripts. One reason for this is the improved accuracy and maturity of physicsbased simulation tools, either Technology Computer Aided Design (TCAD) or circuit analysis programs, that allow researchers to explore, devise and optimize the best breakthroughs going

The diamond-like carbon (DLC) is important for passivation of junction termination in high power devices due to its excellent electrical, mechanical, and thermal properties. While the role of conductivity and polarization of the DLC layer on the blocking capability of a p-n junction has been explained recently, the thermal behavior still needs to be addressed. For this purpose, the diode leakage current

This paper describes the influence of Longitudinal Corner Effect (LCE effect) and PArallel Connection of Metal–Oxide–Semiconductor Field-Effect Transistors (MOSFETs) with Different Channel Lengths Effect (PAMDLE effect) of Diamond (hexagonal gate shape) MOSFET in different Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) technologies (180nm-Bulk and $1\mu \text{m}$ -Silicon-On-Insulator

In this work, the properties of gallium oxide (Ga 2 O 3 ) and its excellent interface properties to GaN-based materials are explored as a gate insulator layer for GaN-based metal-oxide-semiconductor high-electron mobility transistors (MOSHEMTs). A novel vapor cooling condensation system was used to deposit the high quality Ga 2 O 3 films with high insulation and low defect suitable for gate insulator

Three-Independent-Gate Field-Effect Transistors (TIGFETs) are a promising alternative technology that aims to replace or complement CMOS at advanced technology nodes. In this paper, we extracted the parasitic and intrinsic capacitances of a silicon-nanowire TIGFET device using three-dimensional numerical simulations in an attempt to accurately compare its capacitances and, consequently, circuit-level

A novel low loss lateral insulated gate bipolar transistor (LIGBT) with high voltage level is designed and studied in this paper, and is proposed with assisted depletion N-region (AD) and P-buried layer (PB) in the bulk Si substrate, named PBAD LIGBT. The proposed PBAD LIGBT utilizes the idea of electric field modulation (EFM) to greatly improve the breakdown voltage, which optimizes the lateral and

In this paper, a new modeling technique is proposed for extracting small-signal lumped-element equivalent-circuit models for microwave transistors. The proposed procedure is based on using an optimization approach that is improved by targeting a quasi-static behavior as additional objective function rather than only minimizing the error between the simulated and measured scattering parameters. The

This paper presents the calibration of the novel kinetic velocity model (KVM) in the drift-diffusion (DD) transport approach, which can account for the ballistic effect in short-channel devices. The KVM considers a thermionic emission limit and a free carrier acceleration limit for the mobility. We develop a methodology to extract the parameters for the KVM and for the high-field saturation velocity

The paper presents the design and fabrication of lateral-field-excited (LFE) resonators based on 42° Y-cut single-crystal LiTaO 3 (LT) on silicon dioxide (SiO 2 ). A simple coplanar top electrode is defined to excite the bulk acoustic wave modes in the suspended LT/SiO 2 structure, and the fabrication process that only involves two lithography steps is more simplified compared to that of commercial

In this work, a L-shaped tunnel FET (TFET), which has the dominant tunneling current in the normal direction to the gate, is introduced with the doping engineering and its electrical characteristics are analyzed using TCAD device simulations. The proposed L-shaped TFET has the pocket doping (p + -doping for n-type operations) underlying the gate, which can suppress the corner tunneling generated near

This work proposes a mini-LED driving circuit that adopts the pulse-width modulation (PWM) driving method for use in a liquid-crystal display (LCD) backlight. The proposed circuit can compensate for the threshold voltage ( $\text{V}_{\mathrm{ TH}}$ ) variation in a low-temperature poly-crystalline silicon thin-film transistor (LTPS TFT) and a VSS current-resistance (I-R) rise, to generate a stable

In this study, we report high-performance amorphous Ga 2 O 3 metal-oxide (AMO) thin film transistor (TFT) using an low-temperature solution-process coupling with In alloy engineering. In doping can lower the activation temperature of gallium oxide and increase the oxygen vacancy concentration to further activate the device. The optical bandgap of IGO film can be changed from 5.3 to 4.25 eV with the

In this study, in-situ MOCVD-grown SiN/AlN/Al 0.05 Ga 0.95 N HEMTs were fabricated using ALD-Al 2 O 3 /PECVD-SiO 2 passivation. A high on/off current ratio of 10 9 and a low subthreshold swing of 64 mV/dec are achieved. The interface traps in the SiN/AlN/Al 0.05 Ga 0.95 N structure are investigated using frequency-dependent capacitance-voltage and conductance measurements. The shift in threshold voltage

In this paper, we have proposed a simple and zero-cost technique to improve ON-state and reliability performance of LDMOS transistors. We introduced doping gradient in the channel by optimizing position of the P-Well mask during test structure design/layout. Through proper device design, fabrication and measurement on different test structures, we have shown that the graded channel significantly improves

This paper presents a common-drain-based operational amplifier (OPAMP) fabricated by mono n-type indium-zinc-oxide (IZO) thin-film transistors (TFTs). Positive feedback technology is employed to the load TFTs by cross-coupled connection in order to boost the voltage gain of the common-drain differential pair. The OPAMP exhibits an open-loop voltage gain (A v ) of 27 dB over a −3 dB bandwidth (BW) of

A power MOSFET with P-base Schottky diode and built-in channel diode is proposed and numerically investigated in this article. The P-base Schottky diode formed by the P-base Schottky contact is in reverse series with the P-base/N-drift junction diode. Besides, by coupling the gate of the dummy MOSFET to the source, a built-in channel diode is introduced, which provides a unipolar reverse conduction

White light-emitting diodes (WLEDs) with a visible uniform spectral power distribution (SPD) were fabricated by integrating a blue LED chip and a phosphor-in-silicone (PiS)/phosphor-in-glass (PiG) stacked package. After adjusting the doping concentrations of phosphors (cyan, green and red) in the silicone encapsulant, the PiS was dispensed in the cavity of lead frame already bonded with a blue LED

In this article, we propose a novel real-time threshold voltage ( $V_{th}$ ) compensation method for AM-OLED display. The proposed method predicts $V_{th}$ shift of driving thin-film transistors (TFTs) based on the equation derived from the sensing line charging with TFT’s drain current. The prediction equation requires two consecutive source node voltages to consider the mobility variation, and only

Etched-and-regrown GaN pn-diodes capable of high breakdown voltage (1610 V), low reverse current leakage (1 nA = 6 $\mu \text{A}$ /cm 2 at 1250 V), excellent forward characteristics (ideality factor ~1.6), and low specific on-resistance (1.1 $\text{m}\Omega $ .cm 2 ) were realized by mitigating plasma etch-related defects at the regrown interface. Epitaxial ${n}$ -GaN layers grown by metal-organic

Experimental results obtained for 2.3 kV SiC planar-gate power JBSFETs with different cell topologies are analyzed in this article using analytical models and numerical simulations. All the accumulation-channel devices were simultaneously manufactured in a 6-inch commercial foundry with channel length of 0.5 $\mu \text{m}$ and gate oxide thickness of 55 nm. The Schottky contact width was chosen to

We investigated the impact of a sulfur passivation (S-passivation) process step on carrier transport properties of surface-channel In 0.7 Ga 0.3 As quantum-well (QW) Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) with source/drain (S/D) regrowth contacts. To do so, we fabricated long-channel In 0.7 Ga 0.3 As QW MOSFETs with and without (NH 4 ) 2 S treatment prior to a deposition of Al

ON-state conductance properties of vertical GaN ${n}$ -channel trench MISFETs manufactured on different GaN substrates and having different gate trench orientations are studied up to 200 °C ambient temperature. The best performing devices, with a maximum output current above 4 kA/cm 2 and an area specific ON-state resistance of 1.1 $\text{m}\Omega \cdot $ cm 2 , are manufactured on ammonothermal GaN

In this article, we present an experimental study on the impact of post-metallization annealing conditions on the negative-bias temperature instability (NBTI) of Si p-channel fin field-effect transistors (p-FinFETs) with atomic layer deposition tungsten (ALD W) as the gate-filling metal. The effects of annealing conditions on the tensile stress of the W film, impurity element concentration in the gate

This study investigates a device’s ability to boost its on-state current and subthreshold behavior using a ferroelectric field-effect transistor (FeFET) with an ultrathin sub-5-nm Hf 1-x Zr x O2 (HZO). A conventional field-effect transistor (FET) with pure hafnium (HfO 2 ) is used as a control measure and the impact of an internal metal gate (IMG) is also discussed. The study was conducted by using

From our other works, we have developed urea biosensor based on graphene oxide/nickel oxide sensing film modified either by Au nanoparticles or ${\gamma }$ -Fe 2 O 3 nanoparticles. In this study, we have further developed back-end calibration circuit to reduce the drift effect and hysteresis effect of the two types of the urea biosensors. The back-end calibration circuit is composed of non-inverting