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Table of contents IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2021-01-25
Presents the table of contents for this issue of the publication.
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Editorial IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2021-01-21 Enrico Sangiorgi
The Journal of Electron Devices Society (J-EDS) was founded in 2013 and grown up very robustly since then.
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Golden List of Reviewers for 2020 IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-12-30
Presents the reviewers who contributed to this publication in 2020.
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Foreword Special Issue on Compact Modeling of Semiconductor Devices IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-12-08 Benjamin Iñiguez; Yogesh Singh Chauhan; Slobodan Mijalkovic; Kejun Xia; Jung-Suk Goo; Marcelo Pavanello; Marek Mierzwinski; Wladek Grabinski
This Special Issue is dedicated to recent research in the field of compact modeling of semiconductor devices. This is the first J-EDS Special Issue on compact modeling. In the last years, a number of new semiconductor device structures, for electronic and photonic applications, have been developed. Compact models are needed for the incorporation of these new devices in integrated circuits. Therefore
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THz Characterization and Modeling of SiGe HBTs: Review (Invited) IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-11-05 Sebastien Fregonese; Marina Deng; Marco Cabbia; Chandan Yadav; Magali De Matos; Thomas Zimmer
This article presents a state-of-art review of on-wafer S-parameter characterization of THz silicon transistors for compact modelling purpose. After, a brief review of calibration/de-embedding techniques, the paper focuses on the on-wafer calibration techniques and especially on the design and dimensions of lines built on advanced silicon technologies. Other information such as the pad geometry, the
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Compact Modeling of Multi-Gate MOSFETs for High-Power Applications IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-10-21 F. Ávila Herrera; Y. Hirano; M. Miura-Mattausch; T. Iizuka; H. Kikuchihara; H. J. Mattausch; A. Ito
A compact multi-gate MOSFET model is developed for high-voltage applications. The model includes the short-channel effects specific for thin-film MOSFETs with highly resistive drain contact. The short-channel effects are drastically reduced by the drain-resistance effect, which is consistently modeled by considering the whole potential distribution along the device. The overlap length is an important
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Methodology to Investigate Impact of Grain Orientation on Threshold Voltage and Current Variability in Tunneling Field-Effect Transistors IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-10-23 Jang Hyun Kim; Tae Chan Kim; Garam Kim; Hyun Woo Kim; Sangwan Kim
In this article, an investigation has been performed to statistically analyze the entire subthreshold characteristics of tunnel field-effect transistor (TFET) depending on a gate work function variation (WFV). Firstly, the current variations are evaluated through turn-on voltage ( ${V} _{\mathrm{ ON}}$ ) and threshold voltage ( $V_{T}$ ) with help of technology computer-aided design (TCAD) simulation
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Enhanced Non-Uniformity Modeling of 4H-SiC Schottky Diode Characteristics Over Wide High Temperature and Forward Bias Ranges IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-10-21 Gheorghe Brezeanu; Gheorghe Pristavu; Florin Draghici; Razvan Pascu; Francesco Della Corte; Simone Rascuna
A practical model, adequate for full reproduction of inhomogeneous Schottky diodes’ forward characteristics over wide high-temperature and bias ranges, is proposed. According to this ${p}$ -diode model, the Schottky contact current is considered to flow through ${m}$ parallel-connected internal diodes, each with stable, constant barrier height and specific series resistance (both main model parameters)
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Asymmetric Low Metal Contamination Ni-Induced Lateral Crystallization Polycrystalline-Silicon Thin-Film Transistors With Low OFF-State Currents for Back-End of Line (BEOL) Compatible Devices Applications IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-10-14 Po-Yi Kuo; Shao-Chi Lo; Hsiu-Hsuan Wei; Po-Tsun Liu
In this work, polycrystalline-silicon thin-film transistors (poly-Si TFTs) with asymmetric low metal contamination Ni-induced lateral crystallization (LC-NILC) poly-Si channel and high- $\kappa $ HfO 2 gate insulator (GI) have been successfully fabricated and demonstrated for the first time. The amounts of Ni diffused into the poly-Si film can be effectively reduced by Ni removal processes prior to
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3D Simulation for Melt Laser Anneal Integration in FinFET’s Contact IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-10-14 Toshiyuki Tabata; Benoit Curvers; Karim Huet; Soon Aik Chew; Jean-Luc Everaert; Naoto Horiguchi
Process integration feasibility of UV nanosecond melt laser annealing (MLA) in 14 nm node generation FinFET’s contact for dopant surface segregation and activation is assessed by using a 3D TCAD simulation tool. In a n-type source/drain (S/D) in-situ phosphorous doped epilayer, Sb ion implantation is performed, considering the advantage of its surface segregation in lowering of the contact resistivity
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Using the MSET Device to Counteract Power-Analysis Attacks IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-10-20 Assaf Peled; Liron David; Ofer Amrani; Yossi Rosenwaks; Avishai Wool
One pivotal countermeasure in dealing with side-channel power analysis attacks is to maintain the signal-to-noise ratio of the power readings associated with the target as data-independent and as low as possible, in order to limit the attacker’s ability to deduce meaningful information from the target. The following study shows that the MSET (Multiple-State Electrostatically-Formed Nanowire Transistor)
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Simulative Researching of a 1200V SiC Trench MOSFET With an Enhanced Vertical RESURF Effect IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-10-26 Han Yang; Shengdong Hu; Shenglong Ran; Jian’an Wang; Tao Liu
A SiC trench MOSFET with an enhanced vertical RESURF effect is proposed and analyzed in this article. The device features a deep oxide trench surrounded by a P-type doping layer at the source-side. With the assistant depletion effect of the P-type layer, the concentration of the N-drift region is increased and the specific on-resistance ( ${R} _{\mathrm{ on,sp}}$ ) is thus reduced. The P-type doping
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Note Clarifying the Paper, “Charge Sheet Super Junction in 4H-Silicon Carbide: Practicability, Modeling and Design” IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-10-19 K. Akshay; Shreepad Karmalkar
This note clarifies an important approximation used to simulate the breakdown field in the SiO 2 liner of a SiC Charge-Sheet Superjunction - a new power device structure - reported by Akshay and Karmalkar (2020). This electric field simulation sought to assure that the new device does not suffer from SiO 2 reliability problems. The note answers two questions: (a) Why do we remove the SiO 2 liner which
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Foreword Special Issue From the Selected Extended Papers Presented at EDTM 2020 IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-11-03 Samar K. Saha; Arokia Nathan; P. Susthitha Menon; Jagadheswaran Rajendran; Asrulnizam Bin Abd Manaf; Leong Wai Yie
This Special Issue is assembled from a selection of highly-rated technical papers presented at the 4 th IEEE Electron Devices Technology and Manufacturing Conference 2020, EDTM 2020. It took place during April 6-21, 2020 and signified the 1 st of its kind as a virtual conference financially-sponsored by the Electron Devices Society (EDS). The original EDTM 2020 was planned as a full three-day event
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Performance Modeling of Silicon Carbide Photoconductive Switches for High-Power and High-Frequency Applications IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-07 S. Rakheja; L. Huang; Stefan Hau-Riege; S. E. Harrison; Lars F. Voss; Adam M. Conway
In this article, we focus on the physical modeling of the nonlinear operation of intrinsic photoconductive semiconductor switches (PCSS) based on 4H-SiC using coupled electrical and optical simulations to provide performance bounds of the switch as a function of material and geometry parameters, as well as applied bias. We also conduct a full design-space exploration to identify the optimal operating
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Charge Sheet Super Junction in 4H-Silicon Carbide: Practicability, Modeling and Design IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-04 K. Akshay; Shreepad Karmalkar
We discuss details of the Charge Sheet SuperJunction (CSSJ) in 4H-Silicon Carbide (SiC). This device was earlier proposed in Si material. A CSSJ is obtained by replacing the p-pillar of a SJ by a bilayer insulator, e.g., Al 2 O 3 /SiO 2 ; the inter-layer interface of this insulator has a negative charge-sheet, whose magnitude is easily controlled via the insulator deposition temperature. This charge-sheet
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Quasi-Normally-Off AlGaN/GaN HEMTs With SiNₓ Stress Liner and Comb Gate for Power Electronics Applications IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-08-28 Wei-Chih Cheng; Fanming Zeng; Minghao He; Qing Wang; Mansun Chan; Hongyu Yu
Recess processes for the fabrication of normally-off GaN HEMTs generally compromise devices’ on-state performance. In this work, recess-free quasi-normally-off GaN HEMTs with a threshold voltage of 0.24 V is realized by local control of two-dimensional electron gas (2DEG) density. The devices feature a $0.1~{\mu }\text{m}$ gate length, SiN x stress liner, and comb gate. SiN x liner can provide significant
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Efficient Modeling of Barrier Resistance for an Improved Lumped Element Model of GaN-Based MIS-HEMT Gate Stack IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-18 Narendra Rai; Ashutosh Mahajan; Dipankar Saha; Swaroop Ganguly
A methodology has been proposed to accurately model the gate stack of Gallium Nitride (GaN) based metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs). Small-signal analysis has been performed for the device biased in the spill-over region, where electrons accumulate at the insulator/III-Nitride ’critical’ interface. Accounting for the barrier layer resistance with an accurate
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Effect of Nanostructure on Carrier Transport Mechanism of III-Nitride and Kesterite Solar Cells: A Computational Analysis IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-22 S. Routray; K. P. Pradhan; G. P. Mishra
In this work, the computational analysis on use of nanostructures to both III-Nitride and Kesterite solar cell are presented and compared. The scope behind the comparative analysis of III-nitride and kesterite material based solar cells is due to their excellent material properties, which made them suitable as an absorber for solar cells. In III-nitride based solar cells, stress induced polarization
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Compact Modeling of Multi-Layered MoS2 FETs Including Negative Capacitance Effect IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-01 Keshari Nandan; Chandan Yadav; Priyank Rastogi; Alejandro Toral-Lopez; Antonio Marin-Sanchez; Enrique G. Marin; Francisco G. Ruiz; Somnath Bhowmick; Yogesh S. Chauhan
In this article, we present a channel thickness dependent analytical model for MoS 2 symmetric double-gate FETs including negative capacitance (NC) effect. In the model development, first thickness dependent model of the baseline 2D FET is developed, and later NC effect is included in the model using the Landau-Khalatnikov (L-K) relation. To validate baseline model behavior, density functional theory
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Comparison of LER Induced Mismatch in NWFET and NSFET for 5-nm CMOS IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-24 Chandan Kumar Jha; Pritam Yogi; Charu Gupta; Anshul Gupta; Reinaldo A. Vega; Abhisek Dixit
Nanosheet field-effect transistors (NSFETs) have emerged as a novel device replacement for sub-7nm CMOS technology nodes. However, due to smaller fin thickness (Tfin = 5nm), NSFETs are more vulnerable to the process-induced variations. Among various types of process-induced variations, Line edge roughness (LER) is becoming a significant concern for multi-gate field-effect transistors (MugFETs) with
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Impact of Interface Traps on Negative Capacitance Transistor: Device and Circuit Reliability IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-07 Om Prakash; Aniket Gupta; Girish Pahwa; Jörg Henkel; Yogesh S. Chauhan; Hussam Amrouch
In this work, we investigate the impact of Si-SiO 2 interface traps on the performance of negative capacitance transistor, which is a promising emerging technology that aims at achieving a steep sub-threshold slope. Interface traps induced degradation is well known to be one of the major concerns when it comes to reliability. We focus on investigating the impact of different interface trap concentrations
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Heterostructure Ge-Body pTFETs for Analog/RF Applications IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-21 Sayani Ghosh; Kalyan Koley; Samar K. Saha; Chandan K. Sarkar
This article presents a systematic study on the analog and radio-frequency (RF) performance of type-II staggered heterostructure ${p}$ -channel tunnel field-effect transistors ( ${p}$ TFETs) with Ge (Germanium) channel and different compound semiconductor source. In order to study the figure-of-merits (FOMs) of analog and RF performances, various Ge-channel ${p}$ TFETs are designed with Ge, GaAsP,
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A CMOS Low Power Current Source Tunable Inductor With 80% Tuning Range for RFIC IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-10 Selvakumar Mariappan; Jagadheswaran Rajendran; Shahrolhafiz S. Ibrahim; Sofiyah S. Hamid; Yusman M. Yusof; Norlaili M. Noh; Subhash C. Rustagi; Arjun K. Kantimahanti
This article describes a novel Low Power Current Source Tunable Inductor (LPCSTI) for CMOS Radio Frequency Integrated Circuits (RFIC). The LPCSTI comprises a deep triode common source transistor, a stabilizer resistor and a coupling capacitor which is capable to increase the physical inductance value up to 80% from its default value thus achieving higher inductance per area. Integration of the tuner
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Printable Low Power Organic Transistor Technology for Customizable Hybrid Integration Towards Internet of Everything IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-08-28 Yukun Huang; Wei Tang; Linrun Feng; Sujie Chen; Jiaqing Zhao; Zhe Liu; Lei Han; Bang Ouyang; Xiaojun Guo
A highly customizable hybrid sensor system, composed of a silicon integrated circuit (IC) chip and an organic field effect transistor (OFET) transducer, is proposed for Internet of Everything (IoE). In such a system, the silicon IC chip performs high performance and complex signal processing, and the OFET transducer provides flexible or conformable large area coverage and more friendly interfaces to
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Multilayer CVD-Graphene and MoS₂ Ethanol Sensing and Characterization Using Kretschmann-Based SPR IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-07 P. Susthitha Menon; Nur Akmar Jamil; Gan Siew Mei; Ahmad Rifqi Md Zain; Daniel W. Hewak; Chung-Che Huang; Mohd Ambri Mohamed; Burhanuddin Yeop Majlis; Ravi K. Mishra; Srinivasan Raghavan; Navakanta Bhat
The Kretschmann-based surface plasmon resonance (K-SPR) sensor was developed using multilayer graphene and molybdenum disulphide (MoS 2 ) structures on a plasmonic gold (Au) layer for ethanol detection. In this configuration, the SPR spectra of minimum reflectance versus SPR angle was used to determine the sensitivity, detection accuracy and quality factor as the main figure of merit (FOM). Both graphene
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Subthreshold Operation of Photodiode-Gated Transistors Enabling High-Gain Optical Sensing and Imaging Applications IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-08 Kai Wang; Yihong Qi; Yunfeng Hu; Yangbing Xu; Yitong Xu; Jinming Liu; Xianda Zhou
In optical sensors and imagers, high gain that leads to high sensitivity and high signal to noise ratio (SNR) is often desirable. One popular approach is avalanche photomultiplication initiated by impact ionization in an avalanche photodiode or similar devices and the other approach is active pixel sensor (APS) with in-pixel amplifier. However, the former requires high electric field which induces
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Under-FET Thermal Sensor Enabling Smart Full-Chip Run-Time Thermal Management IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-08 Cheng Li; Qi Chen; Feilong Zhang; Mengfu Di; Zijin Pan; Fei Lu; Albert Wang
This article reports design, fabrication and analysis of a novel under-transistor (under-FET) in-hole thermal sensor diode structure. Being able to accurately monitor self-heating of individual transistor in-operando, the under-FET temperature sensor enables smart full-chip run-time thermal management with spatial resolution down to single transistor level. The in-hole thermal sensors were fabricated
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Analysis of Switching Under Fixed Voltage and Fixed Current in Perpendicular STT-MRAM IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-11 S. Fiorentini; R. L. de Orio; S. Selberherr; J. Ender; W. Goes; V. Sverdlov
In spin-transfer torque magnetoresistive random access memory, the magnetization dynamics of a free layer is usually assumed to be determined by the torque created via a position-independent current density. In circuits, however, it is the voltage, not the current density, which stays fixed during switching. Therefore, the approximate evaluation of the torque based on a fixed current density becomes
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Generation of STDP With Non-Volatile Tunnel-FET Memory for Large-Scale and Low-Power Spiking Neural Networks IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-21 Hisashi Kino; Takafumi Fukushima; Tetsu Tanaka
Spiking neural networks (SNNs) have attracted considerable attention as next-generation neural networks. As SNNs consist of devices that have spike-timing-dependent plasticity (STDP) characteristics, STDP is one of the critical characteristics we need to consider to implement an SNN. In this study, we generated the STDP of a biological synapse with non-volatile tunnel-field-effect-transistor (tunnel
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Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC Applications IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-08 Hyeok Yun; Jun-Sik Yoon; Jinsu Jeong; Seunghwan Lee; Hyun-Chul Choi; Rock-Hyun Baek
In this article, by using neural network, we proposed a method to optimize Fully-Depleted (FD) Silicon-on-Insulator (SOI) Field-Effect-Transistor (FET) structures to maximize the on/off current ratio for 14-nm node (70-nm Gate Pitch) System-on-Chip (SoC) and sequential 3-dimensional integrated circuit (3DIC). Using machine learning method, the neural network accurately predicted the electrical behaviors
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Modeling of DC - AC NBTI Stress - Recovery Time Kinetics in P-Channel Planar Bulk and FDSOI MOSFETs and FinFETs IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-14 Nilotpal Choudhury; Narendra Parihar; Nilesh Goel; A. Thirunavukkarasu; Souvik Mahapatra
The physics-based BTI Analysis Tool (BAT) is used to model the time kinetics of threshold voltage shift ( $\Delta {\mathrm{ V}}_{\mathrm{ T}}$ ) during and after NBTI in p-channel planar bulk and FDSOI MOSFETs and SOI FinFETs. BAT uses uncorrelated contributions from the trap generation at the channel/gate insulator interface ( $\Delta {\mathrm{ V}}_{\mathrm{ IT}}$ ) and gate insulator bulk ( $\Delta
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3D TCAD Analysis Enabling ESD Layout Design Optimization IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-28 Zijin Pan; Cheng Li; Mengfu Di; Feilong Zhang; Albert Wang
On-chip electrostatic discharge (ESD) protection design for integrated circuits (ICs) is a challenging design-for-reliability problem. Since ESD events involve very high current transients in very short time period, current crowding is unavoidable, which leads to local overheating and creates local hot spots, resulting in ESD thermal failures. Therefore, layout design plays a critical role in practical
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Pad-Based CDM ESD Protection Methods Are Faulty IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-08 Mengfu Di; Cheng Li; Zijin Pan; Albert Wang
Charged device model (CDM) electrostatic discharge (ESD) protection remains a huge challenge for integrated circuit (IC) reliability designs. The “internal-oriented” CDM model and the “external-oriented” human body model (HBM) describe fundamentally different ESD phenomena. Through the comprehensive analysis, this article concludes that the classic pad-based ESD protection methods, commonly used for
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Understanding and Improving Reliability for Wafer Level Chip Scale Package: A Study Based on 45nm RFSOI Technology for 5G Applications IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-09 Zhuo-Jie Wu; Haojun Zhang; John Malinowski
Wafer level chip scale package (WLCSP) is true chip scale package with low cost by eliminating package substrate. The direct chip-to-board attach through solder joints provides low interconnect inductance and resistance, as well as improved thermal performance. These properties make WLCSP a packaging format well suited for 5G radio frequency (RF) applications where minimized package size and parasitics
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Simulation Study on Dynamic and Static Characteristics of Novel SiC Gate-Controlled Bipolar-Field-Effect Composite Transistor IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-08 Yipan Zhang; Baoxing Duan; Yintang Yang
In this article, a novel bipolar-field-effect composite power transistor, called SiC GCBT (Silicon Carbide Gate-Controlled Bipolar-field-effect Composite Transistor) is presented and studied. The structure is characterized by the use of the base-gate short connection mode, instead of the conventional base-source short connection mode in SiC Vertical Double-diffusion MOSFET (VDMOS). It found that the
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Realization of an IGBT Gate Driver With Dualphase Turn-On/Off Gate Control IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-10-15 You-Da Chen; Albert Chin
Adding passive components in a conventional IGBT gate driver is a simple method to reduce transient current/voltage spikes during switching, but the extra devices and power loss make them less attractive. Alternatively, active gate drivers can improve the switching behavior, but are limited to specific devices and applications from the increased complexity of functions and feedback topology. This article
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Ionization Damage Effects of Pulse Discharge Circuit Switched by Anode-Short MOS-Controlled Thyristor IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-10-14 Lei Li; Ze-Hong Li; Jin-Ping Zhang; Yu-Zhou Wu; Xiao-Chi Chen; Min-Ren; Bo Zhang; Yuan Jian
The MOS-controlled Thyristor (MCT) has been characterized by MOS-gating, high current rise rate, and high blocking capabilities. The anode short MCT (AS-MCT) is distinguished from the conventional MCT by an anode-short structure, which forms an extracting path for the leakage current at the gate-ground and develops a normally-off characteristic. The AS-MCTs are ideal switches for pulse discharge application
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Impact of Series-Connected Ferroelectric Capacitor in HfO₂-Based Ferroelectric Field-Effect Transistors for Memory Application IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-10-07 Wei-Dong Liu; Zi-You Huang; Jun Ma; Zhi-Wei Zheng; Chun-Hu Cheng
In this work, we demonstrated a HfO 2 -based ferroelectric field-effect transistor (FeFET) in series with a HfAlO ferroelectric capacitor for memory application and further investigated the impact of the ferroelectric capacitor with different thicknesses and areas. It was revealed that the memory window of the FeFET has a significant correlation with the ferroelectric capacitor from the transfer curves
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Investigation of THz Frequency Shaped Anode Planar Gunn Diodes Operating in Delayed Mode IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-10-06 Ahmed Mindil; Geoffrey Dunn; Ata Khalid; Chris Oxley
A novel planar design of Gunn diode with a shaped anode contact, utilizing Monte Carlo simulations, has been shown to have produced 0.3 THz frequency current output when operated in delayed mode. Two novel anode designs are investigated here, one with two fixed distances, and the other with three fixed distances between the cathode and anode electrodes. The corresponding waveforms generated, show two
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Analytical Modeling of Exposure Process in Pinned Photodiode CMOS Image Sensors IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-24 Jing Gao; Yuchen Gong; Zhiyuan Gao; Kaiming Nie; Jiangtao Xu
The output features of pixels in CMOS image sensors (CISs) are influenced by different exposure conditions. This article presents an analytical model to describe the output characteristics of the exposure process in pinned photodiode (PPD) CMOS image sensors with the accumulation of three charge sources: photogenerated charge, p-n junction-generated charge, and emission charge. In the proposed model
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An Improved Self-Powered H-Bridge Circuit for Voltage Rectification of Piezoelectric Energy Harvesting System IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-21 Mahesh Edla; Yee Yan Lim; Mikio Deguchi; Ricardo Vasquez Padilla; Iman Izadgoshasb
In recent years, piezoelectric materials have been widely investigated for harvesting energy from ambient vibrations. A vibrating piezoelectric device (PD) generates alternating current (AC), which needs to be converted into direct current (DC) for powering electronic devices or for storage. A traditional full-wave bridge rectifier (FBR) interface circuit serves this purpose, but it suffers from high
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Analytical Study on the Breakdown Characteristics of Si-Substrated AlGaN/GaN HEMTs With Field Plates IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-18 Jianhua Liu; Yu-Feng Guo; Jun Zhang; Jiafei Yao; Maolin Zhang; Chenyang Huang; Ling Du
The breakdown voltage model of Si-substrated AlGaN/GaN HEMTs with gate and drain field plates is proposed in this work. The silicon substrate and GaN buffer are considered as the depletion region in the modeling process. The analytical model shows great simplicity and veracity. It gives physical insights into the breakdown characteristics of the AlGaN/GaN HEMTs. The avalanche breakdown occurs at the
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Electrical Characteristics of LDD and LDD-Free FinFET Devices of Dimension Compatible With 14 nm Technology Node IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-28 Yuchen Du; Md Khaled Hassan; Ri-an Zhao; Xinggong Wan; Manoj Joshi
FinFET devices with and without LDD implantation has been studied for dimensions compatible with leading 14nm technology node. Devices without LDD have better electrostatic characteristics with SS = 65mV/dec and DIBL = 33mV. The nFET transistors with no LDD have device Vtsat mismatch reduction by 20%, together with retained device reliability of HCI as compared to devices with LDD. A full range of
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Modeling the Displacement Damage on Trigger Current of Anode-Short MOS-Controlled Thyristor IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-21 Lei Li; Ze Hong Li; Yu Zhou Wu; Xiao Chi Chen; Jin Ping Zhang; Min Ren; Yuan Jian; Bo Zhang
The MOS-controlled Thyristor (MCT) has been characterized by MOS-gating, high current rise rate, and high blocking capability. The anode short MCT (AS-MCT) is distinguished from conventional MCT by an anode-short structure, which develops a normally-off characteristic. As a composite structure made of metal-oxide-silicon and bipolar junction transistors, AS-MCT is susceptible to displacement damage
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TCAD-Machine Learning Framework for Device Variation and Operating Temperature Analysis With Experimental Demonstration IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-18 Hiu Yung Wong; Ming Xiao; Boyan Wang; Yan Ka Chiu; Xiaodong Yan; Jiahui Ma; Kohei Sasaki; Han Wang; Yuhao Zhang
This work, for the first time, experimentally demonstrates a TCAD-Machine Learning (TCAD-ML) framework to assist the analysis of device-to-device variation and operating (ambient) temperature without the need of physical quantities extraction. The ML algorithm used in this work is the Principal Component Analysis (PCA) followed by third order polynomial regression. After calibrated to limited ‘expensive’
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Realizing XOR and XNOR Functions Using Tunnel Field-Effect Transistors IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-18 Shelly Garg; Sneh Saurabh
Recently, a few compact logic function realizations such as AND, OR, NAND and NOR have been proposed using double-gate tunnel field-effect transistor (DGTFET) with independent gate-control. In this article, using two-dimensional device simulations, we propose to realize the exclusive-OR (XOR) and exclusive-NOR (XNOR) logic functions. To implement an XOR function, a dual-material DGTFET (DM-DGTFET)
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Low Turn-Off Loss 4H-SiC Insulated Gate Bipolar Transistor With a Trench Heterojunction Collector IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-08 Ying Wang; Cheng-Hao Yu; Hong-Kai Mao; Xue Wu; Fang-Wen Su; Xing-Ji Li; Jian-Qun Yang
In this work, an improved 4H-SiC insulated gate bipolar transistor (IGBT), or CTH-IGBT, with a trench p-polySi/p-SiC heterojunction on the backside of the device is proposed to reduce the turn-off energy loss ( $E_{off}$ ) and turn-off time ( $T_{off}$ ). The electrical properties of the proposed and contrast structures are all simulated using the ATLAS simulation software to research the working mechanism
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Low Ge Content Ultra-Thin Fin Width (5nm) Monocrystalline SiGe n-Type FinFET With Low Off State Leakage and High ION/IOFF Ratio IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-15 Chong-Jhe Sun; Meng-Ju Tsai; Siao-Cheng Yan; Tzu-Ming Chu; Chieng-Chung Hsu; Chun-Lin Chu; Guang-Li Luo; Yung-Chun Wu
We successfully fabricate the Si 0.8 Ge 0.2 channel fin field-effect-transistor (FinFET) with 5 nm ultra-thin fin width and high aspect ratio ( $\sim 10\times $ ) on silicon-on-insulator (SOI) substrate by simple two-step dry etching. In comparison of the conventional Si FinFET, our proposed SiGe ultra-thin FinFETs (Si 0.8 Ge 0.2 UT-FinFET) at V D = 0.75 V & V G = 1.5 V shows higher ON-state current
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Hydrogen Source and Diffusion Path for Poly-Si Channel Passivation in Xtacking 3D NAND Flash Memory IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-15 Xinshuai Shen; Zhiliang Xia; Tao Yang; Lei Liu; Jinwen Dong; Wenxi Zhou; Chunlong Li; Zongliang Huo
Poly-Si channels need well passivated by using hydrogen passivation process in 3D NAND flash memories for better poly-Si quality with low trap density. It is believed that Xtacking 3D NAND flash memory has the advantage of flexible arranging the passivation process. In this article, two different passivation locations were compared in Xtacking structure to achieve better trap passivation. An optimized
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Study on the IGBT Using a Deep Trench Filled With SiO2 and High-k Dielectric Film IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-18 Weizhen Chen; Junji Cheng
A novel insulated gate bipolar transistor (IGBT) using a deep trench filled with SiO 2 and high- ${k}$ dielectric film (HKF) is presented. The deep trench with the HKF can provide rapid depletion of the drift region during the turn-off transient, eliminating the tail current and reducing the turn-off loss. According to the simulation results, with a relative permittivity of 475 and a 400 nm thickness
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Thermal Modeling of GaN HEMT Devices With Diamond Heat-Spreader IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-10 M. Mahrokh; Hongyu Yu; Yuejin Guo
Harvesting the potential performance of GaN-based devices in terms of the areal power density and reliability, relies on the efficiency of their thermal management. Integration of extremely high thermal conductivity Single-crystalline CVD-diamond serves as an efficient solution to their strict thermal requirements. However, the major challenge lies in the Thermal Boundary Resistance (TBR) at the interface
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Realization of Synapse Behaviors Based on Memristor and Simulation Study With KMC Method IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-17 Nengfan Liu; Gaoqi Yang; Yuli He; Guokun Ma; Ao Chen; Qin Chen; Zhiyuan Xiong; Chunlei Liu; Yi-Ting Tseng; Ting-Chang Chang; Hao Wang
The memristor, emulating biological synapse, is recognized as one key way to overcome the classic von Neumann bottleneck. In this work, by using active metal Cu as electrode, the device of Cu/GeTeO x /TiN exhibited typical resistive switching characteristic based on the electrochemical metallization mechanism (ECM). Moreover, it realized gradual potentiating and depressing conduction under DC and AC
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Modeling of HCD Kinetics Under Full VG – VD Space, Different Experimental Conditions and Across Different Device Architectures IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-28 Uma Sharma; Souvik Mahapatra
A SPICE compatible compact modeling framework is discussed for Hot Carrier Degradation (HCD) stress spanning the entire drain ( $\text{V}_{\mathrm{ D}}$ ) and gate ( $\text{V}_{\mathrm{ G}}$ ) voltage space and wide range of temperature (T). It can model the HCD time kinetics measured using different methods such as shift in threshold voltage ( $\Delta {\mathrm{ V}}_{\mathrm{ T}}$ ), linear ( $\Delta
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Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-01 Amin Rassekh; Jean-Michel Sallese; Farzan Jazaeri; Morteza Fathipour; Adrian M. Ionescu
In this article, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of the thickness of the ferroelectric on the I-V characteristics. Importantly, our model predicts that the negative capacitance minimizes short channel effects and
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Physical Modeling of p-Type Fluorinated Al-Doped Tin-Oxide Thin Film Transistors IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-08-21 Kadiyam Rajshekar; Hsiao-Hsuan Hsu; Koppolu Uma Mahendra Kumar; P. Sathyanarayanan; V. Velmurugan; Chun-Hu Cheng; D. Kannadassan
Fabrication, physical modeling and dynamic response of $p$ -type Al-doped SnO x active channel thin film transistors (TFTs) are presented for the potential application of ultra-high definition (UHD) displays. After deposition of Al-doped SnO x active layer using reactive co-sputtering, the channel was treated with plasma fluorination which improve the device performance of high $I_{ON}/I_{OFF}$ ratio
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Impact of Surface Treatments and Post-Deposition Annealing Upon Interfacial Property of ALD-Al₂O₃ on a-Plane GaN IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-01 Yanni Zhang; Jincheng Zhang; Zhuangzhuang Hu; Zhaoqing Feng; Hepeng Zhang; Shengrui Xu; Zhihong Liu; Hong Zhou; Yue Hao
Optimization of interface characteristics between dielectric and non-polar GaN surface is very important and urgent for vertical GaN MOS device whose channel is perpendicular to the conventional c-plane. In this work, the effects of piranha cleaning and N 2 post deposition annealing (PDA) to the interface between atomic-layer-deposited (ALD)-Al 2 O 3 and a-plane GaN samples were comprehensively investigated
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Substrate Engineering of Inductors on SOI for Improvement of Q-Factor and Application in LNA IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-08-27 Arun Bhaskar; Justine Philippe; Vanessa Avramovic; Flavie Braud; Jean-François Robillard; Cedric Durand; Daniel Gloria; Christophe Gaquiere; Emmanuel Dubois
High Q-factor inductors are critical in designing high performance RF/microwave circuits on SOI technology. Substrate losses is a key limiting factor when designing inductors with high Q-factors. In this context, we report a substrate engineering method that enables improvement of quality factors of already fabricated inductors on SOI. A novel femtosecond laser milling process is utilized for the fabrication
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A Novel High Schottky Barrier Based Bilateral Gate and Assistant Gate Controlled Bidirectional Tunnel Field Effect Transistor IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-09-01 Xi Liu; Kailu Ma; Yicheng Wang; Meile Wu; Jong-Ho Lee; Xiaoshi Jin
In this article, we propose a high Schottky barrier source/drain contacts based bilateral gate and assistant Gate controlled bidirectional tunnel field Effect transistor (HSB-BTFET). Different from Schottky barrier (SB) MOSFET which use lower Schottky barrier to produces the thermionic emission current, the proposed HSB –BTFET utilizes higher Schottky barrier to minimize the thermionic emission current
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In₀.₅₃Ga₀.₄₇As/InAs Composite Channel MOS-HEMT Exhibiting 511 GHz fτ and 256 GHz fmax IEEE J. Electron Devices Soc. (IF 2.555) Pub Date : 2020-08-18 Brian Markman; Simone Tommaso Šuran Brunelli; Aranya Goswami; Matthew Guidry; Mark J. W. Rodwell
An In 0.53 Ga 0.47 As/InAs composite channel MOS-HEMT exhibiting peak $f_{\tau } = 511$ GHz and peak ${f} _{\max }= 285$ GHz is demonstrated. Additionally, another device exhibiting peak $f_{\tau } = 286$ GHz and peak ${f} _{\max }= 460$ GHz is reported. The devices have a 1 nm / 3 nm Al x O y N z interfacial layer and ZrO 2 gate dielectric on a 2 nm / 4 nm In 0.53 Ga 0.47 As / InAs composite channel