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Compatibility of the BSIM-CMG to the Low-Frequency Noise Simulation in Subthreshold and Linear Regions of Amorphous InZnO TFTs IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-03-14 Yayi Chen, Xingji Liu, Dengyun Lei, Yuan Liu, Rongsheng Chen, Yao Ni, Hoi-Sing Kwok, Wei Zhong
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Program Start Bias Grouping to Compensate for the Geometric Property of a String in 3-D NAND Flash Memory IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-03-08 Sungju Kim, Sangmin Ahn, Sechun Park, Jongwoo Kim, Hyungcheol Shin
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Simulation and Optimization of IGZO-Based Neuromorphic System for Spiking Neural Networks IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-03-06 Junhyeong Park, Yumin Yun, Minji Kim, Soo-Yeon Lee
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Characteristics Comparison of SiC and GaN Extrinsic Vertical Photoconductive Switches IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-03-05 Linglong Zeng, Langning Wang, Xinyue Niu, Fuyin Liu, Ting He, Yanran Gu, Muyu Yi, Jinmei Yao, Tao Xun, Hanwu Yang
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1-Mbit 3D DRAM Using a Monolithically Stacked Structure of a Si CMOS and Heterogeneous IGZO FETs IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-03-01 Takeya Hirose, Yuki Okamoto, Yusuke Komura, Toshiki Mizuguchi, Toshihiko Saito, Minato Ito, Kiyotaka Kimura, Hiroki Inoue, Tatsuya Onuki, Yoshinori Ando, Hiromi Sawai, Tsutomu Murakawa, Hitoshi Kunitake, Hajime Kimura, Takanori Matsuzaki, Makoto Ikeda, Shunpei Yamazaki
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Investigation of Noise Properties in the InP HEMT for LNAs in Qubit Amplification: Effects From Channel Indium Content IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-02-29 Junjie Li, Johan Bergsten, Arsalan Pourkabirian, Jan Grahn
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Enhancement of Selectivity for Chemical Mechanical Polishing by Ultra-High-Dose C and Si Ion Implantation IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-02-29 S. Yuan, K. Omori, T. Yamaguchi, T. Ide, S. Muranaka, M. Inoue
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OLED Microdisplay With Monolithically Integrated CAAC-OS FET and Si CMOS Achieved by Two-Dimensionally Arranged Silicon Display Drivers IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-02-19 Munehiro Kozuma, Yusuke Komura, Shoki Miyata, Yuki Okamoto, Yuki Tamatsukuri, Hiroki Inoue, Toshihiko Saito, Hidetomo Kobayashi, Tatsuya Onuki, Yuichi Yanagisawa, Toshihiko Takeuchi, Yutaka Okazaki, Hitoshi Kunitake, Daiki Nakamura, Takaaki Nagata, Yasumasa Yamane, Makoto Ikeda, Shunpei Yamazaki
We developed an organic light-emitting diode (OLED)/oxide semiconductor (OS)/silicon (Si) display in which Si CMOS display drivers can be arranged two-dimensionally by monolithically stacking ${c}$ -axis-aligned crystalline oxide semiconductor (CAAC-OS) FETs over Si CMOS. A CAAC-OS FET exhibits a higher withstand voltage than a SiFET of the same size, enabling considerable pixel area reduction. The
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A Performance Optimized Operational Amplifier Using Transconductance Enhancement Topology Based on a-IGZO TFTs IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-02-16 Fanzhao Meng, Yi Li, Jun Li, Jie Liang, Jianhua Zhang
This paper reports a performance optimized operational amplifier (OPAMP) using transconductance enhancement topology based on the amorphous indium- gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs). The performance of TFTs is enhanced by N2O plasma treatment that presents electrical characteristics suitable for accomplishing an OPAMP. The circuit consists of 19 TFTs with measured phase margin
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Improving the Manufacturability of Low-Temperature GaN Ohmic Contact by Blocking the Fluorine Ion Injection IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-02-16 Tong Liu, Xiangdong Li, Zhanfei Han, Lili Zhai, Junbo Wang, Shuzhen You, Jincheng Zhang, Jie Zhang, Zhibo Cheng, Yuanhang Zhang, Qiushuang Li, Yue Hao
Stabilizing the CMOS-compatible low-temperature Au-free GaN Ohmic contact is a critical work that determines the performance and yield of GaN power HEMTs in mass production. The instability of this contact has been puzzling the industry and academia for years. In this work, an overlooked factor, fluorine injection, is unambiguously verified to widely exist during dielectric etching and can easily destroy
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Unsupervised Learning in a Ternary SNN Using STDP IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-02-15 Abhinav Gupta, Sneh Saurabh
This paper proposes a novel implementation of a ternary Spiking Neural Network (SNN) and investigates it using a hierarchical simulation framework. The proposed ternary SNN is trained in an unsupervised manner using the Spike Timing Dependent Plasticity (STDP) learning rule. A ternary neuron is implemented using a Dual-Pocket Tunnel Field effect transistor (DP-TFET). The synapse consists of a Magnetic
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Flicker Noise (1/f) in 45-nm PDSOI N-Channel FETs at Cryogenic Temperatures for Quantum Computing Applications IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-02-13 Shruti Pathak, Sumreti Gupta, P. Srinivasan, Oscar H. Gonzalez, Fernando Guarin, Abhisek Dixit
In this paper, we have investigated the flicker noise (1/ $f$ ) in 45-nm RFSOI NFETs for quantum computing applications. 1/ $f$ noise characterization and analysis were performed in linear region at cryogenic temperatures down to 10K. A Lorentzian-like noise is also observed depending on bias conditions, possibly due to the floating body of PDSOI. The extracted frequency exponent $(\gamma)$ shows an
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Design of Fast Response Back-Illuminated 3-D Composite Electrode Silicon Detector Utilizing the RIE-Lag Phenomenon IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-02-13 Wenzheng Cheng, Manwen Liu, Chenchen Zhang, Daimo Li, Zhihua Li
In this paper, a back-incidence 3D Composite Electrode Silicon Detector (3DCESD) is proposed and simulated. The electrode structure comprises 70% trench-like and 30% column-like features, achieved through a single etching step utilizing the RIE-lag phenomenon of the Bosch process. The performance of the 3DCESD device is influenced by the structural parameter ${S}$ . Comparative simulations were conducted
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Energy-Efficient Annealing Process of Ferroelectric Hf0.5Zr0.5O2 Capacitor Using Ultraviolet-LED for Green Manufacturing IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-02-13 Hirotaka Yamada, Satoru Furue, Takehiko Yokomori, Yuki Itoya, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi
Thermal annealing process plays an important role in the formation of ferroelectric phase in Hf0.5Zr0.5O2 (HZO) thin films. In this study, the annealing process of the HZO capacitors is demonstrated using ultraviolet (UV)-LED, for the first time. Since the absorptance of the HZO films with TiN electrodes is highest in UV region, the UV-LED annealing process is promising to achieve a much more energy-efficient
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Accurate Modeling of GaN HEMTs Oriented to Analysis of Kink Effects in S22 and h21: An Effective Machine Learning Approach IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-02-12 Zegen Zhu, Gianni Bosi, Antonio Raffo, Giovanni Crupi, Jialin Cai
In this work, for the first time, a machine learning behavioral modeling methodology based on gate recurrent unit (GRU) is developed and used to model and then analyze the kink effects (KEs) in the output reflection coefficient $(S_{22})$ and the short-circuit current gain $(h_{21})$ of an advanced microwave transistor. The device under test (DUT) is a 0.25- $\mu \text{m}$ gallium nitride (GaN) high
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Stability of GaN HEMT Device Under Static and Dynamic Gate Stress IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-02-05 Linfei Gao, Ze Zhong, Qiyan Zhang, Xiaohua Li, Xinbo Xiong, Shaojun Chen, Longkou Chen, Huaibao Yan, Anle Zhang, Jiajun Han, Wenrong Zhuang, Feng Qiu, Hsien-Chin Chiu, Shuangwu Huang, Xinke Liu
In this work, we investigated the stability of a ${p}$ -GaN gate with high electron mobility transistors (HEMTs) including an internal integrated gate circuit. A circuit was designed to improve ${p}$ -GaN gate stability by using capacitance to release the hole into the ${p}$ -GaN layer to mitigate the threshold voltage shift. Through pulse I-V measurement and positive bias temperature instability (PBTI)
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Investigation of Electrical Property and Thermal Stability in Enhancement-Mode InxAl1–xN/AlN/GaN MOS-HEMTs Fabricated by Using NiOx Gate and Fluorine Treatment IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-02-05 Jian Qin, Jingxiong Chen, Wenxuan Xiao, Hong Wang
In this study, we report a novel approach for achieving high-performance enhancement mode (E-mode) InAlN/GaN MOS HEMTs based on the fluorine treatment and a p-type NiOx gate (F-NiO HEMT). The NiO film was deposited at different substrate temperatures using reactive sputtering in a varied mixture of O2 and Ar. We show that the threshold voltage $({V}_{TH}$ ) is effectively modulated by comprehensively
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An Improved Method for InP HEMT Noise-Parameter Determination Based on 50-Ω Noise Measurements IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-01-31 Yuanting Lyu, Zhichun Li, Ao Zhang, Jianjun Gao
In this paper, we propose an improved method for extracting the four noise parameters of InP HEMT devices based on a 50- $\Omega $ noise measurement system. The noise equivalent circuit and noise correlation matrix technique is combined with 50- $\Omega $ noise measurement to determine the noise parameters. This method eliminates expensive tuners and obtains accurate initial parameter values. The reduction
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Investigation of Static Performances of 1.2kV 4H-SiC MOSFETs Fabricated Using All ‘Room Temperature’ Ion Implantations IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-01-30 Stephen A. Mancini, Seung Yup Jang, Zeyu Chen, Dongyoung Kim, Alex Bialy, Balaji Raghotamacher, Michael Dudley, Nadeemullah Mahadik, Robert Stahlbush, Mowafak Al-Jassim, Woongje Sung
Several different designs of 1.2kV-rated 4H-SiC MOSFETs have been successfully fabricated under various ion implantation conditions. Implantation conditions consisted of different P+ profiles and implantation temperatures of both room temperature (25°C) and elevated temperatures (600°C) in order to monitor subsequent lattice damage. Through the use of X-Ray topography, SEM imaging, and electrical measurements
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2023 Index IEEE Journal of the Electron Devices Society Vol. 11 IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-01-30
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A Physical Charge-Based Analytical Threshold Voltage Model for Cryogenic CMOS Design IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-01-29 Hao Su, Yiyuan Cai, Shenghua Zhou, Guangchong Hu, Yu He, Yunfeng Xie, Yuhuan Lin, Chunhui Li, Tianqi Zhao, Jun Lan, Wenhui Wang, Wenxin Li, Feichi Zhou, Xiaoguang Liu, Longyang Lin, Yida Li, Hongyu Yu, Kai Chen
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Wafer-Level Characterization and Monitoring Platform for Single-Photon Avalanche Diodes IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-01-26 Samuel Parent, Frédéric Vachon, Valérie Gauthier, Steve Lamoureux, Alexandre Paquette, Jacob Deschamps, Tommy Rossignol, Nicolas Roy, Philippe Arsenault, Henri Dautet, Serge A. Charlebois, Jean-François Pratte
When developing a technology based on single-photon avalanche diodes (SPADs), the SPAD characterization is mandatory to debug, optimize and monitor the microfabrication process. This is especially true for the development of SPAD arrays 3D integrated with CMOS readout electronics, where SPAD testing is required to qualify the process, independently from the final CMOS readout circuit. This work reports
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Investigation of Photosensitive Polyimide With Low Coefficient of Thermal Expansion and Excellent Adhesion Strength for Advanced Packaging Applications IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-01-26 Yuan-Chiu Huang, Han-Wen Hu, Yun-Hsi Liu, Hui-Ching Hsieh, Kuan-Neng Chen
In advanced packaging schemes, such as fan-out integration technology, photosensitive polyimide (PSPI) is the key material to the fabrication of panel level redistribution-layer (RDL). However, a large mismatch of coefficient of thermal expansion (CTE) between silicon (Si) and PSPI will cause serious warpage issue. Furthermore, polyimide deformation may occur under external heat and pressure, leading
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Balanced Performance Merit On Wind and Solar Energy Contact With Clean Environment Enrichment IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-01-24 Dr. Priyan Malarvizhi Kumar, Dr. M. M. Kamruzzaman, Badria Sulaiman Alfurhood, Bakri Hossain, Harikumar Nagarajan, Surendar Rama Sitaraman
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Design and Thermal Analysis of 2.5D and 3D Integrated System of a CMOS Image Sensor and a Sparsity-Aware Accelerator for Autonomous Driving IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-01-17 Janak Sharda, Madison Manley, Ankit Kaul, Wantong Li, Muhannad Bakir, Shimeng Yu
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High-Performance of InGaZnO TFTs With an Ultrathin 5-nm Al₂O₃ Gate Dielectric Enabled by a Novel Atomic Layer Deposition Method IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-01-12 Pingping Li, Jun Yang, Xingwei Ding, Xifeng Li, Jianhua Zhang
Al2O3, as one of the gate dielectric materials for thin film transistors (TFTs), has been extensively investigated because of its large bandgap, high breakdown field, and good thermal stability. However, the further development of Al2O3 thin films is limited by the presence of defects such as oxygen vacancies, self-interstitial atoms, or impurity elements. To overcome this obstacle, we have developed
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Optimization of Leaky Integrate-and-Fire Neuron Circuits Based on Nanoporous Graphene Memristors IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-01-11 Kannan Udaya Mohanan, Seyed Mehdi Sattari-Esfahlan, Eou-Sik Cho, Chang-Hyun Kim
Artificial neurons form the core of neuromorphic computing which is emerging as an alternative for the von Neumann computing architecture. However, existing neuron architectures still lack in area efficiency, especially considering the huge size of modern neural networks requiring millions of neurons. Here, we report on a compact leaky integrate and fire (LIF) neuron circuit based on graphene memristor
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Potentiometric MgO Film pH Sensor Measurement Analysis and Integrated Flexible Printed Circuit Board IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-01-05 Po-Hui Yang, Jyun-Ming Huang, Ying-Sheng Chang, Che-Tsung Chan, Wei-Shun Chen
In recent years, research in the field of sensors has been rapidly advancing. As a result, this study proposes a pH sensor based on a magnesium oxide (MgO) thin film. The MgO sensing layer of the pH sensor was deposited onto the electroless nickel immersion gold (ENIG) electrode using a radio frequency (RF) sputtering system, where the ENIG electrode is integrated as the working electrode and reference
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Enhanced Carrier Injection Across S/D Contacts in Selenium-Based TMD FETs Using KI and Metal Induced Gap-States Engineering IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-01-05 Kuruva Hemanjaneyulu, Jeevesh Kumar, Utpreksh Patbhaje, Mayank Shrivastava
Lack of transparent contacts has been a critical bottleneck for the two-dimensional Transition Metal Dichalcogenides (TMDs) Field Effect Transistors (FETs). In the absence of approaches to introduce physical doping without inducing crystal damage, charge transfer-based doping has been widely adopted. This manuscript presents a unique charge transfer doping technique using potassium iodide (KI) solution
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A Run-Time Reconfigurable Ge Field-Effect Transistor With Symmetric On-States IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-01-05 Andreas Fuchsberger, Lukas Wind, Daniele Nazzari, Larissa Kühberger, Daniel Popp, Johannes Aberl, Enrique Prado Navarrete, Moritz Brehm, Lilian Vogl, Peter Schweizer, Sebastian Lellig, Xavier Maeder, Masiar Sistani, Walter M. Weber
Here, we present a Ge based reconfigurable transistor, capable of dynamic run-time switching between n- and p-type operation with enhanced performance compared to state-of-the- art Si devices. Thereto, we have monolithically integrated an ultra-thin epitaxial and defect-free Ge layer on a Si on insulator platform. To evade the commonly observed process variability of Ni-germanides, Al-Si-Ge multi-heterojunction
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Series Capacitance Gate Driver to Suppress Voltage Oscillation of SiC MOSFET IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2024-01-04 Sheng Dou, Liansheng Huang, Peng Fu, Xiaojiao Chen, Xiuqing Zhang, Shiying He, Zejing Wang, Jian Yang
The severe voltage oscillation of SiC MOSFET in switching transient affects the safety of devices and EMI. In this article, a series capacitance gate driver (SCGD) is proposed to solve this problem. The series capacitance is charged or discharged in switching transient so that the equivalent driving resistance is gradually increased compared with that of conventional gate driver (CGD), and the voltage
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Generating Predictive Models for Emerging Semiconductor Devices IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-12-27 Maximilian Reuter, Andreas Kramer, Dakyung Lee, Jens Trommer, Niladri Bhattacharjee, Giulio Galderisi, Thomas Mikolajick, Klaus Hofmann
Circuit design requires fast and scalable models which are compatible to modern electronic design automation tools. For this task typically analytical compact models are preferred. However, for emerging device concepts with altered conduction mechanisms like reconfigurable FETs, tunnel FETs or feedback FETs compact models are often not yet ready for circuit simulation environments. Table models help
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2.1 W/mm Output Power Density at 10 GHz for H-Terminated Diamond MOSFETs With (111)-Oriented Surface IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-12-25 Bing Qiao, Pengfei Dai, Xinxin Yu, Zhonghui Li, Ran Tao, Jianjun Zhou, Rui Shen, Tangsheng Chen
This paper presents high performance hydrogen-terminated diamond MOSFETs fabricated on a (111)-oriented single-crystal diamond substrate. The diamond surface was passivated by a high-quality Al2O3 grown by ALD at 350°C as well as a secondary passivation layer Si3N4 deposited by PECVD. After passivation, a low ohmic contact resistance $R_{c}$ of $0.5 \Omega \cdot $ mm was obtained and the 2DHG sheet
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Enhancement and Expansion of the Neural Network-Based Compact Model Using a Binning Method IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-12-22 Jinyoung Choi, Hyunjoon Jeong, Sangmin Woo, Hyungmin Cho, Yohan Kim, Jeong-Taek Kong, Soyoung Kim
The artificial neural network (ANN)-based compact model has significant advantages over physics-based standard compact models such as BSIM-CMG because it can achieve higher accuracy over a wide range of geometric parameters. This makes it particularly suitable for design space exploration and optimization. However, the ANN-based compact model using only one set of model parameters (global-ANN) requires
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The Dual-Mode Integration of Power Amplifier and Radio Frequency Switch Based on GaN Dual-Gate HEMTs IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-12-13 Meng Zhang, Haozheng Wang, Ling Yang, Bin Hou, Mei Wu, Qing Zhu, Minhan Mi, Xu Zou, Chunzhou Shi, Qian Yu, Wenliang Liu, Hao Lu, Xiaohua Ma, Yue Hao
In this paper, an integrated device which realized the dual-mode integration of power amplifier (PA) and radio frequency (RF) switch based on GaN dual-gate (DG) structure is designed and fabricated. The integrated device provides two working modes and meets the performance requirements of PA and RF switch. In the transmit (Tx) mode, the integrated device is used as PA. At the frequency of 3.6 GHz,
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Foreword Special Issue on the 4th Latin American Electron Device Conference IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-12-06 Lluís F. Marsal, Arturo Escobosa, Benjamin Iñiguez, Fernando Guarín
This Special Issue is devoted to research and development in the field of electron devices science and technology. We have selected a number of high-quality papers presented at the 4th Latin American Electron Device Conference (LAEDC 2022). The forth LAEDC edition took place in Puebla, Mexico, from July 4th to 6th, 2022 and was sponsored by the IEEE Electron Devices Society.
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Vertical GaN-on-GaN Trench Junction Barrier Schottky Diodes With a Slanted Sidewall IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-12-07 Xinke Liu, Bo Li, Junye Wu, Jian Li, Wen Yue, Renqiang Zhu, Qi Wang, Xiaohua Li, Jianwei Ben, Wei He, Hsien-Chin Chiu, Ke Xu, Ze Zhong
In this work, vertical gallium nitride (GaN) trench Junction Barrier Schottky (JBS) diodes fabricated with a novelty slanted p-GaN sidewall on a 2-inch free-standing GaN (FS-GaN) substrate were demonstrated. The slanted sidewall on edge of devices was conducted to suppress the peak of electric field distributions at high voltage. By realizing an off-state breakdown voltage $V_{BR}$ of 2 kV and an on-state
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A 65nm Cryogenic CMOS Design and Performance at 4.2K for Quantum State Controller Application IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-12-06 Munehiro Tada, Koichiro Okamoto, Takahisa Tanaka, Makoto Miyamura, Hiroki Ishikuro, Ken Uchida, Toshitsugu Sakamoto
A performance evaluation of cryogenic CMOS circuit at liquid-helium temperature (4.2K) is conducted using a standard 65nm bulk CMOS for quantum state controller (QSC) applications. The ON-current (Ion) of the core n/pMOSFET are increased by 25% and 9% with excellent gate modulation (Ion/Ioff= $\sim 10~^{\mathrm{ 9}}$ ). The cryogenic characteristics of copper interconnects in the back end of the line
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Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-11-29 Shaoxin Yu, Weiheng Shao, Rongsheng Chen, Rilin Zhang, Xiaoqing Liu, Yongjun Wu, Bin Zhao
The design of LDMOS (Lateral double diffused metal oxide semiconductor) devices with CFP (Contact field plate) has been of great significance in recent years, according to its advantages of low resistance and high switch efficiency. In this paper, this ultra-low $R_{\mathrm{ on,sp}}$ (Specific on-resistance) LDMOS device is simulated, designed, and fabricated. The effects on FOM (Figures-of-merits)
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Self-Organizing Mapping Neural Network Implementation Based on 3-D NAND Flash for Competitive Learning IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-11-29 Anyi Zhu, Lei Jin, Wen Zhou, Tianchun Ye, Zongliang Huo
Self-organizing Map (SOM) neural network is a prominent algorithm in unsupervised machine learning, which is widely used for data clustering, high-dimensional visualization, and feature extraction. However, the hardware implementation of SOM is limited by the von Neumann bottleneck. Herein, a SOM neural network is implemented by the combination of 3D NAND flash memory arrays and in-memory Euclidean
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A New Pixel Circuit for Micro-Light Emitting Diode Displays With Pulse Hybrid Modulation Driving and Compensation IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-11-28 Juncheng Xiao, Wenxue Huo, Dong Yuan, Ce Liang, Guhuang Lai, Ji Li, Hongyuan Xu, Shan Li, Shengdong Zhang
A new pixel circuit consisting of eleven n-type IGZO transistors (TFTs) and four capacitors is proposed and applied for micro light emitting diode (MLED) displays. The circuit is driven by pulse hybrid modulation (PHM), combining pulse amplitude modulation (PAM) and pulse width modulation (PWM). In purpose, high grayscales are achieved by PAM mode and low grayscales are achieved by PWM mode, which
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A Low-Temperature Poly-Silicon Thin Film Transistor Pixel Circuit for Active-Matrix Simultaneous Neurostimulation IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-11-15 Taoming Guo, Bowen Liu, Jiwei Zou, Hanbin Ma, Yongpan Liu, Xueqing Li, Huazhong Yang, Chen Jiang
This work reports a novel low-temperature poly-silicon thin-film-transistor-based pixel circuit for active-matrix neurostimulation. The pixel circuit consists of four transistors and one capacitor (4T1C) for programmable current-mode stimulation, which are designed for storing stimulation intensity information, simultaneously stimulating a large number of channels, and discharging stimulation electrodes
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Use of Nanosecond Laser Annealing for Thermally Stable Ni(GeSn) Alloys IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-11-13 Andrea Quintero, Pablo Acosta Alba, Jean-Michel Hartmann, David Cooper, Patrice Gergaud, Vincent Reboud, Philippe Rodriguez
In this study, we have conclusively used UV-nanosecond laser annealing (UV-NLA) as an alternative to classical rapid thermal annealing (RTA) for the formation of stable Ni-GeSn alloys. The phase formation sequence was similar to the one obtained with RTA. At low laser energy densities (ED) and after the consumption of Ni, the Ni-rich phase, Ni5(GeSn)3, was first obtained. This phase was followed, for
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An a-IGZO TFT-Based AMOLED Pixel Circuit Employing Stable Mobility Compensation Suppressing Degradation of Detected VTH IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-11-10 Kyeong-Soo Kang, Ji-Hwan Park, Chanjin Park, Ji-Ho Lee, Soo-Yeon Lee
In this paper, we propose a new active-matrix organic light-emitting diode (AMOLED) pixel circuit using amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFTs). The proposed pixel circuit consists of seven TFTs and two capacitors, compensating for both threshold voltage (VTH) and mobility variations. The simulation results show that the proposed pixel circuit can successfully compensate
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Editorial IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-11-03 Paolo Pavan
This Section of the IEEE Journal of the Electron Devices Society includes two invited papers for the Special Issue on “Materials, processing and integration for neuromorphic devices and in-memory computing”. These works describe the most recent developments and the state of the art in materials and devices for neuromorphic computing, including both experimental results and theoretical developments
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A CMOS-Compatible Gate-Assisted Photonic Demodulator With Contrast Enhancement for Time-of-Flight Sensing IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-11-01 Annan Xiong, Shunqi Dai, Cristine Jin Estrada, Zhirong Peng, Chen Xu, Jie George Yuan, Mansun Chan
This paper presents a CMOS-compatible gate-assisted photonic demodulator with contrast enhancement (GAPD-CE) techniques. To form an asymmetric field inside the substrate that will facilitate the transfer of photogenerated electrons, p-well and channel doping techniques are applied under the polysilicon guides. Modulation contrast (MC) values extracted from TCAD simulation show that the modified structure
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Three Temperature Regimes in Subthreshold Characteristics of FD-SOI pMOSFETs From Room-Temperature to Cryogenic Temperatures IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-10-27 Yo-Ming Chang, Ting Tsai, Yu-Wen Chiu, Horng-Chih Lin, Pei-Wen Li
We reported three temperature regimes in subthreshold characteristics of 22-nm FD-SOI p-MOSFETs at operation ${T}\,\,=$ 300 K – 4.5 K. Subthreshold swing (SS)-plateau at 125 K – 50 K in combination with SS-linearity at ${T}\,\,=$ 300 K – 125 K and 50 K – 4.5 K were observed in different types of FD-SOI p-MOSFETs with channel length $(L_{G}) \leq100$ nm, which is possibly attributed to temperature-dependent
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Analytical Modeling of Threshold Voltage and Subthreshold Slope for 3-D NAND Flash Memory With a Non-Uniform Doping Profile IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-10-20 Amit Kumar, Shubham Sahay
The emergence of data-driven technologies including Internet of Things (IoT), artificial intelligence (AI), and cloud computing has led to a surge in data generation and mining. The 3D NAND Flash memory has emerged as a promising technology for handling the big data owing to its ultra-high density, ultra-low cost per bit, fast random access, and multi-level programming capability per cell. However
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A 121 A/cm2 High Current Density Copolymer OSC-Based Thin-Film Power OFET With 300 V Off-State Breakdown Voltage IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-10-18 Fubin Wang, Jun Zhang, Hao Zhang, Lei Wang, Xin Wu, Haonan Lin, Jiayi Zhou, Yuhao Wang, Jiafei Yao, Jing Chen, Kemeng Yang, Man Li, Yufeng Guo
The long-term absence of organic drive management circuits has prevented organic integration from achieving full flexibility. The high off-state breakdown performance and its avalanche-like breakdown mechanism of copolymer Organic Semiconductor (OSC)-based Organic Field Effect Transistors (OFETs) have been revealed in recent researches. By employing diketopyrrolopyrrole-based conjugated copolymer OSC(DPPT-TT)
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Analysis of Standard-MOS and Ultra-Low-Power Diodes Composed by SOI UTBB Transistors IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-10-17 Fernando José da Costa, Renan Trevisoli, Rodrigo Trevisoli Doria
The main objective of this work is to present an analysis of the performance of Ultra-Thin-Body and Buried Oxide transistors working as Ultra-Low-Power and standard-nMOS diodes. The implementation of different ground planes and substrate biases is analyzed. It is shown a reduced leakage current and increased ratio between the on and off-state currents for both systems with the nMOS devices’ substrate
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Rectifying Schottky Contact in ZrN/Polycrystalline p-Ge IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-10-13 Kenta Moto, Kaoru Toko, Tomonari Takayama, Toshifumi Imajo, Takamitsu Ishiyama, Keisuke Yamamoto
Fermi-level pinning (FLP) at the metal/Ge interface makes it difficult to control the Schottky barrier height, which forces an ohmic behavior on p-Ge and a rectifying behavior on n-Ge. This study first demonstrates the rectifying behavior on polycrystalline (poly) p-Ge on a glass substrate, using sputter-deposited ZrN contacts under 350 °C process. The rectifying characteristics depend on the poly-Ge
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Analog PWM Method With Sweep Generation Structure Based on P-Type LTPS TFTs for Micro-LED Displays IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-10-12 Chih-Lung Lin, Cheng-Han Ke, Jui-Hung Chang, Chieh-An Lin, Chia-En Wu, Ming-Hsien Lee
This work proposes a novel pixel circuit using analog pulse width modulation (PWM) for micro light-emitting diode (micro-LED) displays. The proposed circuit generates uniform sweep waveforms and driving currents to control micro-LED emission precisely by compensating for threshold voltage (VTH) variations of p-type low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) and VDD current-resistance
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Comprehensive Investigation of ANN Algorithms Implemented in MATLAB, Python, and R for Small-Signal Behavioral Modeling of GaN HEMTs IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-10-12 Saddam Husain, Bagylan Kadirbay, Anwar Jarndal, Mohammad Hashmi
Artificial Neural Network (ANN) is frequently utilized for the development of behavioral models of Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs). However, exhaustive investigation concerning the ANN algorithms implemented in major programming platforms for small-signal behavioral models of GaN HEMTs is generally not available. To fill this void, this paper carefully examines and
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An On-Chip Filter Using Near-End Cross-Coupling With Jigsaw Puzzle Shaped Resonators IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-10-10 Xin Cao, Weiping Li
In this paper, an on-chip band-pass filter with near-end cross-coupling (NECC) scheme is proposed based on the 0.13- $\mu \text{m}$ SiGe (Bi) CMOS processing technology. First, in order to increase the out-of-band suppression, the NECC is proposed to produce an extra transmission zero (TZ) without introducing extra resonators, thus increasing the out-of-band suppression. Then, in order to facilitate
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An ASM-HEMT for Large-Signal Modeling of GaN HEMTs in High-Temperature Applications IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-09-29 Nicholas C. Miller, Alexis Brown, Michael Elliott, Ryan Gilbert, Devin T. Davis, Ahmad E. Islam, Dennis Walker, Gary Hughes, Kyle Liddy, Kelson D. Chabak
This paper reports a temperature-dependent ASM-HEMT for modeling GaN HEMTs at elevated temperatures. Modifications to the standard ASM-HEMT were developed to accurately capture the DC and RF measurements collected at varying chuck temperatures. Several results are reported which validate the model including DC-IV, pulsed-IV, scattering-parameter, and load-pull measurements. The model is then used to
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Analysis of High-Temperature Data Retention in 3D Floating-Gate nand Flash Memory Arrays IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-09-29 Gerardo Malavena, Mattia Giulianini, Luca Chiavarone, Alessandro S. Spinelli, Christian Monzio Compagnoni
In this paper, we present a detailed experimental investigation of high-temperature data retention in 3D floating-gate NAND Flash memory arrays. Data reveal that charge detrapping from the cell tunnel oxide and depassivation of traps in the string polysilicon channel are the physical mechanisms resulting in the most relevant long-term reliability issues for the memory array. On one hand, the two mechanisms
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Compact Modeling of Parasitic Capacitances in GAAFETs for Advanced Technology Nodes IEEE J. Electron Devices Soc. (IF 2.3) Pub Date : 2023-09-18 Swapna Sarker, Abhishek Kumar, Mohammad Ehteshamuddin, Avirup Dasgupta
In this work, a compact model for parasitic capacitances is proposed for Gate-All-Around silicon nanosheet FET (GAAFET). For 3 stack GAAFET, all possible parasitic capacitance components are included according to the electric field lines and geometric structure of this device. Conformal mapping and Schwarz Christoffel transforms as well as elliptic integral methods are used to model the perpendicular