1/f noise provides essential information on the interface trapping effect as well as the scattering mechanism in transistors. In this work, a systematic 1/f noise study has been carried out on the recessed-gate enhancement-mode (E-mode) GaN MOS-HEMTs under electrical and thermal stress together with the depletion-mode (D-mode) counterpart. Low-frequency (1–1000 Hz) measurement has been performed at

A phenomenological model, accounting for interface states at metal-semiconductor contacts, is proposed to explain particular gate-bias-dependent kinking in I-V characteristics sometimes observed in MoS 2 FETs. The effect is studied in double-gate FETs by varying top-gate voltage (V TG ) and bottom-gate voltage (V BG ), with the MoS 2 semiconductor layer overlying source/drain (S/D) metal contacts in

This Special Issue is devoted to research and development in the field of electron devices science and technology. We have selected a number of high quality papers presented at the $2^{nd}$ Latin American Electron Device Conference (LAEDC 2020). The $2^{nd}$ LAEDC was held in San Jose, Costa Rica from the $25^{th}$ to 28 February, 2020 and was sponsored by the IEEE Electron Devices Society.

As scaling of the feature size - the main driving force behind an outstanding increase of the performance of modern electronic circuits - displays signs of saturation, the main focus of engineering research in microelectronics shifts towards finding new paradigms. Any future solution must be scalable and energy efficient while delivering high performance, superior to that of CMOS-based circuits. In

Barrier height ( $\phi _{b}$ ), trap state, bandgap ( $E_{g}$ ), and band alignment information of the metal–ZrO 2 –metal capacitor have been extracted using internal photoemission (IPE) system. By correlating the IPE analysis with I-V and C-V characteristics obtained before and after rapid thermal annealing, origin and transformation of defect states have been successfully investigated. Our analysis

In recent years the Journal of the Electron Device Society (J-EDS) has experienced an increasing number of submissions of “simulation only” manuscripts. One reason for this is the improved accuracy and maturity of physicsbased simulation tools, either Technology Computer Aided Design (TCAD) or circuit analysis programs, that allow researchers to explore, devise and optimize the best breakthroughs going

The diamond-like carbon (DLC) is important for passivation of junction termination in high power devices due to its excellent electrical, mechanical, and thermal properties. While the role of conductivity and polarization of the DLC layer on the blocking capability of a p-n junction has been explained recently, the thermal behavior still needs to be addressed. For this purpose, the diode leakage current

This paper describes the influence of Longitudinal Corner Effect (LCE effect) and PArallel Connection of Metal–Oxide–Semiconductor Field-Effect Transistors (MOSFETs) with Different Channel Lengths Effect (PAMDLE effect) of Diamond (hexagonal gate shape) MOSFET in different Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) technologies (180nm-Bulk and $1\mu \text{m}$ -Silicon-On-Insulator

In this work, the properties of gallium oxide (Ga 2 O 3 ) and its excellent interface properties to GaN-based materials are explored as a gate insulator layer for GaN-based metal-oxide-semiconductor high-electron mobility transistors (MOSHEMTs). A novel vapor cooling condensation system was used to deposit the high quality Ga 2 O 3 films with high insulation and low defect suitable for gate insulator

Three-Independent-Gate Field-Effect Transistors (TIGFETs) are a promising alternative technology that aims to replace or complement CMOS at advanced technology nodes. In this paper, we extracted the parasitic and intrinsic capacitances of a silicon-nanowire TIGFET device using three-dimensional numerical simulations in an attempt to accurately compare its capacitances and, consequently, circuit-level

A novel low loss lateral insulated gate bipolar transistor (LIGBT) with high voltage level is designed and studied in this paper, and is proposed with assisted depletion N-region (AD) and P-buried layer (PB) in the bulk Si substrate, named PBAD LIGBT. The proposed PBAD LIGBT utilizes the idea of electric field modulation (EFM) to greatly improve the breakdown voltage, which optimizes the lateral and

In this paper, a new modeling technique is proposed for extracting small-signal lumped-element equivalent-circuit models for microwave transistors. The proposed procedure is based on using an optimization approach that is improved by targeting a quasi-static behavior as additional objective function rather than only minimizing the error between the simulated and measured scattering parameters. The

This paper presents the calibration of the novel kinetic velocity model (KVM) in the drift-diffusion (DD) transport approach, which can account for the ballistic effect in short-channel devices. The KVM considers a thermionic emission limit and a free carrier acceleration limit for the mobility. We develop a methodology to extract the parameters for the KVM and for the high-field saturation velocity

The paper presents the design and fabrication of lateral-field-excited (LFE) resonators based on 42° Y-cut single-crystal LiTaO 3 (LT) on silicon dioxide (SiO 2 ). A simple coplanar top electrode is defined to excite the bulk acoustic wave modes in the suspended LT/SiO 2 structure, and the fabrication process that only involves two lithography steps is more simplified compared to that of commercial

In this work, a L-shaped tunnel FET (TFET), which has the dominant tunneling current in the normal direction to the gate, is introduced with the doping engineering and its electrical characteristics are analyzed using TCAD device simulations. The proposed L-shaped TFET has the pocket doping (p + -doping for n-type operations) underlying the gate, which can suppress the corner tunneling generated near

This work proposes a mini-LED driving circuit that adopts the pulse-width modulation (PWM) driving method for use in a liquid-crystal display (LCD) backlight. The proposed circuit can compensate for the threshold voltage ( $\text{V}_{\mathrm{ TH}}$ ) variation in a low-temperature poly-crystalline silicon thin-film transistor (LTPS TFT) and a VSS current-resistance (I-R) rise, to generate a stable

In this study, we report high-performance amorphous Ga 2 O 3 metal-oxide (AMO) thin film transistor (TFT) using an low-temperature solution-process coupling with In alloy engineering. In doping can lower the activation temperature of gallium oxide and increase the oxygen vacancy concentration to further activate the device. The optical bandgap of IGO film can be changed from 5.3 to 4.25 eV with the

In this study, in-situ MOCVD-grown SiN/AlN/Al 0.05 Ga 0.95 N HEMTs were fabricated using ALD-Al 2 O 3 /PECVD-SiO 2 passivation. A high on/off current ratio of 10 9 and a low subthreshold swing of 64 mV/dec are achieved. The interface traps in the SiN/AlN/Al 0.05 Ga 0.95 N structure are investigated using frequency-dependent capacitance-voltage and conductance measurements. The shift in threshold voltage

In this paper, we have proposed a simple and zero-cost technique to improve ON-state and reliability performance of LDMOS transistors. We introduced doping gradient in the channel by optimizing position of the P-Well mask during test structure design/layout. Through proper device design, fabrication and measurement on different test structures, we have shown that the graded channel significantly improves

This paper presents a common-drain-based operational amplifier (OPAMP) fabricated by mono n-type indium-zinc-oxide (IZO) thin-film transistors (TFTs). Positive feedback technology is employed to the load TFTs by cross-coupled connection in order to boost the voltage gain of the common-drain differential pair. The OPAMP exhibits an open-loop voltage gain (A v ) of 27 dB over a −3 dB bandwidth (BW) of

A power MOSFET with P-base Schottky diode and built-in channel diode is proposed and numerically investigated in this article. The P-base Schottky diode formed by the P-base Schottky contact is in reverse series with the P-base/N-drift junction diode. Besides, by coupling the gate of the dummy MOSFET to the source, a built-in channel diode is introduced, which provides a unipolar reverse conduction

White light-emitting diodes (WLEDs) with a visible uniform spectral power distribution (SPD) were fabricated by integrating a blue LED chip and a phosphor-in-silicone (PiS)/phosphor-in-glass (PiG) stacked package. After adjusting the doping concentrations of phosphors (cyan, green and red) in the silicone encapsulant, the PiS was dispensed in the cavity of lead frame already bonded with a blue LED

In this article, we propose a novel real-time threshold voltage ( $V_{th}$ ) compensation method for AM-OLED display. The proposed method predicts $V_{th}$ shift of driving thin-film transistors (TFTs) based on the equation derived from the sensing line charging with TFT’s drain current. The prediction equation requires two consecutive source node voltages to consider the mobility variation, and only

Etched-and-regrown GaN pn-diodes capable of high breakdown voltage (1610 V), low reverse current leakage (1 nA = 6 $\mu \text{A}$ /cm 2 at 1250 V), excellent forward characteristics (ideality factor ~1.6), and low specific on-resistance (1.1 $\text{m}\Omega $ .cm 2 ) were realized by mitigating plasma etch-related defects at the regrown interface. Epitaxial ${n}$ -GaN layers grown by metal-organic

Experimental results obtained for 2.3 kV SiC planar-gate power JBSFETs with different cell topologies are analyzed in this article using analytical models and numerical simulations. All the accumulation-channel devices were simultaneously manufactured in a 6-inch commercial foundry with channel length of 0.5 $\mu \text{m}$ and gate oxide thickness of 55 nm. The Schottky contact width was chosen to

We investigated the impact of a sulfur passivation (S-passivation) process step on carrier transport properties of surface-channel In 0.7 Ga 0.3 As quantum-well (QW) Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) with source/drain (S/D) regrowth contacts. To do so, we fabricated long-channel In 0.7 Ga 0.3 As QW MOSFETs with and without (NH 4 ) 2 S treatment prior to a deposition of Al

ON-state conductance properties of vertical GaN ${n}$ -channel trench MISFETs manufactured on different GaN substrates and having different gate trench orientations are studied up to 200 °C ambient temperature. The best performing devices, with a maximum output current above 4 kA/cm 2 and an area specific ON-state resistance of 1.1 $\text{m}\Omega \cdot $ cm 2 , are manufactured on ammonothermal GaN

In this article, we present an experimental study on the impact of post-metallization annealing conditions on the negative-bias temperature instability (NBTI) of Si p-channel fin field-effect transistors (p-FinFETs) with atomic layer deposition tungsten (ALD W) as the gate-filling metal. The effects of annealing conditions on the tensile stress of the W film, impurity element concentration in the gate

This study investigates a device’s ability to boost its on-state current and subthreshold behavior using a ferroelectric field-effect transistor (FeFET) with an ultrathin sub-5-nm Hf 1-x Zr x O2 (HZO). A conventional field-effect transistor (FET) with pure hafnium (HfO 2 ) is used as a control measure and the impact of an internal metal gate (IMG) is also discussed. The study was conducted by using

From our other works, we have developed urea biosensor based on graphene oxide/nickel oxide sensing film modified either by Au nanoparticles or ${\gamma }$ -Fe 2 O 3 nanoparticles. In this study, we have further developed back-end calibration circuit to reduce the drift effect and hysteresis effect of the two types of the urea biosensors. The back-end calibration circuit is composed of non-inverting

In this article, novel double-layer films were designed and examined for dye-sensitized solar cells (DSSCs). The commercial titanium dioxide (TiO 2 ) nanoparticles as a bonding underlayer, and the silver nanowires (AgNWs) were used and prepared by means of the polyol method. They which were doped into TiO 2 composite materials. The microstructure of AgNWs and the effect of modified DSSCs on photovoltaic

The externally compensated display system has been proved to have greater potential to completely solve aging and uniformity issues of the AMOLED display system than the internally compensated display system. However, the traditional compensation method is time consuming and responses slowly to the mobility change of TFT. The traditional compensation method performs calibration during the inter-frame

Ultraviolet (UV) detection is an important index, as UV rays can cause skin diseases in humans. To enhance the performance of UV photodetectors, we fabricated palladium nanoparticles- (Pd NPs) modified ZnO nanorods. The surface morphology is observed by using transmission electron microscopy and transmission electron microscopy. The crystal structure is analysed by using X-ray diffraction. The optical

The liquid phase chemical enhanced oxidation (LPCEO) technique was applied to achieve planarized isolation of a high-indium-content In 0.52 Al 0.48 As/In 0.8 Ga 0.2 As metamorphic high-electron-mobility transistor (MHEMT). Through a simple, low-temperature process not requiring costly machinery, electrical isolation of components was accomplished. In addition, multiple advantages were gained, including

Sheet resistance ( ${R_{sheet}}$ ) reduction of a-few-layered molybdenum disulfide (MoS 2 ) film using sputtering is investigated in this study. To enhance the carrier density, chlorine (Cl 2 ) gas excited by inductively coupled plasma is introduced as a substitute for sulfur. To electrically activate the Cl dopants and simultaneously prevent out-diffusion of sulfur, a furnace annealing was performed

In this study, vertical tunnel FET-based ternary CMOS (T-CMOS) is introduced and its electrical characteristics are investigated using TCAD device and mixed-mode simulations with experimentally calibrated tunneling parameters. This new T-CMOS utilizes two different types of tunneling currents to form three different output voltage states: (1) source-to-drain tunneling current; and (2) conventional

Germanium (Ge) has gained great attention not only for future nanoelectronics but for back-end of line (BEOL) compatible monolithic three-dimensional (M3D) integration recently. For high performance and low power devices, various high-k oxide/Ge gate stacks including ferroelectric oxides have been investigated. Here, we demonstrate atomic layer deposited (ALD) polycrystalline (p-) HfO 2 /GeO X /Ge

I would like to express my sincere gratitude—and the gratitude of the Electron Device Society (EDS) community at large—to David Abe and Tian-Ling Ren, for their commitment, dedication and hard work during their six years of service on the Journal of Electron Devices editorial board. Our very best wishes to them in their future endeavors.

In this work, we improved the performance of germanium (Ge) channel Charge Trapping MemTransistors (CTMTs) as synaptic device by using Ti-doped HfO 2 as charge trapping layer (CTL). We manipulated the amount of Ti dopant within the HfO 2 CTL to perform the band engineering by varying the Hf/Ti cycle ratio in atomic layer deposition (ALD). The content of Ti was quantified and the energy band structures

This article proposes a voltage-to-frequency converter (VFC) design using unipolar metal-oxide thin film transistor (TFT) technology. The proposed VFC has an integrator and Schmitt trigger based structure. This structure has the advantages of constant power consumption, full-swing output, and low circuit complexity compared to the early designs. To verify the proposed design, SmartSpice simulation

In this article, the work-function fluctuation (WKF) of nanosized metal grains is estimated and compared with the cuboid and Voronoi methods for 10-nm-gate gate-all-around silicon nanowire n-MOSFETs. For the methods having different metal grain numbers (MGNs) and 1000 randomly generated samples, we evaluate the variability of the threshold voltage, off-current and on-current. The estimated errors of

We have demonstrated a novel method of depositing ALD-Al 2 O 3 /PECVD-SiO 2 bi-layer dielectric to passive the surface channels of the hydrogen-terminated diamond (H-diamond). After Al 2 O 3 /SiO 2 passivation, the surface current increased with time and then tended to be saturated. Afterwards, it became much more stable and showed a larger current than an unpassivated counterpart. The H-diamond MOSFETs

In this article, we describe several enhancements of a three-phase correlation image sensor (3PCIS) toward its uses for a direct algebraic method of optical flow detection, i.e., determining velocity field of image patterns for detecting, tracking, and three-dimensional recovery of objects in a scene. A recent theoretical study has provided an exact closed-form solution of the velocity from temporal

An optimized doping process is used to achieve extremely-low threshold voltage (ELVT) FinFETs for low-power mmWave applications based on 12nm node technology platform. With the $V_{TH}\approx 100$ mV ELVT FinFET shows 15% $I_{EFF}$ improvement at the same $V_{DD}$ compared to its super-low threshold voltage (SLVT) counterpart, while mismatch and reliability performances are comparable. $F_{T}/F_{MAX}$

Oxide semiconductors are of particular interest in the field of integrated electronics due to their large-area fabrication, high uniformity, and superior performance. Here, we report an exceptionally sensitive photo-induced inverter device with high linearity based on the unipolar n-type channel material amorphous silicon indium zinc oxide (a-SIZO). The field-effect transistor (FET) based on a-SIZO

This article presents the optimization of a one-transistor active pixel sensor (1T-APS), known as the photoelectron in-situ sensing device (PISD) built in a fully-depleted silicon-on-insulator (FD-SOI) substrate. By employing TCAD simulation, we develop a physics-based model and systematically investigate the impact of six key parameters – gate oxide thickness, buried oxide layer, top Si layer, gate

This review paper assesses the main approaches in the electrical characterization of advanced MOSFETs towards their future analog and RF applications. Those approaches are shown to be different from the traditionally used ones for the assessment of the device perspectives for digital applications. Based on the original research realized by our group over the last years, advantages and necessity of

Presents the table of contents for this issue of the publication.

The Journal of Electron Devices Society (J-EDS) was founded in 2013 and grown up very robustly since then.

The use of polymer solar cells (PSCs) for indoor dim-light energy harvesting has attracted significant interest for low power consumption electronics such as the Internet of Things. However, the photostability study and degradation mechanism under indoor artificial light is far behind than those under full sun illumination (standard AM 1.5G), which is crucial for the successful commercialization of

This work studies the effects of the temperature variation, from 300K to 500K, on the electrical parameters of SOI n-type and p-type junctionless nanowire transistors. The temperature influence on the threshold voltage, subthreshold slope, and the effective carrier mobility were analyzed. The mobility scattering mechanisms were analyzed and show that nanowire devices have the phonon scattering as their

Presents the reviewers who contributed to this publication in 2020.

An accurate and efficient noise-based simulation technique for predicting the impact of device-parameter variability on the DC statistical behavior of integrated circuits is presented. The proposed method is validated on a source follower, a diode-load inverter and a current mirror based on organic thin-film transistors. Taking advantage of the standard noise analysis of a circuit, after translating

The gate-all-around nanowire FET (GAA NW FET) is one of the most promising architectures for the next generation of transistors as it provides better performance than current mass-produced FinFETs, but it has been proven to be strongly affected by variability. For this reason, it is essential to be able to characterize device performance which is done by extracting the figures of merit (FoM) using

The Analytical Full Capacitance Model (AFCM) for amorphous oxide semiconductors thin film transistors (AOSTFTs) is first validated, using a 19-stages Ring Oscillator (RO) fabricated and measured. The model was described in Verilog-A language to use it in a circuit simulator in this case SmartSpice from Silvaco. The model includes the extrinsic effects related to specific overlap capacitances present

This Special Issue is dedicated to recent research in the field of compact modeling of semiconductor devices. This is the first J-EDS Special Issue on compact modeling. In the last years, a number of new semiconductor device structures, for electronic and photonic applications, have been developed. Compact models are needed for the incorporation of these new devices in integrated circuits. Therefore

This article presents a state-of-art review of on-wafer S-parameter characterization of THz silicon transistors for compact modelling purpose. After, a brief review of calibration/de-embedding techniques, the paper focuses on the on-wafer calibration techniques and especially on the design and dimensions of lines built on advanced silicon technologies. Other information such as the pad geometry, the

A compact multi-gate MOSFET model is developed for high-voltage applications. The model includes the short-channel effects specific for thin-film MOSFETs with highly resistive drain contact. The short-channel effects are drastically reduced by the drain-resistance effect, which is consistently modeled by considering the whole potential distribution along the device. The overlap length is an important

The persistent advancements made in the scaling and vertical implementation of front-end-of-line transistors has reached a point where the back-end-of-line metallization has become the bottleneck to circuit speed and performance. The continued scaling of metal interconnects at the nanometer scale has shown that their behavior is far from that expected from bulk films, primarily due to the increased

This work demonstrates high-performance AlInGaN/AlN/GaN high electron mobility transistors grown on 150 mm p-type low resistivity (resistivity~ 20–100 $\Omega $ -cm) silicon substrate with state-of-the-art Johnson’s figure-of-merit (JFOM). Current gain cut-off frequency ( $\text{f}_{\mathrm{ T}}$ ) of 83 GHz and 63 GHz and power gain cut-off frequency ( $\text{f}_{\mathrm{ max}}$ ) of 95 GHz and 77