We are pleased to bring to you, in this Special Section, extended versions of eight papers that were first presented at the ESSDERC’2019 Conference in Cracow (Poland). During the selection process carried out by the ESSDERC Technical Program Committee several papers were nominated within Conference Chairs structure for later presentation in this Special Section of JEDS. The Authors were notified by

In this work, we report a novel Indium Arsenide-on-insulator (InAsOI) FinFET platform designed with record high aspect ratio that favors the use of the devices as charge sensors. InAs has very high mobility among III-V semiconductors and an intrinsic surface accumulation layer yielding good ohmic contacts thus making it an interesting choice for chemical and biological sensing platforms. Template Assisted

This work studies the self-heating (SH) effect in ultra-thin body ultra-thin buried oxide (UTBB) FDSOI MOSFETs at cryogenic temperatures down to 77 K. S-parameter measurements in a wide frequency range, with the so-called RF technique, are employed to assess SH parameters and related variation of analog figures of merit (FoMs) at different temperatures. Contrary to the expectations, the effect of self-heating

This paper details a robust parameter extraction flow for the PSPHV LDMOS transistor model. The procedure uses a global scaling parameter set and accounts for self-heating. We describe how to determine parameters associated with important physical effects specific to PSPHV: non-uniform lateral channel doping; the Kirk effect; internal drain voltage clamping; and the drain expansion effect. The method

The effects of an Al 2 O 3 dielectric patterned by wet etching in a metal-insulator-semiconductor (MIS) tunnel diode are studied by I-V, C-V and charge storage characteristics in this paper. The behaviors are obviously different from the device without an etched edge. It is suggested that traps are formed at the edge because of the etching process. A circuit model is proposed to explain the effect

With the development of microelectronic technology, the reliability of devices in a complex electromagnetic environment has become one of the greatest challenges in the semiconductor industry. On this basis, a phenomenon of nonlinear transient response is observed in high-power microwave (HPM)-radiating AlGaAs/InGaAs pseudomorphic high-electron-mobility transistors (pHEMTs). This abnormal response

In this work, the high-performance junctionless-mode (JL) and low-power inversion-mode (IM) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with nanosheet channels (less than 10-nm in thickness) are vertically integrated in monolithic three-dimensional integrated circuit (3D-IC) structure. Both JL and IM TFTs can exhibit high on/off current ratio over 107 to demonstrate their performance

We identify an optimum channel length for planar Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) field-effect transistors, in terms of the specific on-resistance, through systematic device simulation and optimization. We simulate LDMOS devices with different channel lengths ranging from 100 nm to 10 nm, modifying the length of the drift region and doping concentration of the body region to match

We have fabricated and demonstrated ultrathin In-Ga-Zn-O (IGZO) channel ferroelectric HfO 2 field effect transistor (FET) with memory operation. Ultrathin-body IGZO ferroelectric FET (FeFET) shows high mobility and nearly ideal subthreshold slop with minimum 8 nm channel thickness, thanks to the properties of IGZO material, junctionless FET operation, nearly-zero low-k interfacial layer on metal-oxide

This paper presents an investigation on the effects of micropillar physical parameters (height, pitch and diameter) on the optical and electrical performance of ZnO/ZnTe core-shell micropillar solar cells. It also studies the effect of the doping level in the absorber layer on the device’s performance considering the impact of Auger’s recombination. A Finite-Difference Time-Domain (FDTD) solver, Lumerical

In the referenced paper [1] , the micro-photograph shown in Fig. 1 (b) is of a representative HEMT. The measured HEMT of the paper has the following dimensions: ( ${\mathrm {LG}} =5\mu {\mathrm{ m}}, {\mathrm {W}} = 20\mu {\mathrm{ m}}, {\mathrm {LGS}} = {\mathrm {LGD}} = 6\mu {\mathrm{ m}}$ ). Fig. 1 has to be replaced with the corrected figure shown below:

The unified analytical model is proposed for SOI LDMOS (Silicon On Insulator Lateral Double-diffused Metal Oxide Semiconductor) based on the electric field modulation in this paper for the first time. The analytical solutions of the surface electric field distributions and potential distributions are derived on the basis of the 2-D Poisson equation. The variation of the buried layer parameters modulates

In this paper an IGZO memristor with multiple states and analog tuning extended capability is reported. The device has a planar structure and is fabricated by magnetron sputtering on glass substrate. The device resistance could be gradually increased and decreased within the range of one order of magnitude. Larger resistance changes are also possible but they are mostly irreversible. The obtained memristor

This special section of the IEEE JOURNAL OF ELECTRON DEVICES SOCIETY is dedicated to select papers presented at the 2019 IEEE S3S Conference, which was held Oct. 14– 17, 2019 in San Jose, CA, USA. The papers were selected based on their technical merits and relevance to the Journal and with the feedback from the Technical Committee of the conference and session chairs.

This work presents a detailed RF characterization of 28-nm FD-SOI nMOSFETs at cryogenic temperatures down to 4.2 K. Two main RF Figures of Merit (FoMs), i.e., current-gain cutoff frequency (f t ) and maximum oscillation frequency (f max ), as well as parasitic elements of the small-signal equivalent circuit, are extracted from the measured S-parameters. An improvement of up to ~130 GHz in ${\text{f}_{t}}$

A new self-converging programming characteristic in a single-poly floating-gate memory cell with full-compatibility to a CMOS logic technology is observed and studied. A uniquely design cell with a narrow-bridging line between two coupling capacitors promotes a localized charging effect at the electron tunneling site, leading to clamping of threshold voltage states. Through this mechanism, the new

The excellent area efficiency of dual-directional SCRs (DDSCRs) have made them desirable for low-voltage and high-voltage applications. However, to implement the required symmetrical structure, conventional DDSCRs have to lengthen their ESD discharge path. In addition, the low holding voltage of existing DDSCRs is not suitable for high-voltage applications. In this study, a novel DDSCR with a high

In this article, we report the design and fabrication for planar-type incandescent microfilaments on the silicon on insulator (SOI) wafer. The micro-electro-mechanical systems (MEMS) process with XeF 2 etching is used to construct the suspension structure for the reduction of thermal conduction. The fabricated line-type microfilament has a low operation voltage of 4 V. Besides, the operation voltages

In this paper, luminance compensation and optimization without internal or external sensing circuits to delay OLED degradation based on equivalent lifetime detection is proposed. The proposed method can estimate the dynamic luminance degradation with the equivalent lifetime equation derived by converting display time of any OLED cell at different luminance to a reference display time at a certain luminance

A novel 3.3 kV Shielded Insulated Gate Bipolar Transistor (SIGBT) is proposed in this paper. Unlike the partly shielded N-injector of the diode-clamped TIGBT, which is the carrier store layer, the SIGBT features a diode-clamped P-layer to completely shield the N-injector and to protect the N-injector from high electric field more steadily. Then, the N-injector can be heavily doped to reduce the on-state

In this paper, we introduce novel surface treatments of UV/Ozone and TMAH to solve the surface problem of gate recess of InAlAs/InGaAs InP-based HEMTs. The problem of nonstoichiometric surface of InP etch stopper layer was found to be the result of donor-like surface defects brought by HF damage, bringing troubles like kink effect, high gate leakage current and deteriorated noise performance. Through

Previous studies have suggested that the operating voltage and energy-delay properties of a nanoelectromechanical (NEM) system can be improved using the negative capacitance (NC) effect of ferroelectric materials. However, the advantages of using the NC effects alone have been utilized for perovskite ferroelectric materials, which is incompatible in complementary metal–oxide–semiconductor (CMOS) fabrication

In this work, the high temperature performance of a diamond Schottky PIN diode is reported in the range of 298–873 K. The diamond diode exhibited an explicit rectification up to 723 K with an excellent forward current density of >3000 A/cm 2 . The stability of the diode was investigated by exposing the sample to high temperature cycles (up to 873 K) for more than 10 times (totaling up to 120 hours)

In this paper, the SiC planar MOSFET with built-in reverse MOS-channel diode (SiC MCD-MOSFET) is investigated utilizing TCAD simulation tools. When the device is working as a freewheeling diode, the operation of the parasitic body diode is suppressed effectively due to the lower threshold voltage of the MCD. Therefore, the bipolar degradation issue can be completely solved. In addition, the SiC MCD-MOSFET

In this work, we investigated the effects of the crystal phase of ZrO 2 on charge trapping memtransistors (CTMTs) as synaptic devices for neural network applications. The ZrO 2 deposited through thermal (t-ZrO 2 ) atomic layer deposition (ALD) and plasma (p-ZrO 2 ) ALD were analyzed using an X-ray diffractometer, which indicated that the t-ZrO 2 consisted of pure cubic phase, whereas p-ZrO 2 consisted

In this paper, NBTI behaviors of Si pFinFETs are characterized with the measurement time down to ns-scale utilizing the fast $\text{V}_{\mathrm{ th }}$ measurement (FVM) technique. It is found that the NBTI behaviors in terms of $\text{V}_{\mathrm{ th}}$ shift is strongly influenced by the measurement speed even in the nano-second scale (ns-scale). The measurement phase itself during the NBTI characterization

This paper presents a high-speed ring oscillator (RO) with amorphous Indium-Gallium-Zinc-Oxide Thin-film transistors (a-IGZO TFTs). The proposed RO reduces the delay of a single stage inverter using intermediate signals generated within the RO, hence, improving the speed. To validate the proposed idea, two conventional ROs (with diode-load load inverter and bootstrapped pseudo-CMOS inverter) and the

Germanium is a promising alternative material for use in advanced technology nodes because it exhibits symmetrical mobility of holes and electrons. Embedded nonvolatile memory (NVM) is essential in electronic devices with integrated circuit (IC) technology, including future Ge-based technology. In this paper, we demonstrate Ge twin-transistor NVM with a fin field-effect transistor (FinFET) structure

High-K dielectric reduced surface field (RESURF) effects in high-voltage bulk FinFETs through three-dimensional simulation are discussed in this paper for the first time. Compared to a planar gate LDMOSFET where the length of the drift region is the same, dielectric RESURF significantly increases the optimal implant dose for the drift region to a higher value, although BV 2 /R on,sp is similar. By

In this paper, a new vertical double-diffused metal-oxide semiconductor field effect transistors (VDMOS) is proposed with the partial SiC/Si heterojunction (Partial SiC/Si VDMOS) under the drain electrode in this paper for the first time. The breakdown point transfer technique (BPT) is used to transfer the breakdown point from the radius of curvature is large to the radius of curvature is small in

In this work, the process of adhesive stamp mass-transfer of micro light-emitting diode (micro-LED) is optimized by a Support Vector Machine (SVM) model. The pick-up experiments have been performed repeatedly for hundreds of times from which the separation speed and the force between the stamp and the donor substrate are extracted as signal features. The SVM model with a Gaussian kernel function is

We have demonstrated a Si-based bottom-gate-type spin metal-oxide-semiconductor field-effect transistor (spin MOSFET) with an electron inversion channel at room temperature and showed the enhancement of the room-temperature effective spin diffusion length by “spin drift”. Our spin MOSFET was fabricated on a (001)-oriented silicon-on-insulator (SOI) substrate with a p -type ultrathin (8 nm) Si layer

Effects of oxygen flow on positive bias temperature instability and hot carrier injection are investigated in Amorphous InGaZnO (IGZO) thin film transistors. The oxygen flow can suppress the oxygen vacancy density, but introduce shallow states near the conduction edges. The electron can tunnel into gate oxide via these shallow states. As a result, the IGZO channel with oxygen flow has more electrons

We present a simple but accurate 1-D methodology of modeling for AlGaN/GaN High Electron Mobility Transistors (HEMTs), and by which means study its Reduced Surface Field (RESURF) effect. By using the Effective Concentration Profile Concept, the proposed methodology accounts the interactions between each layer and electric field crowding induced by gate/drain electrodes simultaneously without introducing

This paper proposes a theoretical model of photo-controlled quantum capacitors in double-gated graphene-insulator-graphene (DGGIG) structure for terahertz (THz) frequency and phase modulations. In the model, the current-voltage characteristics of each segment of the DGGIG structure are controlled by different gate voltages. Using the different voltages, the DGGIG structure can be used to either generate

Comprehensive channel material benchmarking for n- and pMOS are performed considering effects of quantum transport and carrier scattering. Various channel material options (Si, InAs, In 0.7 Ga 0.3 As, In 0.53 Ga 0.47 As, GaAs, and Ge for nMOS, Si and Ge for pMOS) are covered using hybrid simulation of quantum ballistic transport and semi-classical Monte Carlo. Current-voltage characteristics and performance

We develop a complete compact model to describe the forward current, reverse current, and capacitance of SiC Schottky barrier diodes. The model is based on the fundamental current mechanisms of thermionic emission and tunneling, and is usable over a large range of voltages, temperatures, and for a large range of device parameters. We also demonstrate good agreement with measured data. Furthermore,

2.3 kV 4H-SiC split-gate (SG) planar accumulation-channel power MOSFETs have been successfully manufactured in a 6 inch commercial foundry with good parametric distributions. The measured electrical characteristics of these devices are compared with conventional ACCUFETs manufactured with the same cell-pitch and process to quantify the improved performance. The gate charge and high-frequency figures-of-merit

Four process flow options for Complementary-Field Effect Transistors (C-FET), using different designs and starting substrates (Si bulk, Silicon-On-Insulator, or Double-SOI), were compared to assess the probability of process variation failures. The study was performed using virtual fabrication techniques without requiring fabrication of any actual test wafers. In the study, Nanosheet-on-Nanosheet stacked

In this paper, the effect of ultraviolet (UV) irradiation treatment of active layer IGZO on the bias stability of amorphous IGZO thin film transistor with etch stop (ES) structure is studied. Along with the increase in UV irradiation time, the surface of the IGZO film becomes smoother. An appropriate UV irradiation treatment cannot only improve the bias stress stability but also suppress the lump behavior

This Special Issue is dedicated to recent research in the field of compact modelling for circuit design. The topics included all device structures, provided it was demonstrated thet the presented compact modelling solutions were implementable in circuit design tools. The last Special Issue addressing compact modelling of all types of semiconductor devices was published in 2006. Since then, new device

In this paper, a temperature compensation method is proposed for active-matrix organic light-emitting diode (AMOLED) displays to achieve high luminance uniformity over a wide operating temperature range. The proposed temperature compensation method compensates for variation in OLED luminance according to temperature by adjusting the gamma voltages. To verify the proposed method, a built-in test circuit

Novel Al 0.75 Ga 0.25 N/Al x Ga 1-x N/Al 0.75 Ga 0.25 N/AlN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) with symmetrically-graded widegap Al x Ga 1-x N channel (x = 0.75 → 0.25 → 0.75) grown on a SiC substrate are investigated. Al 2 O 3 was devised as the gate dielectric by using a non-vacuum ultrasonic spray pyrolysis deposition (USPD) technique. Device characteristics

High-k HfO 2 has been widely adopted in Si based MOSFETs as gate dielectric for the superior control over gate leakage and channel electrostatics. However, in AlGaN/GaN HEMTs, the additional interface issue as well as high oxygen transparency of HfO 2 has hindered its practical applications. In this work, high-k Y 2 O 3 with ultra-low oxygen permeability and high thermodynamic robustness has been introduced

Stepped drift region thickness technique alters the drift region doping dose and its distribution, and therefore modulates the device's off-state characteristics. However, due to the sophisticated structure of the 2-D stepped drift region, the conventional 2-D modeling method is too complicated to provide a clear physical meaning. In this paper, based on the Effective Concentration Profile (ECP) theory

We demonstrated that p- and n-type activation layers can be formed in Si films by laser doping with H 3 PO 4 solution and Al 2 O 3 sol coating. The phosphorus and aluminum concentrations at the laser doped region were found to be over 10 19 cm -3 in Si films. In addition, generations of the activation carriers for n- and p-type layers were confirmed by Hall effects measurement. In this study, the characteristic

In this work, a comprehensive, TCAD based design approach for mmWave (mmW) GaN HEMTs is presented. Unique trade-offs between epi-layer design and HEMT's mmW performance are discussed. Effect of surface states on cut off frequency is modeled and presented. We have found that carrier trapping by the donor type interface states causes RF performance drift at high drain fields, which particularly leads

Recent progress in p-GaN trench-filling epitaxy has shown promise for the demonstration of GaN superjunction (SJ) devices. However, the presence of n-type interface charges at the regrowth interfaces has been widely observed. These interface charges pose great challenges to the design and performance evaluation of SJ devices. This work presents an analytical model for SJ devices with interface charges

To elaborate on the relationship between sophisticated 2-D doping profile of drift region and device's breakdown behavior, a unified analytical model for the SOI LDMOS is developed in this paper. The Effective Substrate Voltage (ESV) concept is proposed so that the derivation of electric field and breakdown voltage can be simplified significantly. The ESV indicates that the influence of 2-D doping

The iMemComp (Intelligent memristive computing) gates are a family of logic gates based on the RRAM (Resistive Random Access Memory) devices. It has potential advantage for the design of high-performance logic circuits, because the iMemComp NAND, AND, NOT, and transmission gates only consume single cycle, respectively. However, the original two-input iMemComp OR gate, which requires three cycles, is

As the 3D NAND technology developing toward more and more stack layers, it is essential to shrink the gate length (Lg) and inter-gate space (Ls). However, one of key concerns of scaling Lg/Ls 3D NAND flash is post-cycling data retention characteristics. The impact of cycling induced intercell trapped charge on two primary charge loss mechanisms (vertical and lateral charge loss) was studied in this

This paper introduces novel driving methods of the pull-down unit in a gate driver circuit for enhancement- and depletion-mode a-IGZO thin-film transistors (TFTs). The proposed gate driver circuit can achieve uniform output characteristics and effectively reduce the V OUT ripple voltage because the threshold voltage (V TH ) of the pull-down units is compensated regardless of the a-IGZO TFT operation

Vertical GaN-on-GaN Schottky barrier diodes based on as-grown and regrown samples were fabricated to investigate the effects of the etch-then-regrow process on device performance. The surface roughness increased slightly after dry etching and decreased after regrowth. According to X-ray diffraction results, the etch-then-regrow process caused a slight increase of defect density due to increased edge

Floating gate (FG) memory has long erasing time, which limits its application as an electronic synapse in online training. This paper proposes a novel enhanced floating gate memory (EFM) by TCAD simulation. Here, three other structures are simulated just for comparison. The simulation results show that the erasing speed is about 34ns while the other three need the time over 1.8ms, which makes the operation

Detective properties of a GaAs-based position sensitive detector (PSD) employing a very thin, highly doped p±-GaAs layer as a resistive layer were investigated. In addition to photovoltaic voltages, photovoltaic currents from a three-terminal PSD with two lateral electrodes and one transverse common electrode were also studied. In particular, lateral photovoltaic currents flowing into the two lateral

This paper presents a new reliability threat that affects 3D-NAND Flash memories when a read operation is performed exiting from an idle state. In particular, a temporary large increase of the fail bits count is reported for the layers read as first after a sequence of program/verify and a idle retention phase. The phenomenon, hereafter called Temporary Read Errors (TRE), is not due to a permanent

This paper investigates the inversion charge characteristics and quantum-capacitance induced inversion charge loss for In 0.53 Ga 0.47 As negative-capacitance FinFETs (NC-FinFETs) using theoretical calculation corroborated with numerical simulation. Our study indicates that, the boost of inversion charges due to negative capacitance increases with increasing remnant polarization Pr. In addition, the

To move towards a new generation powerful computing system, brain-inspired neuromorphic computing is expected to transform the architecture of the conventional computer, where memristors are considered to be potential solutions for synapses part. We propose and demonstrate a novel approach to achieve remarkable improvement of analog switching linearity in TaN/Ta/TaO x /Al 2 O 3 /Pt/Si memristors by

An image sensor based on wide band gap silicon carbide (SiC) has the merits of high temperature operation and ultraviolet (UV) detection. To realize a SiC-based image sensor the challenge of opto-electronic on-chip integration of SiC photodetectors and digital electronic circuits must be addressed. Here, we demonstrate a novel SiC image sensor based on our in-house bipolar technology. The sensing part

N-p-n InGaP/GaAs double heterojunction bipolar transistor has been successfully grown on a 200 mm Ge/Si wafer using metalorganic chemical vapor deposition with low defect density of 10 7 cm -2 . Non-gold metals of Ni/Ge/Al and Ti/Al are used to form the ohmic contact for small pieces device fabrication. Both direct-current (dc) and high-frequency characteristics of the device were measured. The device