Presents the table of contents for this issue of the publication.

The Journal of Electron Devices Society (J-EDS) was founded in 2013 and grown up very robustly since then.

Presents the reviewers who contributed to this publication in 2020.

This Special Issue is dedicated to recent research in the field of compact modeling of semiconductor devices. This is the first J-EDS Special Issue on compact modeling. In the last years, a number of new semiconductor device structures, for electronic and photonic applications, have been developed. Compact models are needed for the incorporation of these new devices in integrated circuits. Therefore

This article presents a state-of-art review of on-wafer S-parameter characterization of THz silicon transistors for compact modelling purpose. After, a brief review of calibration/de-embedding techniques, the paper focuses on the on-wafer calibration techniques and especially on the design and dimensions of lines built on advanced silicon technologies. Other information such as the pad geometry, the

A compact multi-gate MOSFET model is developed for high-voltage applications. The model includes the short-channel effects specific for thin-film MOSFETs with highly resistive drain contact. The short-channel effects are drastically reduced by the drain-resistance effect, which is consistently modeled by considering the whole potential distribution along the device. The overlap length is an important

In this article, an investigation has been performed to statistically analyze the entire subthreshold characteristics of tunnel field-effect transistor (TFET) depending on a gate work function variation (WFV). Firstly, the current variations are evaluated through turn-on voltage ( ${V} _{\mathrm{ ON}}$ ) and threshold voltage ( $V_{T}$ ) with help of technology computer-aided design (TCAD) simulation

A practical model, adequate for full reproduction of inhomogeneous Schottky diodes’ forward characteristics over wide high-temperature and bias ranges, is proposed. According to this ${p}$ -diode model, the Schottky contact current is considered to flow through ${m}$ parallel-connected internal diodes, each with stable, constant barrier height and specific series resistance (both main model parameters)

In this work, polycrystalline-silicon thin-film transistors (poly-Si TFTs) with asymmetric low metal contamination Ni-induced lateral crystallization (LC-NILC) poly-Si channel and high- $\kappa $ HfO 2 gate insulator (GI) have been successfully fabricated and demonstrated for the first time. The amounts of Ni diffused into the poly-Si film can be effectively reduced by Ni removal processes prior to

Process integration feasibility of UV nanosecond melt laser annealing (MLA) in 14 nm node generation FinFET’s contact for dopant surface segregation and activation is assessed by using a 3D TCAD simulation tool. In a n-type source/drain (S/D) in-situ phosphorous doped epilayer, Sb ion implantation is performed, considering the advantage of its surface segregation in lowering of the contact resistivity

One pivotal countermeasure in dealing with side-channel power analysis attacks is to maintain the signal-to-noise ratio of the power readings associated with the target as data-independent and as low as possible, in order to limit the attacker’s ability to deduce meaningful information from the target. The following study shows that the MSET (Multiple-State Electrostatically-Formed Nanowire Transistor)

A SiC trench MOSFET with an enhanced vertical RESURF effect is proposed and analyzed in this article. The device features a deep oxide trench surrounded by a P-type doping layer at the source-side. With the assistant depletion effect of the P-type layer, the concentration of the N-drift region is increased and the specific on-resistance ( ${R} _{\mathrm{ on,sp}}$ ) is thus reduced. The P-type doping

This note clarifies an important approximation used to simulate the breakdown field in the SiO 2 liner of a SiC Charge-Sheet Superjunction - a new power device structure - reported by Akshay and Karmalkar (2020). This electric field simulation sought to assure that the new device does not suffer from SiO 2 reliability problems. The note answers two questions: (a) Why do we remove the SiO 2 liner which

This Special Issue is assembled from a selection of highly-rated technical papers presented at the 4 th IEEE Electron Devices Technology and Manufacturing Conference 2020, EDTM 2020. It took place during April 6-21, 2020 and signified the 1 st of its kind as a virtual conference financially-sponsored by the Electron Devices Society (EDS). The original EDTM 2020 was planned as a full three-day event

In this article, we focus on the physical modeling of the nonlinear operation of intrinsic photoconductive semiconductor switches (PCSS) based on 4H-SiC using coupled electrical and optical simulations to provide performance bounds of the switch as a function of material and geometry parameters, as well as applied bias. We also conduct a full design-space exploration to identify the optimal operating

We discuss details of the Charge Sheet SuperJunction (CSSJ) in 4H-Silicon Carbide (SiC). This device was earlier proposed in Si material. A CSSJ is obtained by replacing the p-pillar of a SJ by a bilayer insulator, e.g., Al 2 O 3 /SiO 2 ; the inter-layer interface of this insulator has a negative charge-sheet, whose magnitude is easily controlled via the insulator deposition temperature. This charge-sheet

Recess processes for the fabrication of normally-off GaN HEMTs generally compromise devices’ on-state performance. In this work, recess-free quasi-normally-off GaN HEMTs with a threshold voltage of 0.24 V is realized by local control of two-dimensional electron gas (2DEG) density. The devices feature a $0.1~{\mu }\text{m}$ gate length, SiN x stress liner, and comb gate. SiN x liner can provide significant

A methodology has been proposed to accurately model the gate stack of Gallium Nitride (GaN) based metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs). Small-signal analysis has been performed for the device biased in the spill-over region, where electrons accumulate at the insulator/III-Nitride ’critical’ interface. Accounting for the barrier layer resistance with an accurate

In this work, the computational analysis on use of nanostructures to both III-Nitride and Kesterite solar cell are presented and compared. The scope behind the comparative analysis of III-nitride and kesterite material based solar cells is due to their excellent material properties, which made them suitable as an absorber for solar cells. In III-nitride based solar cells, stress induced polarization

In this article, we present a channel thickness dependent analytical model for MoS 2 symmetric double-gate FETs including negative capacitance (NC) effect. In the model development, first thickness dependent model of the baseline 2D FET is developed, and later NC effect is included in the model using the Landau-Khalatnikov (L-K) relation. To validate baseline model behavior, density functional theory

Nanosheet field-effect transistors (NSFETs) have emerged as a novel device replacement for sub-7nm CMOS technology nodes. However, due to smaller fin thickness (Tfin = 5nm), NSFETs are more vulnerable to the process-induced variations. Among various types of process-induced variations, Line edge roughness (LER) is becoming a significant concern for multi-gate field-effect transistors (MugFETs) with

In this work, we investigate the impact of Si-SiO 2 interface traps on the performance of negative capacitance transistor, which is a promising emerging technology that aims at achieving a steep sub-threshold slope. Interface traps induced degradation is well known to be one of the major concerns when it comes to reliability. We focus on investigating the impact of different interface trap concentrations

This article presents a systematic study on the analog and radio-frequency (RF) performance of type-II staggered heterostructure ${p}$ -channel tunnel field-effect transistors ( ${p}$ TFETs) with Ge (Germanium) channel and different compound semiconductor source. In order to study the figure-of-merits (FOMs) of analog and RF performances, various Ge-channel ${p}$ TFETs are designed with Ge, GaAsP,

This article describes a novel Low Power Current Source Tunable Inductor (LPCSTI) for CMOS Radio Frequency Integrated Circuits (RFIC). The LPCSTI comprises a deep triode common source transistor, a stabilizer resistor and a coupling capacitor which is capable to increase the physical inductance value up to 80% from its default value thus achieving higher inductance per area. Integration of the tuner

A highly customizable hybrid sensor system, composed of a silicon integrated circuit (IC) chip and an organic field effect transistor (OFET) transducer, is proposed for Internet of Everything (IoE). In such a system, the silicon IC chip performs high performance and complex signal processing, and the OFET transducer provides flexible or conformable large area coverage and more friendly interfaces to

The Kretschmann-based surface plasmon resonance (K-SPR) sensor was developed using multilayer graphene and molybdenum disulphide (MoS 2 ) structures on a plasmonic gold (Au) layer for ethanol detection. In this configuration, the SPR spectra of minimum reflectance versus SPR angle was used to determine the sensitivity, detection accuracy and quality factor as the main figure of merit (FOM). Both graphene

In optical sensors and imagers, high gain that leads to high sensitivity and high signal to noise ratio (SNR) is often desirable. One popular approach is avalanche photomultiplication initiated by impact ionization in an avalanche photodiode or similar devices and the other approach is active pixel sensor (APS) with in-pixel amplifier. However, the former requires high electric field which induces

This article reports design, fabrication and analysis of a novel under-transistor (under-FET) in-hole thermal sensor diode structure. Being able to accurately monitor self-heating of individual transistor in-operando, the under-FET temperature sensor enables smart full-chip run-time thermal management with spatial resolution down to single transistor level. The in-hole thermal sensors were fabricated

In spin-transfer torque magnetoresistive random access memory, the magnetization dynamics of a free layer is usually assumed to be determined by the torque created via a position-independent current density. In circuits, however, it is the voltage, not the current density, which stays fixed during switching. Therefore, the approximate evaluation of the torque based on a fixed current density becomes

Spiking neural networks (SNNs) have attracted considerable attention as next-generation neural networks. As SNNs consist of devices that have spike-timing-dependent plasticity (STDP) characteristics, STDP is one of the critical characteristics we need to consider to implement an SNN. In this study, we generated the STDP of a biological synapse with non-volatile tunnel-field-effect-transistor (tunnel

In this article, by using neural network, we proposed a method to optimize Fully-Depleted (FD) Silicon-on-Insulator (SOI) Field-Effect-Transistor (FET) structures to maximize the on/off current ratio for 14-nm node (70-nm Gate Pitch) System-on-Chip (SoC) and sequential 3-dimensional integrated circuit (3DIC). Using machine learning method, the neural network accurately predicted the electrical behaviors

The physics-based BTI Analysis Tool (BAT) is used to model the time kinetics of threshold voltage shift ( $\Delta {\mathrm{ V}}_{\mathrm{ T}}$ ) during and after NBTI in p-channel planar bulk and FDSOI MOSFETs and SOI FinFETs. BAT uses uncorrelated contributions from the trap generation at the channel/gate insulator interface ( $\Delta {\mathrm{ V}}_{\mathrm{ IT}}$ ) and gate insulator bulk ( $\Delta

On-chip electrostatic discharge (ESD) protection design for integrated circuits (ICs) is a challenging design-for-reliability problem. Since ESD events involve very high current transients in very short time period, current crowding is unavoidable, which leads to local overheating and creates local hot spots, resulting in ESD thermal failures. Therefore, layout design plays a critical role in practical

Charged device model (CDM) electrostatic discharge (ESD) protection remains a huge challenge for integrated circuit (IC) reliability designs. The “internal-oriented” CDM model and the “external-oriented” human body model (HBM) describe fundamentally different ESD phenomena. Through the comprehensive analysis, this article concludes that the classic pad-based ESD protection methods, commonly used for

Wafer level chip scale package (WLCSP) is true chip scale package with low cost by eliminating package substrate. The direct chip-to-board attach through solder joints provides low interconnect inductance and resistance, as well as improved thermal performance. These properties make WLCSP a packaging format well suited for 5G radio frequency (RF) applications where minimized package size and parasitics

In this article, a novel bipolar-field-effect composite power transistor, called SiC GCBT (Silicon Carbide Gate-Controlled Bipolar-field-effect Composite Transistor) is presented and studied. The structure is characterized by the use of the base-gate short connection mode, instead of the conventional base-source short connection mode in SiC Vertical Double-diffusion MOSFET (VDMOS). It found that the

Adding passive components in a conventional IGBT gate driver is a simple method to reduce transient current/voltage spikes during switching, but the extra devices and power loss make them less attractive. Alternatively, active gate drivers can improve the switching behavior, but are limited to specific devices and applications from the increased complexity of functions and feedback topology. This article

The MOS-controlled Thyristor (MCT) has been characterized by MOS-gating, high current rise rate, and high blocking capabilities. The anode short MCT (AS-MCT) is distinguished from the conventional MCT by an anode-short structure, which forms an extracting path for the leakage current at the gate-ground and develops a normally-off characteristic. The AS-MCTs are ideal switches for pulse discharge application

In this work, we demonstrated a HfO 2 -based ferroelectric field-effect transistor (FeFET) in series with a HfAlO ferroelectric capacitor for memory application and further investigated the impact of the ferroelectric capacitor with different thicknesses and areas. It was revealed that the memory window of the FeFET has a significant correlation with the ferroelectric capacitor from the transfer curves

A novel planar design of Gunn diode with a shaped anode contact, utilizing Monte Carlo simulations, has been shown to have produced 0.3 THz frequency current output when operated in delayed mode. Two novel anode designs are investigated here, one with two fixed distances, and the other with three fixed distances between the cathode and anode electrodes. The corresponding waveforms generated, show two

The output features of pixels in CMOS image sensors (CISs) are influenced by different exposure conditions. This article presents an analytical model to describe the output characteristics of the exposure process in pinned photodiode (PPD) CMOS image sensors with the accumulation of three charge sources: photogenerated charge, p-n junction-generated charge, and emission charge. In the proposed model

In recent years, piezoelectric materials have been widely investigated for harvesting energy from ambient vibrations. A vibrating piezoelectric device (PD) generates alternating current (AC), which needs to be converted into direct current (DC) for powering electronic devices or for storage. A traditional full-wave bridge rectifier (FBR) interface circuit serves this purpose, but it suffers from high

The breakdown voltage model of Si-substrated AlGaN/GaN HEMTs with gate and drain field plates is proposed in this work. The silicon substrate and GaN buffer are considered as the depletion region in the modeling process. The analytical model shows great simplicity and veracity. It gives physical insights into the breakdown characteristics of the AlGaN/GaN HEMTs. The avalanche breakdown occurs at the

FinFET devices with and without LDD implantation has been studied for dimensions compatible with leading 14nm technology node. Devices without LDD have better electrostatic characteristics with SS = 65mV/dec and DIBL = 33mV. The nFET transistors with no LDD have device Vtsat mismatch reduction by 20%, together with retained device reliability of HCI as compared to devices with LDD. A full range of

The MOS-controlled Thyristor (MCT) has been characterized by MOS-gating, high current rise rate, and high blocking capability. The anode short MCT (AS-MCT) is distinguished from conventional MCT by an anode-short structure, which develops a normally-off characteristic. As a composite structure made of metal-oxide-silicon and bipolar junction transistors, AS-MCT is susceptible to displacement damage

This work, for the first time, experimentally demonstrates a TCAD-Machine Learning (TCAD-ML) framework to assist the analysis of device-to-device variation and operating (ambient) temperature without the need of physical quantities extraction. The ML algorithm used in this work is the Principal Component Analysis (PCA) followed by third order polynomial regression. After calibrated to limited ‘expensive’

Recently, a few compact logic function realizations such as AND, OR, NAND and NOR have been proposed using double-gate tunnel field-effect transistor (DGTFET) with independent gate-control. In this article, using two-dimensional device simulations, we propose to realize the exclusive-OR (XOR) and exclusive-NOR (XNOR) logic functions. To implement an XOR function, a dual-material DGTFET (DM-DGTFET)

In this work, an improved 4H-SiC insulated gate bipolar transistor (IGBT), or CTH-IGBT, with a trench p-polySi/p-SiC heterojunction on the backside of the device is proposed to reduce the turn-off energy loss ( $E_{off}$ ) and turn-off time ( $T_{off}$ ). The electrical properties of the proposed and contrast structures are all simulated using the ATLAS simulation software to research the working mechanism

We successfully fabricate the Si 0.8 Ge 0.2 channel fin field-effect-transistor (FinFET) with 5 nm ultra-thin fin width and high aspect ratio ( $\sim 10\times $ ) on silicon-on-insulator (SOI) substrate by simple two-step dry etching. In comparison of the conventional Si FinFET, our proposed SiGe ultra-thin FinFETs (Si 0.8 Ge 0.2 UT-FinFET) at V D = 0.75 V & V G = 1.5 V shows higher ON-state current

Poly-Si channels need well passivated by using hydrogen passivation process in 3D NAND flash memories for better poly-Si quality with low trap density. It is believed that Xtacking 3D NAND flash memory has the advantage of flexible arranging the passivation process. In this article, two different passivation locations were compared in Xtacking structure to achieve better trap passivation. An optimized

A novel insulated gate bipolar transistor (IGBT) using a deep trench filled with SiO 2 and high- ${k}$ dielectric film (HKF) is presented. The deep trench with the HKF can provide rapid depletion of the drift region during the turn-off transient, eliminating the tail current and reducing the turn-off loss. According to the simulation results, with a relative permittivity of 475 and a 400 nm thickness

Harvesting the potential performance of GaN-based devices in terms of the areal power density and reliability, relies on the efficiency of their thermal management. Integration of extremely high thermal conductivity Single-crystalline CVD-diamond serves as an efficient solution to their strict thermal requirements. However, the major challenge lies in the Thermal Boundary Resistance (TBR) at the interface

The memristor, emulating biological synapse, is recognized as one key way to overcome the classic von Neumann bottleneck. In this work, by using active metal Cu as electrode, the device of Cu/GeTeO x /TiN exhibited typical resistive switching characteristic based on the electrochemical metallization mechanism (ECM). Moreover, it realized gradual potentiating and depressing conduction under DC and AC

A SPICE compatible compact modeling framework is discussed for Hot Carrier Degradation (HCD) stress spanning the entire drain ( $\text{V}_{\mathrm{ D}}$ ) and gate ( $\text{V}_{\mathrm{ G}}$ ) voltage space and wide range of temperature (T). It can model the HCD time kinetics measured using different methods such as shift in threshold voltage ( $\Delta {\mathrm{ V}}_{\mathrm{ T}}$ ), linear ( $\Delta

In this article, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of the thickness of the ferroelectric on the I-V characteristics. Importantly, our model predicts that the negative capacitance minimizes short channel effects and

Fabrication, physical modeling and dynamic response of $p$ -type Al-doped SnO x active channel thin film transistors (TFTs) are presented for the potential application of ultra-high definition (UHD) displays. After deposition of Al-doped SnO x active layer using reactive co-sputtering, the channel was treated with plasma fluorination which improve the device performance of high $I_{ON}/I_{OFF}$ ratio

Optimization of interface characteristics between dielectric and non-polar GaN surface is very important and urgent for vertical GaN MOS device whose channel is perpendicular to the conventional c-plane. In this work, the effects of piranha cleaning and N 2 post deposition annealing (PDA) to the interface between atomic-layer-deposited (ALD)-Al 2 O 3 and a-plane GaN samples were comprehensively investigated

High Q-factor inductors are critical in designing high performance RF/microwave circuits on SOI technology. Substrate losses is a key limiting factor when designing inductors with high Q-factors. In this context, we report a substrate engineering method that enables improvement of quality factors of already fabricated inductors on SOI. A novel femtosecond laser milling process is utilized for the fabrication

In this article, we propose a high Schottky barrier source/drain contacts based bilateral gate and assistant Gate controlled bidirectional tunnel field Effect transistor (HSB-BTFET). Different from Schottky barrier (SB) MOSFET which use lower Schottky barrier to produces the thermionic emission current, the proposed HSB –BTFET utilizes higher Schottky barrier to minimize the thermionic emission current

An In 0.53 Ga 0.47 As/InAs composite channel MOS-HEMT exhibiting peak $f_{\tau } = 511$ GHz and peak ${f} _{\max }= 285$ GHz is demonstrated. Additionally, another device exhibiting peak $f_{\tau } = 286$ GHz and peak ${f} _{\max }= 460$ GHz is reported. The devices have a 1 nm / 3 nm Al x O y N z interfacial layer and ZrO 2 gate dielectric on a 2 nm / 4 nm In 0.53 Ga 0.47 As / InAs composite channel