We present a simple but accurate 1-D methodology of modeling for AlGaN/GaN High Electron Mobility Transistors (HEMTs), and by which means study its Reduced Surface Field (RESURF) effect. By using the Effective Concentration Profile Concept, the proposed methodology accounts the interactions between each layer and electric field crowding induced by gate/drain electrodes simultaneously without introducing

This paper proposes a theoretical model of photo-controlled quantum capacitors in double-gated graphene-insulator-graphene (DGGIG) structure for terahertz (THz) frequency and phase modulations. In the model, the current-voltage characteristics of each segment of the DGGIG structure are controlled by different gate voltages. Using the different voltages, the DGGIG structure can be used to either generate

Comprehensive channel material benchmarking for n- and pMOS are performed considering effects of quantum transport and carrier scattering. Various channel material options (Si, InAs, In 0.7 Ga 0.3 As, In 0.53 Ga 0.47 As, GaAs, and Ge for nMOS, Si and Ge for pMOS) are covered using hybrid simulation of quantum ballistic transport and semi-classical Monte Carlo. Current-voltage characteristics and performance

2.3 kV 4H-SiC split-gate (SG) planar accumulation-channel power MOSFETs have been successfully manufactured in a 6 inch commercial foundry with good parametric distributions. The measured electrical characteristics of these devices are compared with conventional ACCUFETs manufactured with the same cell-pitch and process to quantify the improved performance. The gate charge and high-frequency figures-of-merit

In this paper, the effect of ultraviolet (UV) irradiation treatment of active layer IGZO on the bias stability of amorphous IGZO thin film transistor with etch stop (ES) structure is studied. Along with the increase in UV irradiation time, the surface of the IGZO film becomes smoother. An appropriate UV irradiation treatment cannot only improve the bias stress stability but also suppress the lump behavior

This Special Issue is dedicated to recent research in the field of compact modelling for circuit design. The topics included all device structures, provided it was demonstrated thet the presented compact modelling solutions were implementable in circuit design tools. The last Special Issue addressing compact modelling of all types of semiconductor devices was published in 2006. Since then, new device

In this paper, a temperature compensation method is proposed for active-matrix organic light-emitting diode (AMOLED) displays to achieve high luminance uniformity over a wide operating temperature range. The proposed temperature compensation method compensates for variation in OLED luminance according to temperature by adjusting the gamma voltages. To verify the proposed method, a built-in test circuit

Novel Al 0.75 Ga 0.25 N/Al x Ga 1-x N/Al 0.75 Ga 0.25 N/AlN metal-oxide-semiconductor heterostructure field-effect transistors (MOS-HFETs) with symmetrically-graded widegap Al x Ga 1-x N channel (x = 0.75 → 0.25 → 0.75) grown on a SiC substrate are investigated. Al 2 O 3 was devised as the gate dielectric by using a non-vacuum ultrasonic spray pyrolysis deposition (USPD) technique. Device characteristics

High-k HfO 2 has been widely adopted in Si based MOSFETs as gate dielectric for the superior control over gate leakage and channel electrostatics. However, in AlGaN/GaN HEMTs, the additional interface issue as well as high oxygen transparency of HfO 2 has hindered its practical applications. In this work, high-k Y 2 O 3 with ultra-low oxygen permeability and high thermodynamic robustness has been introduced

Stepped drift region thickness technique alters the drift region doping dose and its distribution, and therefore modulates the device's off-state characteristics. However, due to the sophisticated structure of the 2-D stepped drift region, the conventional 2-D modeling method is too complicated to provide a clear physical meaning. In this paper, based on the Effective Concentration Profile (ECP) theory

We demonstrated that p- and n-type activation layers can be formed in Si films by laser doping with H 3 PO 4 solution and Al 2 O 3 sol coating. The phosphorus and aluminum concentrations at the laser doped region were found to be over 10 19 cm -3 in Si films. In addition, generations of the activation carriers for n- and p-type layers were confirmed by Hall effects measurement. In this study, the characteristic

In this work, a comprehensive, TCAD based design approach for mmWave (mmW) GaN HEMTs is presented. Unique trade-offs between epi-layer design and HEMT's mmW performance are discussed. Effect of surface states on cut off frequency is modeled and presented. We have found that carrier trapping by the donor type interface states causes RF performance drift at high drain fields, which particularly leads

Recent progress in p-GaN trench-filling epitaxy has shown promise for the demonstration of GaN superjunction (SJ) devices. However, the presence of n-type interface charges at the regrowth interfaces has been widely observed. These interface charges pose great challenges to the design and performance evaluation of SJ devices. This work presents an analytical model for SJ devices with interface charges

To elaborate on the relationship between sophisticated 2-D doping profile of drift region and device's breakdown behavior, a unified analytical model for the SOI LDMOS is developed in this paper. The Effective Substrate Voltage (ESV) concept is proposed so that the derivation of electric field and breakdown voltage can be simplified significantly. The ESV indicates that the influence of 2-D doping

The iMemComp (Intelligent memristive computing) gates are a family of logic gates based on the RRAM (Resistive Random Access Memory) devices. It has potential advantage for the design of high-performance logic circuits, because the iMemComp NAND, AND, NOT, and transmission gates only consume single cycle, respectively. However, the original two-input iMemComp OR gate, which requires three cycles, is

As the 3D NAND technology developing toward more and more stack layers, it is essential to shrink the gate length (Lg) and inter-gate space (Ls). However, one of key concerns of scaling Lg/Ls 3D NAND flash is post-cycling data retention characteristics. The impact of cycling induced intercell trapped charge on two primary charge loss mechanisms (vertical and lateral charge loss) was studied in this

This paper introduces novel driving methods of the pull-down unit in a gate driver circuit for enhancement- and depletion-mode a-IGZO thin-film transistors (TFTs). The proposed gate driver circuit can achieve uniform output characteristics and effectively reduce the V OUT ripple voltage because the threshold voltage (V TH ) of the pull-down units is compensated regardless of the a-IGZO TFT operation

Vertical GaN-on-GaN Schottky barrier diodes based on as-grown and regrown samples were fabricated to investigate the effects of the etch-then-regrow process on device performance. The surface roughness increased slightly after dry etching and decreased after regrowth. According to X-ray diffraction results, the etch-then-regrow process caused a slight increase of defect density due to increased edge

Floating gate (FG) memory has long erasing time, which limits its application as an electronic synapse in online training. This paper proposes a novel enhanced floating gate memory (EFM) by TCAD simulation. Here, three other structures are simulated just for comparison. The simulation results show that the erasing speed is about 34ns while the other three need the time over 1.8ms, which makes the operation

Detective properties of a GaAs-based position sensitive detector (PSD) employing a very thin, highly doped p±-GaAs layer as a resistive layer were investigated. In addition to photovoltaic voltages, photovoltaic currents from a three-terminal PSD with two lateral electrodes and one transverse common electrode were also studied. In particular, lateral photovoltaic currents flowing into the two lateral

This paper presents a new reliability threat that affects 3D-NAND Flash memories when a read operation is performed exiting from an idle state. In particular, a temporary large increase of the fail bits count is reported for the layers read as first after a sequence of program/verify and a idle retention phase. The phenomenon, hereafter called Temporary Read Errors (TRE), is not due to a permanent

This paper investigates the inversion charge characteristics and quantum-capacitance induced inversion charge loss for In 0.53 Ga 0.47 As negative-capacitance FinFETs (NC-FinFETs) using theoretical calculation corroborated with numerical simulation. Our study indicates that, the boost of inversion charges due to negative capacitance increases with increasing remnant polarization Pr. In addition, the

To move towards a new generation powerful computing system, brain-inspired neuromorphic computing is expected to transform the architecture of the conventional computer, where memristors are considered to be potential solutions for synapses part. We propose and demonstrate a novel approach to achieve remarkable improvement of analog switching linearity in TaN/Ta/TaO x /Al 2 O 3 /Pt/Si memristors by

An image sensor based on wide band gap silicon carbide (SiC) has the merits of high temperature operation and ultraviolet (UV) detection. To realize a SiC-based image sensor the challenge of opto-electronic on-chip integration of SiC photodetectors and digital electronic circuits must be addressed. Here, we demonstrate a novel SiC image sensor based on our in-house bipolar technology. The sensing part

N-p-n InGaP/GaAs double heterojunction bipolar transistor has been successfully grown on a 200 mm Ge/Si wafer using metalorganic chemical vapor deposition with low defect density of 10 7 cm -2 . Non-gold metals of Ni/Ge/Al and Ti/Al are used to form the ohmic contact for small pieces device fabrication. Both direct-current (dc) and high-frequency characteristics of the device were measured. The device

The Low Frequency Noise (LFN) in MOSFETs is critical to Signal-to-Noise Ratio (SNR) demanding circuits. Buried Channel (BC) MOSFETs are commonly used as the source-follower transistors for CCDs and CMOS image sensors (CIS) for lower LFN. It is essential to understand the BC MOSFETs noise mechanism based on trap parameters with different transistor biasing conditions. In this paper, we have designed

GaN-based planar Gunn diodes are promising terahertz sources for monolithic microwave and terahertz integrated circuits (MMICs and MTICs, respectively) due to high output power and easiness of fabrication and circuit integration. However, high lateral current in the 2DEG channel may lead to failures such as early breakdown and suppression of oscillations. In this paper, we will, for the first time

The impact of linear correlation between lognormal distribution grain size mean and sigma along the polysilicon channel on threshold voltage (Vth) variability has been investigated in three dimensional (3D) NAND flash. The variety of grain size mean and sigma results in the unstable Vth variability. To obtain a stable Vth distribution with various grain size mean, the grain size mean dependent Vth

In this paper, the degradation behavior of the electrical characteristics was investigated, and trap analysis based on low-frequency noise (LFN) was carried out for the commercial 1.2-kV/30-A silicon carbide (SiC) power MOSFETs under repetitive short-circuit (SC) stress. The experiment results show that the on-state resistance (R dson ) and threshold voltage (V th ) increase significantly. Meanwhile

The high performance Hf doped ZnO (Hf-ZnO) flexible thin film transistors (TFTs) were fabricated using Ag NWs as gate electrode and high-k HfO 2 as dielectric. The field effect mobility of Hf-ZnO is 14.7 cm 2 /Vs, I on /I off ratio is more than 106, and the subthreshold swing is about 0.26 V/dec. Furthermore, after 5000 bending cycles test, the TFTs with Ag NWs still maintain a superior performance

This paper reports on-chip rail-to-rail timing signals generation thin-film circuits for the first time. These circuits, based on a-IGZO thin-film transistors (TFTs) with a simple staggered bottom gate structure, allow row and column selection of a sensor matrix embedded in a flexible radiation sensing system. They include on-chip clock generator (ring oscillator), column selector (shift register)

We have developed a manufacturing-friendly spin-orbit torque magnetic random access memory (SOT-MRAM) technology in CMOS compatible 8-inch fab process. The proposed SOT-MRAM process technology resolves etching non-uniformity and reduction of high resistivity heavy-metal nanowire resistance issues. Besides, we present device size-dependent switching current threshold in the proposed SOT-MRAM cell structure

In [1] , the revised date was incorrect. It should be as follows: “revised 4 December 2019”

This paper proposes a new 8T nonvolatile SRAM (nvSRAM) cell employing ULP FinFETs and ferroelectric FinFETs to enable energy-efficient and low-latency store/recall operations. Different from other types of nvSRAM requiring additional circuitry or nonvolatile memories connected to a standard 6T SRAM cell to achieve nonvolatility, the proposed hybrid nvSRAM cell reduces the area penalty by embedding

This paper reports generalized design solutions for the punch-through and nonpunch-through drift layers in 4H-SiC. In general, the critical electric field relation of Konstantinov is widely used to design the drift parameters in 4H-SiC due to its accuracy. In this paper, a fitted version of Konstantinov's critical electric field relation is used to derive the generalized optimum parameters for the

The key feature of NCFET (negative capacitance field effect transistor) is its sub-threshold slope (SS) <; 60 mV/decade at 300 K. In this work, the n-type NCFET (i.e., pull-down (PD) and passgate (PG) transistor in six-transistor (6T) SRAM bit-cell) has SS of 53.92 mV/decade, and the p-type NCFET (i.e., pull-up (PU) transistor in the 6T SRAM bit-cell) has SS of 58.96 mV/decade. In the NCFET-based SRAM

Based on the device physics, a mobility model for organic thin-film transistors (OTFTs) is presented considering temperature and contact resistance. As a function of the surface potential, the mobility model including hopping mechanism is able to explain the dependence of temperature and gate bias. The contact resistance is also considered in order to extract the correct mobility. Furthermore, with

A novel trench shielded planar gate IGBT (TSPG-IGBT) with self-biased pMOS is proposed in this paper. It features a P-layer beneath the trench of the TSPG-IGBT to form a self-biased pMOS, which provides an additional path for the hole current and clamps the potential of the nMOS's intrinsic drain for lower saturation current. In the off-state, with the increasing potential of the N-cs (N-doped carrier

Based on transmission line modeling, a new technology of collaborative applying the ultralow-k dielectric and the high-k dielectric materials in coupled multilayer graphene nanoribbon (MLGNR) interconnects (i.e., case 4) to reduce propagation delay and to expand 3-dB bandwidth of the conventional pristine (undoped) MLGNR interconnects is proposed in this paper. By using the decoupling technique and

We extended the density-gradient (DG) model to include a second-order quantum correction (SOQC) term. The DG model has been widely used as a device simulation model capable of simulating quantum effects in efficient way. However, when only the first order quantum correction term is considered in the DG model, it is difficult to accurately describe device characteristics such as carrier density or potential

A current of 1.54 kA was obtained under a bias voltage of only 1.6 kV by employing a single photoconductive semiconductor switch (PCSS) excited by a laser diode (LD) with energy of 4 μJ. In this work, an opposed contact structure PCSS was used instead of a lateral structure one. We show that a avalanche multiplication rate of PCSS as high as 258 has been obtained. The effects of the electric field

Normally-off p-GaN gated AlGaN/GaN high electron mobility transistors (HEMTs) were developed. Oxygen plasma treatment converted a low-resistive p-GaN layer in the access region to a high-resistive GaN (HR-GaN); that oxygen plasma treatment used an AlN layer as an oxygen diffusion barrier layer to prevent further oxidizing of the underlying AlGaN barrier layer, and to ensure that the low-resistive p-GaN

This work proposes a new pixel circuit for active-matrix organic light-emitting (AMOLED) smartwatch displays with a low frame rate. Within the long emission period, the leakage current of a low-temperature polycrystalline silicon thin-film transistor (LTPS TFT) is reduced to suppress the distortion of the driving voltage at the gate node of the driving TFT. Based on the measured electrical characteristics

Gallium nitride (GaN)-based power devices enable high power density and high switching frequency for power electronics systems. For the emerging vertical GaN devices, the electric field crowding around the edge of the main junction could result in premature breakdown. It is challenging to employ the commonly used junction-based termination techniques as in Si and SiC high-voltage devices for vertical

A 0.28-inch InGaN-based blue micro-LED display with 256 pixel-per-inch resolution and a pitch of 100 μm was successfully fabricated in this study. A thick Ti/Al/Ti/Au interconnection metal was deposited on the n-type gallium nitride (n-GaN) region to reduce the interconnection resistance. The micro-LED array with interconnection metal exhibits better electrical property consistency as compared with

The VLT technique features for its irregular thickness of drift region and therefore realize the even surface electric field even with a uniformly doped drift region. However, the sophisticated structure of the drift region also making 2-D methods impractical in both modeling and explaining VLT's physical nature. In this paper, based on the Effective Concentration Profile (ECP) theory, a simple but

This paper presents a device matching study of a commercial 40-nm bulk CMOS technology operated at cryogenic temperatures. Transistor pairs and linear arrays, optimized for device matching, were characterized over the temperature range from 300 K down to 4.2 K. The device parameters relevant for mismatch, i.e., the threshold voltage and the current factor, were extracted, from which the change in both

In this letter, a compact model for charge and drain current in molybdenum disulfide (MoS 2 ) field-effect transistors (FETs) is developed, which is valid from ballistic to quasi-ballistic to drift-diffusion electronic transport regimes. Considering the influence of trap charges in MoS 2 transistors, a physical-based and analytical charge model is derived. Based on the virtual source model which applies

Due to the high number of reachable conductance levels in resistive switching devices, they are good candidates to implement artificial synaptic devices. In this work, we have studied the control of the intermediate conductance levels in HfO 2 -based MIM capacitors using current pulses. The set transition can be controlled in a linear way using this kind of signal. The potentiation characteristic is

This paper reports on the modulation of Schottky barrier heights (SBH) on three different orientations of $\beta $ -Ga 2 O 3 by insertion of an ultra-thin SiO 2 dielectric interlayer at the metal-semiconductor junction, which can potentially lower the Fermi-level pinning (FLP) effect due to metal-induced gap states (MIGS). Pt and Ni metal-semiconductor (MS) and metal-interlayer-semiconductor (MIS)

This work presents a novel general compact model for 7-nm technology node devices like FinFETs as an extension of previous conventional compact model that based on some less accurate elements including one-dimensional Poisson equation for three-dimensional devices and analytical equations for short channel effects, quantum effects and other physical effects. The general compact model exhibits efficient

This work proposes a hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) gate driver with a low-leakage capacitive coupling structure to reduce the delay of the clock signal. The proposed circuit suppresses the fluctuation in the gate node of the driving TFT induced by clock-feed-through effect, reducing the leakage current that flows from the clock signal line to the power source line

We investigated the effect of material choice and orientation in limiting source to drain tunneling (SDT) in nanowire (NW) p-MOSFETs. Si, Ge, GaSb, and Ge 0.96 Sn 0.04 nanowire MOSFETs (NWFETs) were simulated at a scaled gate length ( ${\mathrm{ L}}_{\mathrm{ G}}$ ) of 10 nm, using rigorous ballistic quantum transport simulations. To properly account for the non-parabolicity and anisotropy of the valence

In this paper, we demonstrate high-performance quasi-vertical GaN-on-Sapphire Schottky barrier diodes (SBD) with a reverse GaN p-n junction termination (RPN). The SBD has a current output of 1 kA/cm 2 at $V_{F}=2.5$ V, a low $V_{on}$ of 0.66 V ± 0.017 V, a low $R_{on,sp}$ of 1.4 $\text{m}\Omega \cdot $ cm 2 , current ON/OFF ratio of over $10^{9}$ (−3 V~3 V). By introducing the RPN, the breakdown voltage

Temperature dependence under various HCD conditions was analyzed in 14 nm node FinFETs. Unlike oxide traps, interface traps show different temperature dependence depending on HCD voltage conditions. Therefore, the interface traps were separated into three components and the temperature dependence was analyzed for each component. Multiple particle process (MP) and Field enhanced thermal degradation

The motion blur of a large-size, organic, light-emitting device (OLED) panel could be reduced by decreasing the moving-picture response time (MPRT). The MPRT of an OLED display panel with a fast response was significantly affected by the frame frequency and the compensation driving method, and the MPRTs of large-size OLED display panels could be significantly decreased by using an integrated gate driver

This brief presents a study on the effect of substrate choice on the performance of lateral GaN transistors. This is accomplished using a previously calibrated TCAD model of the device which was used to investigate the effect of substrate choice on capacitance-voltage characteristics of the device. It is shown in simulation that ${C} _{\mathrm{ GD}}$ and ${C} _{\mathrm{ DS}}$ have a demonstrable dependence

In this paper, an N-type silicon line tunneling TFET (LT-TFET) with an ultra-shallow N + pocket was proposed. The pocket was formed by using the germanium preamorphization implantation (Ge PAI), arsenic ultra-low energy implantation and spike annealing. Due to the Ge PAI, the tunneling probability was improved significantly. As a result, a high on-state current of $40 \mu \text{A}/\mu \text{m}$ , a

We have examined impacts of gate insulator (Al 2 O 3 or HfO 2 ) and gate electrode (TiN or W) on electrical performance of ZnSnO/Si bilayer tunneling fieldeffect transistors (TFETs). It is found from the capacitance-voltage ( ${C}$ - ${V}$ ) characteristics that the W gate is effective to reduce the counter-clockwise hysteresis. Additionally, the optimal temperature of post-metallization annealing

This paper reports a novel HEMT structure that includes a built-in light emitter through band-to-band radiative recombination that is provided via holes from the p-GaN layer and electrons from the 2DEG. The electrical switching and illumination functions are able to be combined into a single device. The peak of the emitted light spectrum is located at 365 nm, corresponding to the bandgap of the GaN