Void inspection is crucial for insulated gate bipolar transistors. X-ray computed laminography (CL) is an imaging method for plate-like objects such as insulated gate bipolar transistors. Hence, voids in CL images should be identified automatically and accurately. This paper proposes a fully automatic method of void inspection in the welding layer between a direct-bonded ceramic and a baseplate. No-reference

Solder voids has an important impact on healthy operation of insulated-gate bipolar transistor (IGBT) modules, but voids damage is difficult to be estimated accurately by conventional methods due to the lack of calculation in mutual thermal effect between chips. So this paper proposes a base solder voids identification method by using case temperature, takes into account both self-thermal diffusion

The thickness increase of gallium nitride (GaN) cap layer from 2 nm to 35 nm to achieve an enhancement mode GaN MIS-HEMT (Metal-Insulator-Semiconductor High-Electron-Mobility Transistor) with a threshold voltage (Vth) of +0.5 V is studied using TCAD simulations. The simulations are calibrated to measured I-V characteristics of the 1 μm gate length GaN MIS-HEMT with the 2 nm thick GaN cap. A good agreement

This paper presents a comprehensive finite element analysis study on the effect of the support and fixation schemes on the dynamic characteristics and fatigue life of electronic assemblies under vibration. In this study, high accuracy finite element (FE) model was created and thoroughly validated with modal analysis experiments in terms of natural frequencies and mode shape. Accordingly, the finite

Deep learning tasks cover a broad range of domains and an even more extensive range of applications, from entertainment to extremely safety-critical fields. Thus, Deep Neural Network (DNN) algorithms are implemented on different systems, from small embedded devices to data centers. DNN accelerators have proven to be a key to efficiency, as they are even more efficient than CPUs. Therefore, they have

With the introduction of the ISO26262 standard in the automotive field, numerous solutions for the in-field and on-line testing have been proposed. Among the several test solutions available, the Built-In Self-Test (BIST) approach is the most used for manufacturing test of chips, while the Software-Based Self-Test (SBST) approach is the most commonly used for on-line test the modern processors. This

Electrical connectors can get static charges during handling and discharge on a printed circuit board when assembled. The rise time and shape of the discharge current waveform is studied with simulation and measurement methods. Results show that the ESD current rise time can be less than 10 ps.

Dynamic avalanche effect can occur due to the influence of free carrier on electric filed during inductive turn-off of IGBT, which is a critical factor influencing the device reliability. In this paper, a one-dimensional (1-D) analytical model for dynamic avalanche onset is at first derived based on the basic principles of semiconductor and it gives insight into the details of internal physical mechanisms

Temperature variation on board can have a significant impact on electronic circuit parameters. In this paper, we investigate and model how both irradiated NPN and PNP-Bipolar Junction Transistors (BJTs) at room temperature respond electrically to temperature variation. A temperature-dependent analytical model for total-ionizing-dose-induced excess base current in BJTs is proposed. Our model captures

As Cu is appearing to be a promising alternative for Au in wire bonding applications the corrosion behavior of the Cu/Al intermetallic compounds (IMCs) is becoming a concern. In this study, the corrosion behavior of Cu/Al IMC layers in NaCl solution is investigated. Among Cu9Al4, CuAl and CuAl2 IMCs only CuAl IMC appears to be corroded. The surface potential difference between Cu, Al, and Cu/Al IMCs

Product lifetime is one of the most important issues associated with circular and sharing economies. In the face of global warming, increasing product quality and product lifetime can enhance product value and industry competitiveness. Many electronic products use designs with spare electronic components to enhance their reliability. To prevent the loss of generality, we assumed that an electronic

In this paper, we identified the defect state of p-channel low temperature poly-Si thin film transistors (LTPS TFTs) fabricated on a polyimide (PI) substrate that is distributed differently in the interface and channel areas depending on the activation annealing temperature, as well as observed the effect on the threshold voltage (VT) and reliability. To verify the effect of the process temperature

This work analytically models the crucial physical mechanisms accountable for the defect kinetics and the degradation of base current in PNP BJTs. Both the space charge and bimolecular mechanisms have been incorporated to elicit the defect dynamics (oxide charge and interface trap) following ionization radiation. Thereafter, two novel insights into the ionization damage on SiO2 of bipolar structure

A carbon nanotube (CNT) has remarkable properties, but it has disadvantages in application because of its dispersal- and bonding-related issues. Metal–CNT composite materials are necessary in solving these problems. In this study, nickel (Ni)–multi-walled CNTs (Ni–MWCNTs) are synthesized through sequential processing, functionalizing, and electroless plating processes to deposit Ni nanoparticles on

The effect of Al2O3 nanoparticles addition on melting, microhardness, microstructural, and mechanical properties of multicomponent Sn-3Ag-0.5Cu-0.06Ni-0.01Ge (SACNiGe) solder alloy was investigated. The shear strength of the capacitor assemblies under varying high-temperature environments for different nanocomposites was assessed and the reliability of the joint was determined using Weibull analysis

The reverse recovery (RR) behavior of SiC MOSFET body diode is of great importance in power application, where these devices are used in a wide range of operating temperatures. The carrier lifetime in the drift region varies with temperature, and it heavily affects the tailoring of the RR current, opening reliability issues related to the RR voltage amplitude and to possible anomalous voltage oscillations

The investigation of a prospective lead-free solder alloy provides the essential data for microelectronic applications and estimation of solder joint reliability. In this study, we used the rotary magnetic field (RMF) as a novel approach to improve the mechanical performance and microstructure of Sn-2.0Ag-0.5Cu-2.0Zn (SACZ) lead-free solder alloy. The results revealed that both microstructure evolution

This work presents a new decoding algorithm that extends the error-correction capacity of group testing based (GTB) non-binary error correction codes without modifying the number of parity symbols of the codeword. A list decoding algorithm based on the pattern of the syndromes takes advantage of the parity matrix equation exploiting its structure. The decoding algorithm can be reformulated by detecting

This paper studied the effect of total ionizing dose (TID) radiation on 10 V high-voltage n-type metal-oxide-semiconductor (HVNMOS) devices. The study was conducted on two devices with P+ ion-implantation for radiation-hardening. Both devices were geared towards embedded applications, and ions were implanted into them through P+ ring and P+ sub implantation methods, separately. Leakage channels induced

Large target is essential for the fabrication of semiconductor devices, and the reliability of sputtering target backplate assembly plays a key role on the quality of sputtered films in the devices. In this work, the interface of an 8-inch Co target soldered on Cu backplate by In alloy is studied and characterized systematically. At the Cu backplate side, there are many void defects, and only one kind

A Cu-cored solder ball (CCSB) is often used as the interconnection material for 3D package. The CCSB has a Cu core surrounded by Sn-Ag-Cu alloy. The effect of the Cu core on mechanical reliability of the CCSB was investigated using thermal shock test. Microstructure and thermal shock reliability of the CCSB with organic solderability preservative (OSP) surface finish was compared with that of Sn-3

Chip–package interaction (CPI) has become an increasingly important reliability issue in the microelectronics industry. In order to survive the thermally induced stresses during processing or working lifetime, the complex back-end-of-line (BEOL) layer stacks must have sufficient mechanical strength. The understanding of accelerated mechanical tests performed at wafer level, such as shear microprobing

This paper describes a comprehensive analysis of the degradation mechanisms of green InGaN based high-power LEDs. The combination of electrical, optical and thermal measurement allows a separation of the degradation mechanisms and their influence on the performance of the devices. The results show that the LEDs have parasitic diodes in their initial state, which influence increases over the aging period

This paper reviews the feasibility of the state-of-the-art electrical techniques adopted from Si technology for characterization of SiC MOS devices. The inability of these conventional characterization techniques to correctly evaluate the trap capture cross section and field-effect mobility in SiC MOS devices are investigated and explained. As near-interface traps (NITs) are an important cause of field-effect

We investigate the effect of TID electron irradiation on a 65 GHz LNA in 130 nm SiGe BiCMOS. The LNA is exposed to a Sr-90 radiation source and irradiated at a rate of 200 krad (Si)/hr to a total dose of 15 Mrad (Si), with S-parameter and NF measurements taken at regular intervals. It is found that TID produces and increase in the input impedance, especially in the reactive component. The damage results

A novel space vector modulation (SVM) strategy called maximum-boost discontinuous SVM (MBDSV) is proposed in this paper to reduce the thermal stress of three phase impedance source inverters (ISI). By exploiting the switch clamping mechanism and arranging the shoot-through (ST) states properly, the proposed strategy obtains the flowing merits: further optimize the thermal performance, improve the reliability

Moisture induced failure is one of the major reliability concerns in electronic packaging. This research provides a comprehensive solution for modeling the moisture induced delamination in electronic packaging during solder reflow. Existing finite element approaches of studying the moisture and vapor pressure induced package delamination issue were discussed, reviewed, summarized and integrated into

The Dual-Core Lockstep configuration is largely employed in safety-critical System-on-Chips for the sake of compliance with functional safety standards. Such configuration includes two processor cores paired together, always fed with the same identical inputs and their outputs are continuously compared by a set of comparators. However, permanent faults affecting the comparators may invalidate the system

Considering shock loading on the MEMS microphone is necessary for its reliability assessment since drop of portable devices is a common situation. In this study, the stress distribution and the failures of MEMS capacitive microphone chip by TSMC 0.18 μm CMOS process, with 4 by 3 microphone array under shock loading (peak acceleration 1500 g) and shock plus static electricity loading were investigated

This study investigates a time-reduced sintering process for die attachment, prepared, within a processing time of several seconds using dry nanosilver film. The effects of three main sintering parameters, sintering temperature (220 to 300 °C), sintering time (1 to 9 s) and bonding pressure (6 to 25 MPa) on the resultant shear strength are investigated using uniform design and single factor experimental

As the chip power densities increase radically with scaling, thermal gradients are predicted to become a major reliability concern in interconnects compatible with the 3 nm technology node and beyond. In this study, the impact of temperature gradients on the reliability of Cu nano-interconnects with highly scaled linewidth of 10 nm is simulated using a Korhonen-type modelling framework previously calibrated

A dedicated experimental setup is presented for the acquisition of single ionization events generated in power devices by ionizing radiation. This spectrometer chain is designed to be used for long-term experiments, where devices are submitted to the natural terrestrial cosmic radiation (TCR), for TCR characterizations, as well as in conjunction with radioactive sources. Every single ionization event

In nMOS transistors the impact of positive bias temperature instability (PBTI) on the device performance is typically considered negligible and has thus been barely studied in the past. However, an accurate description of this phenomena requires and in depth understanding of the physical origin being responsible for the change of the device characteristics over time. For the assessment of PBTI in nanoscale

A DDR3 SDRAM test setup implemented on the Griffin III test system from HILEVEL Technologies is used to analyse the row hammer bug. Row hammer pattern experiments are compared to standard retention tests for different manufacturing technologies. The row hammer effect is depending on the number of stress activation cycles. The analysis is extended to an avoidance scheme with refreshes similar to the

Under unclamped inductive switching (UIS) condition, the distribution of avalanche breakdown current in insulated gate bipolar transistor (IGBT) is non-uniform. Many previous studies have shown the results of calculating current distribution and behavior using a device simulator. As a result of experimental observation, there are some reports that the temperature change of the device was observed by

The successive oxide failure statistics theory that arises from the clustering model is used for investigating the time-to-breakdown distributions of Al2O3/HfO2-based nanolaminates. These gate dielectrics in metal-insulator-semiconductor structures are intended to combine a high injection barrier material (Al2O3) with a high-K material (HfO2). When a constant voltage is applied to the structures, the

In this paper, an experimental and numerical study of the electrical ruggedness in double-sided cooled power modules is presented. In particular, the analysis focuses on the role of the spacing between substrates, which are commonly kept distant to avoid electrical failures like partial discharge and dielectric breakdown. To this aim, many double-sided cooled assemblies were manufactured and then tested

PV (Photovoltaic) power systems have been rapidly installed and spreading worldwide in recent years. And there is a belief that the PV power plant will operate stably for more than 25 years. However, the PV modules have an unexpected failure. In this paper, we diagnosed a 10-year-old power plant using drone with infra-red (IR) camera, current-voltage (I-V) and electroluminescence (EL) measurement.

In this work a new concept of liquid cold plate for high power press-pack assemblies is investigated. In industrial applications it is very important to reduce the volume and weight of the device-heatsink stack, in order to improve reliability and availability of the whole system. The potential of aluminum additive manufacturing technology is investigated by means of coupled thermal fluid-dynamic 3D

Due to the increasing demand for high performance in embedded systems, devices such as SRAM-based programmable devices are becoming an appealing solution to reach high performance with limited costs. However, SRAM-based programmable devices are subjected to various sources of radiation-induced faults that affect their reliability, such as ionizing radiation and particles, even at sea-level. In this

UMOSFET on-resistances have been dramatically improved in recent decades with the miniaturization of cell size by innovations in the fabrication process. However, with miniaturization, failure in the gate oxide, large deviations in the threshold voltage and reductions in avalanche capability have emerged as design problems for mass production. In particular, threshold voltage increase have appeared

Scratchpad memories (SPMs) are intensively utilized in modern embedded processors where a demand on improving reliability without compromising performance-predictability and area/power efficiency is on rise. Our observations imply that one target for this reliability improvement is to combat ever increasing threats of multiple bit upsets (MBUs) occurring in the SPM addresses as well as multiple event

This paper proposes a study on the resilience to radiation of MEMS sensors based on piezoresistive transduction by means of suspended silicon nanogauges. It is particularly interesting for applications in severe environment like in space or in nuclear plant. This work shows that the resistivity of a single nanogauge exhibits a sensitivity of 16.5 ppm/kGy whereas the silicon nanogauges bridge used for

This work presents an in depth investigation regarding the effect of PECVD silicon nitride (SiNx) stoichiometry on its charging mechanisms. The investigation took place in SiNx dielectric films with different Si-content (x = 0.47–1.04) with the aid of Metal-Insulator-Metal capacitors. The experimental assessment involved a single-point Kelvin probe System, the monitoring of Current – Voltage characteristics

Multilayer polymer aluminum electrolytic capacitors represent one of the most recently developed capacitor technology; this paper presents a reliability analysis of multilayer polymer capacitors in elevated-temperature and humidity applications (85 °C). Three groups of capacitors were selected and tested at two different environmental conditions (85 °C/85% RH and 110 °C/85% RH with rated voltage bias)

Spin-transfer torque (STT)-magnetic random access memory (MRAM) requires yield-aware design for hybrid magnetic-CMOS integration. In this paper, a novel cycle-sensing margin enhancement (CSME) scheme with pMOS assisted voltage-type sense amplifier (p-VSA) is proposed to alleviate imperfect process induced performance fluctuations. With iterated charging-discharging through non-volatile data path and

Reliability testing of Si power semiconductors has had a long history and has resulted in a good predictability of standard degradation-mechanism tests such as power cycling. To enable a rapid adoption of SiC MOSFETs into the mass market, application stress tests have also been carried out. In order to validate robustness, and assess end-of-life behavior, it is necessary to monitor performance-relevant

Aiming at the inaccurate problems of lifetime prediction and reliability evaluation of 3D Trinary-Level Cell (TLC) NAND flash memory, a method to evaluate the remaining lifetime and the reliability of flash memory based on the threshold voltage distribution is proposed. In order to analyze the impact on Program/Erase (P/E) cycles on the flash memory from the perspective of voltage distribution, a complete

The complete percentile lifetime models are essentially required for a mission profile based reliability evaluation of power modules. However, the information on the complete lifetime models or lifetime data of power modules is rarely fully provided by manufacturers. The Monte Carlo method is a good solution to obtain the time-dependent reliability function when only limited lifetime information such

Connected mobile applications, known as the Internet of Things (IoT), require deploying extensive efforts to optimize power consumption and to improve the system performance at the same time. One way to reach this goal is based on sacrificing the computing precision by adopting different approximate computing methodologies for boosting system performance and reducing the power consumption. In this

This paper proposes a system-level prognostic approach for power electronic systems with slow degradation profiles. Although a model-based approach has been adopted to deal with such multivariable dynamical systems with degradation properties, the forecasting of the Remaining Useful Life (RUL) is independent of prior knowledge of degradation profiles. Thus, this proposition is mainly based on the estimation

A vast range of electronics products have utilized 2.5D packages for better performance and miniaturization. As multi-level assembly technologies are getting mature, 2.5D packaging technology becomes affordable. In this work, design guideline for board-level reliability of a 2.5D package was provided with respect to accelerated thermal cycling (ATC) and power cycling (PC). Finite element models were

Microelectronic packages continue to become smaller and more complex. Interfacial delamination is a common failure mechanism present in microelectronic packages due to the mismatch in the coefficient of thermal expansion (CTE) between different materials. Epoxy Molding Compound (EMC)/copper is a common interface found in microelectronic packages and is susceptible to delamination due to CTE mismatch

Recent developments in high-tech industries have led to integrated circuits that are used increasingly in most of the critical applications such as medical supervisory systems and space applications. These systems are facing two major challenges, namely reliability and timing requirements. In other words, these systems have to operate correctly while meeting timing requirements even in the presence