In this paper, the impact of the traditional interdigital DDSCR structure (TI-DDSCR) and the embedded DDSCR (EM-DDSCR) structure with and without P+ guard-ring is analyzed under the 0.5-μm complementary and double-diffused MOSFET (CDMOS) technology. In order to verify and predict the characteristics of those electrostatic discharge (ESD) protection devices, a transmission line pulse (TLP) testing system

A novel analysis routine is proposed that visualizes the opening of a transistor channel using Electron Beam Induced Current (EBIC) with a net zero-volt bias across a channel. nFET devices on a 7 nm technology node chip were examined in two different regions of the sample. With varying gate voltage, the device turn-on was clearly evident in the resulting EBIC image. Quantitative analysis of the resulting

This paper investigates the mechanisms that limit the efficiency and the reliability of InGaN-based LEDs, by presenting an analysis carried out on devices having two quantum wells that emit at different wavelengths (405 nm and 495 nm). A color-coded test structure was designed in order to easily quantify the optical characteristics of both quantum wells, and to describe in detail the stress dynamics

Wide-bandgap (WBG) based cascode devices combine the advantages of the gate driveability and reliability of silicon MOSFETs with the power conversion efficiency and switching rate of wide bandgap devices. A low voltage (rated at ~20–30 V) silicon MOSFET drives a vertical JFET for the SiC cascode whereas for the GaN cascode, it drives a lateral GaN HEMT. This paper presents the first systematic comparison

Microelectromechanical systems (MEMS) switches are attractive for many applications including radio frequency and microwave systems, logic devices, acceleration sensing and electric protection. However, low reliability limits the introduction of these devices into the commercial use. For two decades of research, many reliability issues have been successfully overcome, but some aspects have received

Under unclamped inductive switching (UIS) condition, there is non-uniformity in the intra-chip distribution of avalanche breakdown current in insulated gate bipolar transistors (IGBTs). The “current filaments”, which are concentrations of current caused by the parasitic PNP transistor, move through the chip and are thought to be related to failures. During the avalanche breakdown, the charge bremsstrahlung

In this paper, a new Radiation Hardened By Design (RHBD) 8T SRAM cell is proposed that can tolerate single-event upset (SEU) in a radiation environment. According to the simulation results for 130 nm silicon-on-insulator (SOI) technology, the critical charge of the proposed 8T cell increases by 82.9% compared to the conventional 6T SRAM cell and by 62.5% compared to the other RHBD SRAM cell, the S

In recent years, power electronics has played a fundamental role in the development of increasingly efficient circuits for energy conversion. The characterization of a Power MOSFET under a gate overstress and the correlation with the reliability performances represent a crucial point in the optimization of the trench technology where the oxidation processes of the gate oxide are critical in terms of

By an effective energy model in the device under laser single event effects (SEE) test, a two-photon absorption (TPA) of pulsed laser energy transmission mechanism model vs heavy ion linear energy transfer (LET) for SEE have been established. Based on 4H Silicon Carbide (4H-SiC) diodes material parameters which should be considered for SEE) irradiated by TPA of pulsed laser, model for TPA of pulsed

This paper presents the numerical evaluation of different multiphotonic absorption mechanisms to be used for backside laser testing of single-event effects in GaN-on-Si HEMTs. The optical transmission through the complete stack of layers of three commercial references is calculated. Experimental results illustrating the possibility to use three-photon absorption for charge injection in the GaN layer

In this work, reliability of boron-doped graphene field effect transistor (GFET) is examined by modeling the effect of doping in terms of linearity performance metrics. The key potential (VN) induced in B doped GFET is analytically modeled for various B doping concentrations. An accurate compact equivalent circuit model integrated with VN for B doped GFET is proposed to investigate the effects of memoryless

Large array devices are often used for big current driving capabilities in power electronic integrated circuit (IC) applications. Since these structures have big sizes, typical electrostatic discharge protection methodologies cannot be applied in such kind of IC. Otherwise, IC will become too huge to marketing. In this paper, a novel signal control switching architecture for adding large array devices'

Sub-10 MeV proton-induced single-event transients (SETs) were firstly reported in this work. Sub-10 MeV proton experiment demonstrates that sub-10 MeV proton-induced SET pulse can be wider than 200 ps and the average SET pulse-width increases with proton energy. The analysis indicates that the observed SETs are attributed to recoil ions and SETs induced by oxygen recoils can be much wider than those

The space environment's hostility requires that the processors used in spacecraft be designed using fault tolerance techniques to reduce the propagation of errors. In this context, this work presents a low-cost fault-tolerant processor based on the RISC-V architecture, an emerging industry standard for building embedded processors. The implemented processor was integrated with a System-on-Chip to assess

With the advance of autonomous systems, security is becoming the most crucial feature in different domains, highlighting the need for protection against potential attacks. Mitigation of these types of attacks can be achieved using embedded cryptography algorithms, which differ in performance, area, and reliability. This paper compares hardware implementations of the eXtended Tiny Encryption Algorithm

The paper presents the results of irradiation of the triple junction solar cell (SC) based on perspective InGaP/InGaAs/Ge semiconductor structure with Ge-substrate by electrons, neutrons and gamma-rays. The electrical and spectral characteristics of the SC were investigated before and after each stage of irradiation. Results show that degradation curves obtained with different types of radiation sources

With the shrinking device geometries, the extremely high electric field in the drain-channel region makes nano-devices more susceptible to Hot Carrier induced Degradation (HCD) effects. This paper develops an HCD degradation model of gate underlap Double Gate (DG) and Gate All Around (GAA) MOSFET due to hot carrier induced interface trap charges (ITCs). The parabolic approximation and conformal mapping

Temperature-dependent electrical characteristics were explicitly investigated for a 400-μm diameter neutron-irradiated (NI) GaN Schottky barrier diode (SBD). Based on C-V measurements, a marked decrease in electron concentration has been revealed for the NI diode compared with the pristine sample, suggesting a thermal-enhanced carrier removal effect. Neutron irradiation causes noticeable Schottky barrier

Hydrothermal growth method was used to grow the zinc oxide (ZnO) thick films on ZnO seed layer previously deposited by RF magnetron sputtering technique. The effect of introducing of zinc acetate and chloride salts on the structure, chemical and physical properties of the obtained films was investigated. Scanning electron microscope (SEM) and atomic force microcopy (AFM) were utilized to both justify

In view of the structural warpage deformation and stress-strain problems of 2.5D and 3D package structures under the temperature cycling environment, the causes of structural warpage deformation and the difference of stress and strain between the two structures are analyzed by combining the results of finite element simulations. The most critical solder joints life of the two structures are calculated

Eletrothermal microgrippers are nowadays commonly used as they are small in size, low cost and easy to manufacture. Modeling of these microgrippers is challenging as most of the systems are described in partial differential equations. The microgripper is modeled through finite element method, producing a large number of ordinary differential equations, thus making model order reduction a fruitful proposition

Analyzing transient ESD device behavior with TLP equipment requires more attention for implementation and measurement details than the classical quasi-static TLP approach. Minimizing hardware parasitics reduces the de-embedding effort and optimizes the quality of the voltage and current measurements. We explore different methods and hardware options and highlight potential pitfalls.

The main aim of the paper is to provide effective and accurate solutions for the calculation of the support region of the μ-law logarithmic companding quantizers. A new solution for the starting point of iterative methods will be proposed, that provides very accurate value of the support region (being the main parameter needed for the design of the quantizer) only after one iteration of the iterative

In recent years, there has been considerable interest on the part of scientist and engineers in effectively designing accelerated degradation test, which is very useful to assess product's life information with long-life and high-reliability properties. An effective optimal ADT design method can provide a reasonable arrangement of accelerated stress level setting, sample allocation and test time. However

The advancement of Integrated Circuit (IC) technology has encouraged the IC industries to go fabless and outsource the fabrication to other companies, due to the cost associated with installing a new facility and design to production time limitations. It has also introduced an adverse effect on hardware security, known as Hardware Trojan (HT), which is very difficult to detect due to low signal-to-noise

Avalanche robustness in dynamic operation is one of the main obstacles to further promote the commercialization of SiC MOSFETs. In this paper, a cell-level optimization design is proposed to suppress the avalanche failure caused by parasitic BJT activation. Several retrograde doping profiles with different thickness of lightly doping region (TLD) are designed for P-well, which is the key area affecting

This paper analyzes the mechanism by which Single-Event-Upsets (SEUs) and Single-Event-transients (SETs) impact on the working condition of the charge-pump-phase-locked-loop (CPPLL) and relevant hardened techniques, and also presents a soft-error-tolerant CPPLL in 40 nm CMOS process. It employs dual-mode interlocking (DMI) and divider-resistance techniques to reduce the soft-error rate caused by natural

Deep Neural Networks (DNNs) have been successfully deployed in safety-critical applications due to the capability of computing in complex tasks. Because of low energy, ARM (Advanced RISC Machine) processors are used for DNNs in embedded applications. However, in harsh environments, soft errors induced by radiation strikes may cause Silent Data Corruptions (SDCs) and Detected Unrecoverable Errors (DUEs)

Proton-induced degradation and catastrophic failures in 650 V SiC diode and 900 V SiC MOSFET under different bias voltage and different proton energy are investigated. The experimental results show that when the bias voltage of SiC diode and MOSFET reaches 88% of rated voltage, 20 MeV protons will not cause the single event burnout (SEB) of two SiC devices. When SiC devices are burned out, a wave-shaped

All-Programmable System-on-Chips (APSoCs) constitute a compelling option for employing applications in radiation environments thanks to their high-performance computing and power efficiency merits. Despite these advantages, APSoCs are sensitive to radiation like any other electronic device. Processors embedded in APSoCs, therefore, have to be adequately hardened against ionizing-radiation to make them

Thick epitaxial GaN power switching devices are known to contain a high density of crystal defects, especially threading dislocations in the epitaxial layer. The impact of these defects on device performance is a topic of ongoing research. This paper presents a review on the current understanding of the impact of dislocations on leakage current, blocking voltage, peak electric field, switching frequency

Physical attacks, namely invasive, observation, and combined, represent a great challenge for today's digital design. Successful class of strategies adopted by industry, allowing hiding data dependency of the side channel emissions in CMOS is based on balancing. Although attacks on CMOS dynamic power represent a class of state-of-the-art attacks, vulnerabilities exploiting data dependency in CMOS static

In Deep Sub Micron (DSM) technology, the critical issues in the NoC interconnect design are to meet the performance, power consumption requirements of the SoC and to address reliability simultaneously, interconnect delay, power consumption and crosstalk noise. It is essential to select an optimal coding technique to improve communication reliability and reduce self and coupling switching activities

Cracking of sintered silver layer always leads to the reliability issues in power devices. In this paper, the cracking behaviors of sintered silver layer have been investigated through numerical analysis with fracture based method. Energy release rate of various interfacial cracks and vertical cracks in sintered silver are computed. It is found that the energy release rate of interfacial crack and

In order to obtain junction temperature of insulated-gate bipolar transistor (IGBT) on electric vehicle, a number of studies have proposed junction temperature (Tj) estimation methods. However, some of these methods require additional circuits which lead to cost increase, some methods simulate the IGBT thermal process with thermal model, which induces a deviation between real functional results and

Among the most important components in complex and high-power mechatronic systems is the transistor. The High Electron Mobility Transistor (HEMT) is a technology under development. This paper presents the hybrid Reliability Based Design Optimization (RBDO) method applied to the HEMT technology in order to improve its performance and reliability. The execution of RBDO processes requires the development

A three-phase half-bridge insulated gate bipolar transistor (IGBT) module is designed and prototyped as the assembly of heat sink-substrate-post-chip-substrate-heat sink to realize high power density and good thermal performance for electric and hybrid electric vehicle applications. This paper reports the failure modes different from those fatigue of the chip-near interconnections in the conventional

Radio frequency identification (RFID) is widespread and still necessary in many important applications. However, and in various significant cases, the use of this technology faces multiple security issues that must be addressed. This is mainly related to the use of RFID tags (transponders) which are electronic components communicating wirelessly, and hence they are vulnerable to multiple attacks through

Many challenges accompany the use of three-dimensional (3D) integrated circuits (ICs). Some of these challenges are design-related, while others are verification-related. In this paper, we focus on verification issues; more precisely, on advanced layout physical verification tasks, such as advanced latch-up design rule checks and candidate hot junction detection. We explain the differences and additional

Stress test system development is increasingly aimed at meticulous reliability and robustness evaluation for power semiconductors under application conditions as well as qualification purposes. Newly developed silicon (Si) power devices need further investigation in terms of potential new failure mechanisms. A double pulse tester is utilized as a test vehicle for studying hard switching related failure

The insulated-gate bipolar transistor (IGBT) is one of the most widely used power transistors in switching and industrial control systems. Its actual junction temperature plays a critical factor in determining the dynamic performance, reliability and life-time of the device. Although some noninvasive measurement methods such as optical and physical contact methods may be used to estimate the junction

Modern CMOS technologies such as FDSOI are affected by severe aging effects that do not only depend on physical issues related to nanoscale technologies, but also on the circuit environment and its run-time activity. Therefore it is extremely difficult to reliably establish a-priori guard bands for Critical Path estimations, usually leading to both large delay penalties (and therefore loss of performances)

In this study, Al-50 ppm Ni (AN0005) was fabricated into 15, 12, and 4 mil (375, 300, and 100 μm, respectively) wires through the wire drawing process. The thick 12 and 15 mil wires exhibited an isometric crystal structure. A large plastic deformation of the thin 4 mil wire resulted in obvious grain refinement. Thin 4 mil AN0005 wires exhibited the best mechanical performance. In the fusing test, the

Scan based DfT is indispensable for IC testing in the semiconductor chip industry to ensure correctness of chip, both functionally and structurally. Since a higher degree of fault coverage is essential, cryptographic ICs rely on it as a standard technique during manufacturing test. Yet an invaluable tradeoff needs to be met between security and testability, because it is the observability and controllability

In-memory-computing (IMC) architecture has been proposed as an alternative to cope with the memory wall of von-Neumann computing architecture. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. An IMC memory can be operated in memory mode and computing mode, which increases the test complexity. Thus, the IMC memory need to be tested

Silver microparticles (Ag MPs) are widely used in conductive pastes for printed flexible electronics because of their easier synthesis and lower cost than silver nanoparticles. However, the cyclic bending reliability of the printed conductive patterns containing Ag MPs needs to be improved to use the devices under bending conditions. In this work, the conductive paste was prepared by mixing two silver

Solder connections provide an electrical and mechanical connection between components and PCB (Printed Circuit Board) in electronic devices. It is very important to develop a reliable method to detect the cracks in the quality control field of solder joints. When a crack is generated in the solder joint, parts of the solder are replaced by air gaps, leading to an increase of the thermal resistance

Silicon carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) are susceptible to unexpected short-circuit (SC) impacts in high-voltage inverters operating in complex applications. This paper presents a research on the effect of high-side blocking and classical low-side blocking on short circuit characteristics. Simulation of the steady-state electric field, which equivalent to

We find in experiments a linear dependence of ionization irradiation-induced degradations on pre-irradiation values of the input bias current in bipolar devices with simple input stages. The dependence is found to generally exist in all studied cases of different device types and different irradiation conditions. A unique behavior of the energy distribution of the interface states (Dit) under irradiation

A superior figure-of-merit (FoM) 1200 V class 4H-SiC trench MOSFET with p + shielding region partially surrounded by the buried n region is proposed in this paper. The buried n region is introduced to restrain the lateral extension of the depletion layer formed by p + shielding region at the quasi-saturation (QS) state, which leads to a significant improvement of the transfer and forward characteristics

The Internet of Things (IoT) as an emerging infrastructure has an essential rule in daily lives in many domains, ranging from healthcare wearable devices to complex industrial systems. Nevertheless, its security is a challenging issue that has to be addressed. The security can be settled by utilizing cryptographic techniques such as Advanced Encryption Standard (AES) for encryption and authentication

Microprocessors are widely used in space applications. ARM processors fabricated with FDSOI technologies are promising for future space programs. However, radiation-hardening approaches can greatly affect the resource overhead and performance. These hardening techniques need to be evaluated at system level to better understand their effectiveness, especially for modern CMOS technologies. In this paper

Short-term reliability and robustness of 110 nm AlN/GaN HEMTs has been evaluated by means of off-state, semi-on state and on-state step stress tests on devices having different gate-drain distance, LGD. While breakdown voltages and critical voltages scale almost linearly with LGD, failure mode remains almost unchanged in all tested devices, and consists in an increase of gate leakage, accompanied by

Power electronics reliability in a high humidity environment has recently been considered an important aspect of power converters. In this article boost stage power semiconductor modules from two vendors with varying device technologies were exposed to high humidity, high temperature and high voltage reverse bias direct current (H3TRB-HVDC) test conditions. The exposed modules were monitored with in

Present-day IoT systems that capture, process, and transfer real-world data, employ lightweight ciphers in sensor devices for applications with multiple limitations, such as restricted size, power consumption, and processing speed. The largest security threat that such devices incur comprises implementation-based attacks, such as fault attacks, power analysis attacks, etc. Therefore, it is imperative

Electromigration continues to be a major concern for integrated circuit design. The susceptibility to electromigration is assessed by tracking the stress in metal lines under the influence of applied currents, which can be computationally expensive for large chips. Over the last few years, an efficient approach for tracking stress in large interconnect networks has been developed, and well-received

In three-dimensional integration, atomic migration is a critical challenge for through‑silicon-via (TSV) reliability, especially under high electric current and thermal stress. Meanwhile, Bosch scallops, as the byproduct of Bosch process, can cause stress concentration around them, which further undermines TSV reliability. In this paper, the migration behavior of copper TSVs with Bosch scallops is