In three-dimensional integration, atomic migration is a critical challenge for through‑silicon-via (TSV) reliability, especially under high electric current and thermal stress. Meanwhile, Bosch scallops, as the byproduct of Bosch process, can cause stress concentration around them, which further undermines TSV reliability. In this paper, the migration behavior of copper TSVs with Bosch scallops is

As the demand for flexible hybrid electronics has increased extensively e.g. for the internet of things (IoT), electronic skin and wearables applications, the implementation of devices based on low-cost materials such as PET, paper, and unpackaged bare dies have become crucial for economical mass production. To facilitate flexibility for instance in wearables, the rigid silicon-based components are

We propose a complete Artificial Intelligence (AI)/Deep Learning (DL)-based image analysis framework for hardware assurance of digital integrated circuits (ICs). Our aim is to examine and verify various hardware information by analyzing the Scanning Electron Microscope (SEM) images of an IC. In our proposed framework, we make use of DL-based methods at all essential steps of the analysis. To the best

One of the common reliability concern on most of power modules is a failure of its bonding. Stress, strain, and displacement fields around those bonding in power modules are required for highly-reliable design based on physically/mechanically based failure model. They can be accurately obtained from CAE tools such as finite element computer codes for stress analysis with mechanical properties of materials

Lateral parasitic PNP transistor inside P+/N-well diode is explored and investigated for the electrostatic discharge (ESD) protections in I/O interface integrated circuits (ICs). An analysis for the breakdown behavior of the lateral parasitic PNP transistor with base floating is presented for the first time. Simulations on the lateral parasitic PNP transistor have been performed to understand the effects

Contemporary embedded systems work in changing environments, some features (e.g., execution time, power consumption) of the system are often not completely predictable. Therefore, for systems with strong constraints, a worst-case design is applied. We observed that by enabling the self-adaptivity we may obtain highly optimized systems still guaranteeing the high quality of service. This paper presents

The use of reflow flux system for soldering process of SMT electronics results in the concealed residues located underneath of the components, which changes its characteristics upon exposure to humidity. In this paper, the transformation of reflow process-related solder flux residues was investigated under varied humidity and temperature conditions. Evolution of potentially corrosive active components

Due to its attractive characters, nanosecond ranged access latency and higher bit density，phase change memory (PCM) has emerged as a promising main memory candidate for embedded systems in the future. However, relatively lower endurance has limited its practical application. Discussions regarding hybrid memory wear leveling algorithms have dominated research dereliction in recent years. However, most

The wafer map is obtained by testing each die in the wafer during semiconductor production for defects and marking the defective die. The classification of wafer maps can provide evidence for problems occurring in the production process, so as to solve the problems and reduce the costs. Before classifying the wafer map, the most important thing is feature extraction. In addition to a certain spatial

The prediction of high-resolution mechanical stress distributions in electronic chips with a view to improving prognostic and health management in electronics and N/MEMS via artificial intelligence-based processing of measurement data is the focus of this study. Temperature, shear, and differential stress time-series data acquired through piezo-resistive silicon-based stress sensors on multiple electronic

The response of a 20-nm fully depleted silicon on insulator (FDSOI) transistor under irradiation by heavy ions is analysed using GEometry ANd Tracking (Geant4) and Synopsys Sentaurus device simulations. Because of the huge energy fluctuations between thin silicon layers, the deposited energy calculated using surface linear energy transfer (LET) is imprecise under the incidence of heavy ions at very

Corrosion reliability is a severe concern related no-clean flux (NCF) residue. It results in a decreased life span of electronic devices, specially fine pitch assemblies. NCFs are formulated from various organic/inorganic components viz. activator, solvent, surfactant, and additive. Each constituent of a flux has specific functions, and its advantages and limitations. The first part of this review

Effects of oxidation and nitric oxide (NO) post-oxidation annealing (POA) processes on the gate oxide integrity on 4H-SiC are investigated. Interface state density, flatband voltage, electron tunneling barrier height, breakdown field, and time-dependent dielectric breakdown are extracted. With the same NO POA condition, more nitrogen atoms are incorporated into wet oxide than dry oxide. The interface

Digital microfluidic biochips (DMFBs) are increasingly important used for clinical diagnostics drug discovery and point-of-care. Those procedures require high output precision, so the reliability and lifetime of the chips are extremely important. Due to the inherently reconfigurable nature of DMFBs, a degraded electrode may be reused many times. Therefore, the lifetime of the chips is closely related

In every new technology, the understanding of its failure mechanism is essential to ensure reliability. In this paper an overview on some state-of-the-art characterization methods of 4H-SiC metal oxide semiconductor field effect transistors (MOSFETs) are presented. Silicon-based devices employ many different tools for the study of failure mechanism, which can be exploited for silicon carbide (SiC)

Reversible logic has recently gained a remarkable interest due to its information lossless property, which minimizes power dissipation in the circuit. Furthermore, with their natural reversibility, quantum computations can profit from the advances in reversible logic synthesis, as the latter can be easily applied to map practical logic designs to quantum architectures. Although numerous algorithms

This study presents a new modeling approach for moisture concentration in the presence of time dependent saturated moisture concentration and diffusivity by considering only native ANSYS elements. It removes the shortcomings of the ANSYS “diffusion” and “coupled field” elements by employing thermal (LINK33, PLANE55 and SOLID70) and spring (COMBIN14) elements. The accuracy of this modeling approach

The trend of electrification and miniaturization brings the reliability of interconnects to the forefront. The solder joints are subjected to thermo-mechanical mismatch due to the Joule heating and electromigration (EM)-induced degradation under high current stressing conditions. However, most of the studies are limited to lab test samples or lab test conditions, which lack transferability in engineering

The piezoresistive silicon based stress sensor has the potential to be part of the Digital Twin implementation in automotive electronics. One solution to enforce reliability in digital twins is the use of Machine Learning (ML). One or more physical parameters are being monitored, while other parameters are projected with surrogate models, just like virtual sensors. Piezo-resistive stress sensors are

In this work, the impact of interface trap charges (ITCs) on electrical characteristics of dielectric pocket SOI-TFET (DP SOI-TFET) proposed for the reduction of ambipolar conduction and improvement of high-frequency (HF) performances has been demonstrated in details. The reliability of DP SOI-TFET has been examined by analysing the impact of varying polarity and density of ITCs on dc and analog/HF

In this work, Fluoropolymer-based ultrathin coating is evaluated as a protective barrier for Printed Circuit Board (PCB) against corrosion failures. Constant humidity with temperature cycling was applied as external climatic conditions for performance assessment through electrochemical AC impedance and DC potentiostatic measurements. Morphology of the coating before and after test was inspected using

In this study, the dV/dt ruggedness of commercial 4H-SiC Schottky diodes C3D02060A (Wolfspeed) with DC blocking voltage of 600 V and continuous forward current of 2 A was investigated. The quasi-static reverse current-voltage characteristics of the diodes were measured in the recoverable avalanche breakdown regime up to currents of about 7 A. The mature avalanche breakdown voltage was measured to be

In this paper, the influence of ageing by PCT (Power Cycling Test) on the hard switching behavior of IGBT (Insulated Gate Bipolar Transistor) devices, especially the current change rate di/dt and voltage change rate dv/dt during the switching process, is investigated with standard DC-PCT and a PCT with superimposed switching losses. 1200 V IGBTs with two different package forms are used for the PCTs

Electronic assemblies are often utilised in environments in which they are exposed to significant combinations of simultaneous vibration and thermal loads. In this study, vibration durability tests and results under isothermal conditions are presented for SAC105 solder joints of CR0805 chip resistor components. The tests are performed using a specially designed multi-cantilever printed wiring assembly

The purpose of the study is proposing a gate oxide degraded MOSFET model that represents the degraded MOSFET effects on Class-A power amplifier parameters. The model includes electrical stress induced threshold voltage and transconductance parameter instabilities of transistor. The change in threshold voltage is between 3.2 V and -1 V; the change in transconductance parameter is between 0.4A/V2 and

The effect of thermal ageing, fatigue and thermo-mechanical ageing on flexible microelectronic devices is studied and reported from a materials and functional durability perspective. The degradation mechanisms of encapsulant and substrate were both studied. Property changes in encapsulant and substrate materials are analyzed and their relationships in the failure mechanisms of the flexible devices

Insulated Gate Bipolar Transistor (IGBT) is the core power switch device in electrical field. IGBT's reliability is the basis of safe and stable operation for electrical system or equipment. At present, the aging analysis of IGBT mostly focuses on a single failure mode. This paper proposes a new aging parameter based on Miner's linear fatigue cumulative theory. Then this parameter is used to characterize

This paper focuses on the design of two analog nonlinear transformations dedicated to analog signal processing such as energy detection: the square function and the Teager Energy Operator (TEO). Both requiring an analog multiplier, this paper firstly analyses the design equations of a MOS Gilbert cell in order to operate around the mid supply voltage. Considering this, an analog multiplier, having

In order to realize small package size, uniform performance and high manufacture efficiency, a chip scale packaging (CSP) technology has been developed by controlling the thickness of the phosphor film in this paper. Five CSP LEDs with different thicknesses of 4 side faces are prepared. Optical tests and thermal simulations were carried out to evaluate the performance of the five samples. The measurement

In semiconductor manufacturing, pattern analysis of wafer maps is important in terms of failure analysis and activities to increase yield. Image classification research using deep learning becomes popular; its application in wafer map classification in semiconductor manufacturing is also growing. However, to improve defect analysis accuracy, through-wafer map classification and clustering, more accurate

The computational workload involved in CNNs is typically out of reach for low-power embedded devices. The Approximate Computing paradigm can be exploited to reduce the CNN complexity since it improves performances and energy-efficiency by relaxing the need for fully accurate operations. In this work, we target weight-sharing as an approximate technique to reduce the memory footprint of a CNN. More

In this work, we observe the distinct VTH characteristics in the Au-free gate-first processing p-GaN/AlGaN/GaN HEMTs with two commonly used passivation layers, i.e., SiN and SiO2. The lower incorporated H was found in the p-GaN/AlGaN/GaN heterostructure with higher activation anneal temperature (i.e., 700 °C). Furthermore, Photoluminescence (PL) spectrum demonstrates a higher blue luminescence (BL)

This paper presents the transient dose rate (TDR) effect of analog Delay Locked Loops (DLLs). The analog DLL circuits are built upon a previous design, and the typical photocurrents are calculated by the Sentaurus TCAD. Both single double-exponential and dual double-exponential functions are successfully introduced to fit the different photocurrent waveforms with change of the simulated nodes, which

A two-dimensional analysis of the off-state breakdown characteristics in field-plate AlGaN/GaN HEMTs is performed. The gate-to-drain distance is 1.5 μm, and the parameters are the SiN passivation-layer thickness d and the field-plate length LFP. For a moderate d of 0.1 μm, the breakdown voltage Vbr increases with LFP, and takes an maximum value (~400 V) around LFP = 0.3 μm, and decreases when LFP becomes

Polymers are highly affected by moisture and temperature in terms of reliability of packaging. Especially, interface delamination between dissimilar materials with polymer is one of the major issues to the structural integrity and reliability, which is affected significantly by temperature and moisture concentration. In this paper, moisture absorption characteristics and thermo-mechanical delamination

The degradation behavior and lifetime of LEDs for field operation is currently predominantly estimated using LM-80 data in combination with TM-21 extrapolations. If the environmental conditions differ significantly from the laboratory conditions of the LM-80 tests, differences in in-situ degradation behavior and TM-21 predictions could occur. Independently of the previous described methods, the following

Total ionizing dose (TID) effects are investigated in a nanosheet gate-all-around field effect transistor using three-dimensional technology computer aided design simulation. TID is a reliability concern in terms of building up trap charges in any dielectric surrounding the transistor body. In this work, the impact of trap charges on different dielectrics including gate oxide, gate spacer and shallow

The performance of the Hodgkin-Huxley neuron circuits used in novel communication and computer systems depends on its capacitors. Thus, degradation of capacitors in neuron circuits may have significant impact on reliability of the neuron. In this paper, a simulation-based reliability assessment approach was developed for a Hodgkin-Huxley neuron circuit to consider the degradation of capacitors. SPICE

A novel approach is presented to evaluate the mechanical stability of back end of line (BEoL) stacks. A SRAM test vehicle manufactured in 28 nm technology with copper pillar bumps is used. In a second step, the validity of the approach is also shown for a second sample manufactured in 22 nm technology and the experimental results are compared. To inflict damage to the BEoL stack of the respective semiconductor

Microcontrollers storing valuable data or using security functions are vulnerable to fault injection attacks. Among the various types of faults, instruction skips induced at runtime proved to be effective against identification routines or encryption algorithms. Until recently, most research works assessed a fault model that consists in a single instruction skip, i.e. the ability to prevent one chosen

Failures on MEMS microphones placed on dummy smartphone are observed during a guided free fall test. The instants before and after the first impact are registered with a high-speed camera and the displacement/velocity signals are used as input for three-dimensional finite element analyses at different scales to obtain insights at local level to judge whether possible ruptures arise. The numerical procedure

Owing to its low cost and high efficiency, the blue light-emitting diode (LED) chip covered with the Y3Al5O12:Ce3+ (YAG) phosphor has become a mainstream technology of high power white LED packaging. However, phosphors are often susceptible to degradation under high-temperature and high-humidity conditions, which directly affects the optical and color stability of the white LED package. In this study

This paper tackles the analog and mixed-signal modeling for verification challenges. It proposes an adjustable automated modeling approach, which provides set-valued models with reduced overapproximation. The models reliably enclose parameter variations and modeling errors. The reduced overapproximation is obtained by computing the intersecting set of models with intervals and affine forms. The nonlinear

Power electronic devices are very important component of power processing circuits. However, sometimes under circuit overstress, they may face abrupt failures. Lifetime prediction is needed to prevent these sudden failures in power devices. However, the random noise and errors in the measurement data make the existing methods have large prediction errors. This paper proposes a fusion method based on

We measured the stress in a Si chip mounted on a Cu plate using Raman spectroscopy and compared the results with those calculated by using the finite element method (FEM). The difference in the stress observed at the vicinity of the chip edge was approximately 30 MPa, and the simulated value was smaller than that observed using Raman spectroscopy. We found that the difference occurred owing to the

Overheating is the cause of PIN limiter diode damage under a high-power electromagnetic pulse, but the physical mechanism for overheating has not previously been clarified and thus is studied in this paper through measurements and simulations. The damage process of the PIN limiter diode SMP1330 is measured first, where a drastic voltage drop is observed. The mechanism causing the voltage drop is analyzed

The impact of heavy ion energy and species on single-event upsets (SEU) sensitivity in state-of-the-art NAND Flash memories is investigated in this paper. Experimental results indicate that the heavy ion with the same linear-energy-transfer (LET) but higher energy and mass will cause a decrease in the SEU cross-section of the three kinds of floating gate cells when the device surface LET value is 37

A methodology is proposed to emulate and assess the single event effect in configuration memory on 16 nm Ultrascale+ MPSoC. The solution depends on fault injection and fault tree analysis. Three image processing applications, including histogram computation, image stretch and sobel edge detection, are used as the benchmarks. The results demonstrate 38.1% to 40.5% system errors cannot be recovered,

Quad-Flat-No-Lead (QFN) packages are electric components that are producing a substantial amount of heat during operation due to significant power loss. Resulting elevated temperatures can lead to critical damage of the chip and the package, which could cause a loss of functionality. Therefore, controlling the maximum temperature within the package is crucial. Using thermal vias embedded in the PCB

This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core lockstep (DCLS) technique to mitigate single event upset (SEU) and common-mode failure (CMF) problems. The Lock-V was deployed in two versions, Lock-VA and Lock-VM by applying design diversity in two processor architectures at the instruction set architecture (ISA)-level. Lock-VA features an Arm Cortex-A9

In this paper, FinFETs are realized by integrating neutral beam etching(NBE) and microwave annealing (MWA) into the fabrication process. Electrical characteristics are measured at room temperature and parameters such as Sub-threshold swing of 89 mV/decade, Ion/Ioff of 106, DIBL of 72 mV/V and effective mobility (μeff) of 502 cm2V−1 s−1 are obtained with Wfin/Lgate = 40/100 nm. These characteristics

The lead‑tin solder has already been replaced by the lead-free solder gradually in most industrial applications according to the RoHS restriction. However, the reliability test duration and the failure mechanism of lead-free solders are always a concerned problem that must be addressed when designing a new electronic product. In this paper, a thermo-electric accelerated test (TEC) method, as well as

The continuous growth and advancements of semiconductor devices for automotive applications and internet-of-things drive the demand and scaling of embedded non-volatile memories (eNVM). Existing eNVM landscape in 40 nm and 28 nm advanced processes is dominated by split-gate flash memory devices (Do, 2016) where inter-poly oxide (IPO) defect is one of the most challenging types of defect to localize

Decision making tasks carried out by the usage of deep neural networks are successfully taking over in many areas, including those that are security critical, such as healthcare, transportation, smart grids, where intentional and unintentional failures can be disastrous. Edge computing systems are becoming ubiquitous nowadays, often serving deep learning tasks that do not need to be sent over to servers

The major design parameters of embedded cache memory (SRAM memory cell) are speed, power consumption, noise tolerance, and reliability. It is a challenging task to design an SRAM cell in the face of process, voltage, and temperature variations at low supply voltages. At scaled technology node the conventional 6T SRAM cell suffers from read and write failures as well as instability. Moreover, it is

Palladium coated copper (PCC) wire has been increasingly used in the semiconductor package in the last 10 years, especially in consumer products as a low-cost alternative to gold (Au) bonding wire. However, the PCC wire is still not widely used in the automotive industry due to the reliability limitations under a high temperature condition. In order to improve the long term reliability of PCC wire

Full-precision Floating-Point Units (FPUs) can be a source of extensive hardware overhead (power consumption, area, memory footprint, etc.). As several modern applications feature an inherent tolerance to precision loss, a new computing paradigm has emerged: Transprecision Computing (TC). TC proposes several tools and techniques that trade precision for energy efficiency. However, most of these tools

In this paper, large-scale molecular dynamic (MD) simulation is performed to investigate the concentration-dependent vacancy volume relaxation in Al, Cu, and Au, respectively. The vacancy volume relaxation factor is calculated and correlated to the microstructure change based on MD results. It is found that the vacancy volume relaxation factor is nearly a constant at low to mid-vacancy concentration