The drain current of the amorphous InGaZnO thin-film transistors (TFTs) shows the Arrhenius and the non-Arrhenius dependence at the high temperature and the low temperature respectively. The gate-voltage-dependent effective temperature is introduced into the Arrhenius equation. Considering the normal Meyer-Neldel (MN) rule and the inverse MN rule, the equation successfully describes both the Arrhenius

Halo implanted MOSFETs exhibit anomalous behavior in drain current power spectral density (SID) of flicker noise (1/f) with the variation in drain voltage, but this behavior cannot be captured by existing 1/f models. To identify the reasons for this abnormal behavior of 1/f noise, we have performed experimentally calibrated technology computer-aided design (TCAD) simulations. We find that this anomalous

Low frequency noise (LFN) studies are carried out on n-channel gate all around nanowire (GAA NW) FETs. Measurements both as a function of applied polarisation at fixed temperature and conserving the same drain current bias points as a function of temperature are performed, to investigate the predominant flicker noise fluctuation mechanism and to execute low frequency noise spectroscopy allowing to

A new device structure for the Si tunnel field-effect transistor (TFET) is proposed along with feasible fabrication processes. The device consists of a Si fin with high impurity concentration at the fin surfaces, which are realized using the tilted-ion-implantation technique (TII) to effectively generate the gate-normal band-to-band tunneling (BTBT) and simultaneously create carrier conduction paths

In this paper, the role of gold nanoparticles on the temporal response of a porous silicon gas sensor has been studied. The porous layer was prepared by a laser-assisted etching process using 810 nm wavelength and 2 W infrared laser diode as an illumination photonics source. The experimental etching conditions involve 20 mA/cm2 current density and 10 min etching time. Gold nanoparticles were incorporated

We present a detailed analysis of large-signal Sawyer–Tower measurements on a power GaN HEMT device in OFF-state. The measurements show hysteresis which results in an energy loss dissipated as heat in the range of sub-μJ’s. We model this important phenomenon in this paper using a previously calibrated model of the same device. We propose two models, one with linear Effective Series Resistance (ESR)

We present a TCAD simulation of the negative capacitance gate-all-around (NCGAA) field-effect transistor with the 3-D Ginzburg-Landau-Khalatnikov Model. The baseline device is based on the 2020 IRDS Table, and the mobility model is calibrated to account for ballistic transport and to match the “1.5nm node” IRDS on-current requirement. The NC parameters are extracted from experimental C-V data. The

The effect of high-temperature irradiation with 15 MeV protons on the parameters of high-voltage 4H-SiC Schottky diodes has been studied at irradiation temperatures of 23-500°C and doses in the range from 7×1013 to 2×1014 cm-2. After the irradiation with a dose of 1014 cm-2 at room temperature, the forward current at a forward voltage U = 2 V decreases by ∼10 orders of magnitude. In this case, the

Logic gates are designed using symmetric lateral doping-free bipolar junction transistor (BJT) on silicon on insulator (SOI) using differential pass transistor logic, and their performance matrices are presented. Charge carriers are induced in lightly doped emitter and collector regions using two unique approaches. i.e., the charge plasma (CP) and polarity control (PC). AND, OR and XOR gates are designed

With the recent advances in carbon nanotube (CNT) electronics, transistors made of thin films of single wall CNTs (SWNTs) are gaining great attention due to their high quality electrical characteristics. With such improvements it has become essential to develop suitable models to accurately predict the electrical transport in such devices which in the current scenario remains scarce. This work presents

In this paper, an Al/Ti Schottky-electrode was fabricated on a 4H- SiC surface via sputtering, and an Al2O3 layer was inserted into the metal semiconductor contact-surface using atomic-layer deposition. We studied the inhomogeneity of the Schottky-barrier height by inserting the dielectric layer (Al2O3) with different thicknesses. The Schottky-barrier heights and ideality factors were extracted for

In this paper, we proposed an equivalent circuit of a cell device (high-voltage silicon diode), considering effects of temperature and reverse voltage on it, and obtained the analytical expression of impedance of a cell device. Subsequently, in order to improve the reverse voltage distribution of the high-voltage diode stack consisting of a serial connection of cell devices, uniform voltage impedance

Dye sensitized solar cells (DSSCs) have been in the research limelight for some years and plenty of research were devoted to the investigation of material properties for device enhancement. The electrical modeling facilitates the simulation of the device characteristics of the DSSCs. In order to develop highly efficient DSSCs, it is crucial to elucidate the electric mechanism within the cell through

Ageing effect on the performance of Ag/ITO/MoOx/n-Si/LiFx/Al carrier selective contact (CSC) silicon solar cells has been investigated based on silicon surface morphology (planar, different pyramid sizes, and chemical polishing of pyramids). The cells with small silicon pyramids (~2 µm) have shown better stability with time than the medium/large pyramids (~5/~8 µm). The chemical polishing of pyramid

We have investigated the exchange bias effect in La0.7Sr0.3MnO3/SrRuO3 bilayers that epitaxial grown in different directions and various substrates. A linear-tunable exchange bias effect, which related to the spin states of the SrRuO3 layers have been discovered. The spin state of Ru4+ play the centre role in the interaction, and proposes mechanisms to understand the Mn-O-Ru antiferromagnetic coupling

This article reports the fabrication and characterization of metal–semiconductor high electron mobility transistors (MS-HEMT) and metal–oxidesemiconductor (MIS-HEMT) grown on the semi-insulating SiC substrates with 0° and 4°-off axis. For the MIS-HEMT, the HfO2 film was used as the insulator deposited by atomic layer deposition. With a gate length of 2 μm, MS-HEMT and MIS-HEMT devices with 4°-off SiC

As an important part of three-dimensional (3D) magnetic sensors, the vertical Hall devices directly determine the overall performance of the sensors. However, the traditional vertical Hall devices (5CVHD) have large offset and low sensitivity due to an inherent electrical asymmetry. In order to solve this problem, the traditional five-contact vertical Hall devices are optimized to obtain the five-contact

A polycrystalline silicon vertical thin film transistor (VTFT) is fabricated, and the electrical parameters are extracted and compared with the typical lateral thin film transistor (LTFT). The similar subthreshold slope and the distinct field effect mobility is verified by the DOS calculation in the deep and shallow trap regions, respectively, and in this article, it is used to compare with the grain

When the AlGaN/GaN HEMT is working for a long time under the high-power and high-temperature conditions, the internal heat will reduce its reliability. Here, the author first proposed a 2-D temperature distribution model to explain the mechanism of internal charge modulation to reduce the junction temperature of AlGaN / GaN HEMT. The etched AlGaN layer affects the channel 2DEG distribution and a new

We demonstrate effective reduction of interface states and current collapse in AlGaN/GaN metal insulator semiconductor heterostructure field effect transistor (MISHFETs) with Al2O3 and in-situ AlN passivation layer. Here, first, a 3 nm-thick in-situ AlN layer is grown on AlGaN/GaN structure by using MOCVD at 1070 °C, and second a 7 nm-thick atomic layer deposition (ALD) Al2O3 layer is immediately deposited

We present two novel barrier-well heterostructure diodes, for use as zero bias detectors in microwave and mm-wave applications. One based on the GaAs platform and one based on In0.53Ga0.47As lattice matched to InP. This is achieved by adding quantum wells to Asymmetric Spacer Layer Tunnel (ASPAT) diodes next to the barrier. The DC characteristics of these new diodes were simulated in SILVACO Atlas

In this work, voltage distributions of forming operations are analyzed by using an advanced statistical approach based on phase-type distributions (PHD). The experimental data were collected from batches of 128 HfO2-based RRAM devices integrated in 4-kbit arrays. Three different switching oxides, namely, polycrystalline HfO2, amorphous HfO2, and Al-doped HfO2, were tested in the temperature range from

We investigated the effect of growth temperature on the structural and electrical properties of InAlAs layers grown on InP (1 0 0) substrates by metalorganic chemical vapor deposition (MOCVD) method. Flat surface morphology of InAlAs layers with root mean square (RMS) surface roughness values below 0.4 nm were obtained at 500 °C and 660 °C, while RMS surface roughness values of InAlAs layers grown

In this paper, we propose a stochastic model for the resistive switching of ReRAM devices with 1T1R configuration. We work with the fact that the switching occurs in the narrowest zone of the conductive filament due to changes caused by the electric field. This active region is represented by a net of vertical connections, each one composed of three electrical elements: two of them are always low resistive

This paper describes device simulation studies of surface and buffer trapping effects on static I-V, output-admittance (Y22), and transient characteristics of AlGaN/GaN HEMTs. The TCAD simulation model considering surface donors at EC − 0.5 eV and buffer traps at EC − 0.47 eV have been used to quantitatively reproduce the measured DC, Y22 frequency dispersion, gate-lag (GL) and drain-lag (DL) transients

In this work we report on the integration of indium oxide (In2O3) nanoparticles (NPs) for Resistive Random Access Memory (RRAM) applications. This low-temperature integration process is fully compatible CMOS Back-End integration given a carefull selection of materials deposited by MOCVD and ALD. A detailed description of the process is provided together with AFM analysis performed on the indium oxide

Herein, we investigated the effect of organic solvent drop-casting and solvent vapour annealing (SVA) on the surface morphology of copper phthalocyanine (CuPc) and its effect on the transistor performance and contact resistance in organic field effect transistors (OFETs). Organic solvents: acetone and isopropyl alcohol (IPA) are used for drop-casting and SVA treatment of CuPc film. The morphology,

A detailed and didactic analysis of the diffusivity in a 2D inversion layer is carried out, providing its dependence on carrier density and temperature. Then, a comprehensive study of the diffusion and drift current components in a MOSFET is proposed. Their dependence with gate and drain voltages is investigated down to deep cryogenic temperature, revealing that at T = 4 K the diffusion current is

We report a comparative study of metamorphic InAs p-i-n photodetectors epitaxially grown on GaAs and Si by molecular beam epitaxy. Linearly graded InAlAs buffers were employed to bridge the high lattice mismatch between InAs and Si. Quantitative measurement for threading dislocation density (TDD) in the InAs layers grown on GaAs and Si has been performed using transmission electron microscopy and electron

We fabricated the Fe3O4/alkyl-sulfonic acid molecules hybrid nanoparticles by self-assembly monolayers (SAMs) in air and nitrogen ambience to investigate the impact of the oxidation on the spin transport. X-ray photoelectron spectra (XPS) and Fourier transform infrared (FTIR) spectroscopy measurements infer that the chemical bonding between Fe3O4 and alkyl-sulfonic acid remains unchanged as interfacial

A compact charge model for Si gate-all-around n-type metal-oxide-semiconductor capacitors (nMOSCAPs) with cylindrical cross-sections including the quantum confinement effect is presented. The density-gradient equation with a penetrating boundary condition is integrated to consider the quantum confinement effect. From the integrated equation, an expression for the surface potential is derived, and a

Z2-FET, a partially gated diode, was explored for ESD protection due to its sharp switching behavior and is also a promising candidate for 1T-DRAM application. Based on detailed TCAD simulations, we develop a pragmatic SPICE compact model, including DC and memory operation. The model is validated via TCAD and experimental data. The proposed model reproduces the S-shaped V-I characteristics, the hysteresis

Nanoelectromechanical (NEM) device has been regarded as one of the future switching devices due to its nearly infinite switching slope and zero off-state leakage current. However, it suffers from high pull-in voltage which causes high operation voltage. In this study , a sub-15 nm-thick Al-doped HfO2-based ferroelectric (FE) layer with a negative capacitance (NC) that can exceed the scalability limitation

This paper presents a generalized charge-based EKV MOSFET model that includes the effects of trapped charges in the bulk oxide and at the silicon/oxide interface. It is shown that in the presence of oxide- and interface-trapped charges, the mobile charge density can still be linearized but with respect to both the surface potential and the channel voltage. This enables us to derive closed-form expressions

We studied the mechanism of the proton-induced electrical degradation of AlGaN/GaN high electron mobility transistors (HEMTs) through 5-MeV proton irradiation. First, the AlGaN/GaN heterostructure was exposed to protons with a fluence of 1 × 1015 p/cm2 to investigate the relationship between the radiation-caused damage in the heterostructure and the electrical characteristics of HEMTs. The HEMTs fabricated

A physics-based compact model for phase-change random access memory (PcRAM) was proposed considering the ratio of vertical-to-lateral crystal growth rate (α) and it was incorporated into HSPICE via Verilog-A. The proposed model was verified by using the experimental results taken from the 256 × 256 cross-point (X-point) PcRAM cell array with the Ge2Sb2Te5 2z-nm technology node. The proposed compact

In this paper, we demonstrate high-performance lateral AlGaN/GaN Schottky barrier diodes (SBD) on Si substrate with a recessed-anode structure. The optimized rapid etch process provides results in improving etching quality with a 0.26-nm roughness of the anode recessed surface. By using the high work function metal Pt as the Schottky electrode, a low turn-on voltage of 0.71 V is obtained with a high

In this paper, the experimental investigation on the electrical properties of silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT) after total-ionizing-dose (TID) irradiation is presented. We find that the TID irradiation reduces the threshold voltage (Vth), and increases the collector current (ICE) at the same gate voltage (Vg). The raising ICE is mainly attributed to the negative

This work investigates the transient current in the subthreshold region of a low-temperature polycrystalline silicon thin-film transistor (LTPS TFT) on a polyimide (PI) substrate. The measurement of this current shows an instability that is not seen in the device on a glass substrate; the instability appears as a current variation under constant voltage and overshoot or undershoot under external stress

An accurate and efficient parasitic parameter extraction method is proposed for gallium nitride (GaN) high electron-mobility transistors (HEMTs). In this letter, a 19-element small signal equivalent circuit model is established to describe the characteristics of the device precisely. The simulation of the high frequency behavior is improved by introducing the series parasitic inductances into the cold

In this work, a continuous and symmetric trans-capacitance compact model for triple-gate junctionless MOSFETs is presented, valid in all regions of operation. Initially, the expressions of the gate, drain and source total charges are analytically derived based on a continuous and symmetric drain current compact model already developed. Then, the intrinsic capacitances are calculated via the differentiation

Charge stabilities and spin-based quantum bit (qubit) operations in Si double quantum dot (DQD) systems, whose confinement potentials are controlled with multiple gate electrodes, are theoretically studied with a multi-scale modeling approach that combines electronic structure simulations and a Thomas-Fermi method. Taking Si/SiGe heterostructures as the target of modeling, this work presents in-depth

Several methods of depositing pure boron (PureB) layers on silicon are examined with respect to their potential for fabricating advanced PureB (photo)diodes with back-end-of-line (BEOL) CMOS compatibility. PureB devices were fabricated in two different batch furnace chemical-vapor deposition (CVD) systems or by electron-beam-assisted physical-vapor deposition (EBPVD), and their electrical characteristics

InAs nanowires (NWs) were selectively grown on hole patterned InP (111)B substrate by Metal-Organic Chemical Vapor Deposition (MOCVD). This study reports the vertical growth behavior of InAs NWs transitioned at a certain height and its difference under various growth conditions. This certain height is referred as “critical height.” This is a boundary where both vertical and lateral growth occur. Under

We analyzed Incremental Step Pulse Programming (ISPP) slope degradation to improve the program efficiency of 3D NAND Flash memory using both measurement and simulation data. The simulation data are calibrated with the measurement data and they are in good agreement. The ISPP slope indicates program efficiency and its ideal value is 1. In reality, however, ISPP slope degradation (< 1) occurs in the

We observed abnormal threshold voltage (VT) shift in amorphous InGaZnO (a-IGZO) thin-film transistors under negative gate bias stress (NBS) after soaking them in H2O (pH 8). Before NBS, we soaked a-IGZO TFTs in H2O. During application of NBS, VT decreased by −0.43 V, then increased to nearly the initial value. We hypothesize that the electrical field that was applied during NBS caused some dissociation

Conventional Hall effect devices are designed to respond to a single magnetic field component in 3D space. However, if plastic encapsulated Hall effect devices in cubic crystals are exposed to poorly defined and unstable mechanical shear stress, small portions of unwanted, perpendicular magnetic field components will show up in the Hall output signals. Mathematically, any such crosstalk – may it originate

The built-in bipolar junction transistor of H-gate partially depleted SOI NMOS was characterized by measuring the common-emitter output curve and calculating the common-emitter current gain. Unoptimized doping results in a low common-emitter current gain. The bias state of the front gate of the MOS has a significant influence on the characteristics of the built-in BJT. The geometry effect of the device

Pattern-recessed ohmic contacts are investigated for InAlGaN/GaN high-electron-mobility transistors (HEMTs). Periodically-recessed patterns are introduced in the source and drain contact area to achieve the lower contact resistance by making sidewall contact as well as top contact on the active mesa. The lowest ohmic contact resistance (Rc) of 0.19 Ω·mm is achieved. It is significantly lower than the

Silicon Photonics Technology using sub micrometer SOI platform, which commercially emerged at the beginning of the century, has now gained market shares in the field of fiber optic interconnects, from Inter-to Intra-Data Center communications. With growing demands in terms of aggregated bandwidth, scalability, transceiver form factor, and cost, Silicon Photonics is expected to play a growing role,

The triboelectric nanogenerator (TENG) based on the contact-electrification and electrostatic induction are attractive for the abundant application in many disciplines. To explore the practical application of TENG devices, we firstly reported a novel TENG based on the white sugar (WS-TENG) to harvest mechanical energy, and simultaneously, which can also serve as the self-powered humidity sensor due

The thermal-oxidation/wet-etching gate-recess mask using low-pressure-chemical-vapor-deposition (LPCVD) SiN/atomic-layer-deposition (ALD) AlN combined with high-quality LPCVD-SiN/ALD-SiO2 gate dielectric has been developed for the fabrication of normally-off GaN MISFETs by the self-terminated gate recess etching technique. The experimental results showed that the SiN/AlN layer could effectively hinder

Recently, negative capacitance (NC) effect in the dielectric/ferroelectric (DE/FE) bilayer system has received significant attention due to its potential in achieving sub- 60 mV/decade subthreshold swing in FETs as well as extremely large capacitance density in dynamic random-access memory (DRAM). However, such reports, to date, are primarily based on conventional perovskite FE materials which are

A systematic method for the verification of high frequency measurement (up-to 500 GHz) of silicon germanium heterojunction bipolar transistor (SiGe HBT) is proposed. First of all, the method involves an accurate estimation of the effects of passive environment on the overall measurement by a detailed electro-magnetic (EM) simulation. This ensures that the complete measurement environment like probes

Due to their excellent photo-to-electric power conversion efficiency (PCE) (up to 25.2%) under AM 1.5G (≈100,000 Lux), the perovskite solar cells (PSCs) have received widespread attention in recent years, but the research on their weak light (0–1000 Lux) performances is still rare. So, the effect factors of their weak light performances were explored in this work. According to the results, the PSCs

It is important to characterize the distribution of spatial traps in the MOS structure for separating the interface states from the subgap density-of-states. In this study, we report a characterization technique for the spatial distribution of traps using the C-V characteristics under deep-depletion bias. Depletion capacitance is determined by the depletion depth (Xd) and the dielectric constant with

For pragmatic utilizations of field-effect transistors (FETs), the control of threshold voltage (Vth) is significant for sensing applications as various sensors and circuits require distinctive electrical characteristics. Moreover, the controllable threshold voltage is essential for creating integrated circuits (IC). The threshold voltage of a TFT is sensitive to numerous factors, which make it alluring

Processing techniques for the thickness-controlled layer separation of a single-crystalline semiconductor have been actively developed for manufacturing complementary metal–oxide–semiconductor (CMOS)-technology-based flexible devices. A mechanical separation process for thin semiconductor layers, called the spalling technique, has recently attracted much attention because of its process simplicity