In this paper, a small-signal model of Negative Capacitance FETs (NCFETs) is developed and the analog performance of NCFETs is studied using the developed model. A new ferroelectric factor K is introduced to capture the ferroelectric gain in NCFETs as compared to traditional small signal MOSFET/FinFET models. Using our new NCFET small-signal model, we show analog design trade-offs between various analog

The electrical characteristics of diamond Schottky p-i-n diodes grown by plasma enhanced chemical vapor deposition have been measured from DC to 25 GHz and used to extract the small-signal parameters for a lumped-element compact model. The model accurately reproduces the forward and reverse bias DC characteristics, the capacitance-voltage behavior, as well as the insertion and reflection loss. The

Al/TE (top electrode)/AlOx/Pt RRAM (resistive random access memory) devices with solution-processed spin-coated AlOx layers annealed at various temperatures (225/250/275 °C) exhibited typical bipolar resistive switching performance with low SET/RESET voltage (<4 V), larger ON/OFF ratio (>103) and excellent stability (retention time over 104 s and endurance cycles more than 100). Ni and TiN were chosen

Thermal resistance (Rth) is an important design parameter for high power integrated circuits (ICs). Evaluation of Rth is particularly complicated for FETs in CMOS silicon-on-insulator (SOI) technology. Although the buried oxide underneath FETs in CMOS ICs presents a barrier to heat flow, the interconnect metals and surrounding oxide provide additional paths for heat-sinking. This paper describes simulations

Vgmax Hot-Carrier-Injection (HCI) degradation in Multi-finger p-Laterally-Diffused Metal-Oxide-Semiconductor Field-Effect-Transistors (LDMOSFET) had been investigated by Multi-Region Direct-Current-Current-Voltage (MR-DCIV) characterization method-probing the interface state distribution along the channel, accumulation and (Shallow Trench Isolation) STI-drift region. The method feasibility was verified

This brief proposes an analytical approach to model the DC electrical behavior of extremely narrow cylindrical junctionless nanowire field-effect transistors (JL-NW-FETs). The model includes explicit expressions, taking into account the first-order perturbation theory for calculating eigenstates and corresponding wave-functions obtained by the Schrödinger equation in the cylindrical-coordinate. Assessment

In this work, we studied different proportions of Mo-C alloy Schottky contacts. Compare the electrical characteristics and SiC interface with the Mo/4H-SiC based diodes. The Schottky interface obtained was studied at different annealing temperatures and its electrical properties were analyzed. Analyze electrical performance through temperature-related current-voltage (I-V) and capacitance-voltage (C-V)

A theoretical model is proposed to characterize the transient operation of Pseudo-MOSFET under gate pulses by considering the substrate effect. The analysis provides Zerbst-like expression of drain current with substrate biased in deep-depletion state. The model can be used for the extraction of carrier lifetime with process parameter variations. The dependence of temperature on carrier lifetime was

This study experimentally investigated the hot-carrier-induced device degradations in Schottky barrier (SB) ambipolar polysilicon transistors and validated the degradation mechanism. The behavior of hot-carrier-induced device degradation in SB ambipolar transistors was different from that of a unipolar MOSFET. The phenomenon of hot-carrier generation at the source electrode, attributed to the existence

Charge trapping is studied in the context of random telegraph noise (RTN) and low-frequency noise (1/f noise), aiming unified statistical modeling. Analytical formulations for 1/f noise (frequency domain) and RTN (time domain) have been derived, using a single modeling framework, where model parameters are the same in frequency and time domain. The modeling addresses the time dependent variability

Under optical illumination of metal–insulator-semiconductor field effect transistors with insulated gate structure (MISFETs including MOSFETs and TFTs), photo-generated electron-hole pairs (ehp’s) cause the photovoltaic effect (PVE) and the photoconductive effect (PCE) in the electrical characteristics of MISFETs. In the modeling and characterization of MISFETs under optical excitation for both optical

In this paper, enhancement-mode AlGaN/GaN p-type GaN cap layer high electron mobility transistors (p-GaN HEMTs) with Ti/Au gate metal are fabricated and electrically characterized. The post gate annealing (PGA) treatment at 300 °C for 10 min is utilized to improve the devices’ characteristics. As a result, the p-GaN HEMTs achieve a high drain current (IDS) of 490 mA/mm at VGS = 7 V with a high threshold

Radio-frequency (RF) high-power high electron mobility transistors (HEMTs) are fabricated with multiple fingers and larger widths to increase the output delivered power. The increased power handling capability is a consequence of the increased capability of handling a larger drain-to-source current. The current is distributed over multiple fingers to keep the current and power density low to avoid

In this paper we compare the performances of SiN with respect to an optimized SiC encapsulation in Wall based Phase-Change Memory (PCM) integrating a Ge-rich Ge-Sb-Te alloy (GGST) suitable for high temperature stability in automotive applications. Thanks to the electrical characterization of 4 kb arrays, 3D electro-thermal simulations and TEM analyses performed on programmed devices, we demonstrate

Poisson-Schrödinger (PS) simulations and an analytical charge model for a back biased FDSOI structure operated at deep cryogenic temperatures have been developed. PS simulations have been conducted down to 0 K, where metallic statistics applies, by replacing the F0 Fermi integral by a Heaviside function. Considering, as a first approximation, two separated channels for front and back interface, a set

Ferroelectric tunnel junction devices based on ferroelectric thin films of solid solutions of hafnium dioxide can enable CMOS integration of ultra-low power ferroelectric devices with potential for memory and emerging computing schemes such as in-memory computing and neuromorphic applications. In this work, we present ferroelectric tunnel junctions based on Hf0.5Zr0.5O2 with materials and processes

In this paper, we studied the electrical and structural properties of Ni/Si/Al Ohmic contacts to p-type 4H-SiC. The p-type epilayer (NA = 1 × 1019 cm−3) was grown on the N-type epilayer with Al dopants. The properties of Ni/Si/Al contacts were analyzed by changing the thickness of Si film and the annealing temperature. After annealing at 700 °C, the Ni/Si/Al contact forms ohmic contact. Compared to

Since two decades ago, research on resistive memories has continuosly grown, gathering relevance through the variety of different technologies that fit into the non-volatile memories’ area. In this study, we discuss the performance and electrical characteristics of RRAM cells constituted by MIM stacks with dielectric formed by Nb2O5-doped SiO2. We report experimental results that show a clear improvement

Nanolayers of pure boron (PureB) deposited on Si form p+-type regions at deposition temperatures from 50 °C to 700 °C. At 700 °C, commercial PureB photodiodes are produced for advanced detection systems including those in extreme-ultraviolet (EUV) lithography systems. In addition, potent MEMS applications of B-nanolayers have been demonstrated. Attractive diode characteristics were also found for devices

Due to the thin InAlN barrier layer, leakage current is a serious problem in InAlN/GaN high-electron-mobility transistors (HEMTs). The InGaN back-barrier can raise the conduction band of the GaN buffer layer and enhance the carrier confinement, resulting in a reduced buffer leakage current. The surface oxidation treatment prior to gate deposition can form an oxide layer and reduce the barrier leakage

This paper reports on the study of inverted metal-oxide semiconductor (MOS) structures formed through mechanical exfoliation of MoS2 flakes onto Al2O3 or SiO2 layers grown on degenerately doped p type silicon substrates. Using Au/Ni metal top contacts, multi-frequency capacitance and conductance characterisation were performed to investigate electrically active defects in the MoS2/oxide structures

Capacitive Metal-Insulator-Semiconductor structures with graphene as interfacial layer between the HfO2 dielectric and the top electrode have been fabricated and investigated at device level and at the nanoscale with Conductive Atomic Force Microscope. In particular, their electrical properties and variability have been compared to devices without graphene to evaluate their feasibility as ReRAM devices

A drift-diffusion approach to coupled spin and charge transport has been commonly applied to determine the spin-transfer torque acting on the magnetization in metallic valves. This approach, however, is not suitable to describe the predominant tunnel transport in magnetic tunnel junctions. In this work we present a coupled Finite Element solution to the spin and charge drift–diffusion equations. We

We report on a quantitative use of Kelvin probe force microscopy (KPFM) for the analysis of charge injection in thin oxides. Here, thin dielectrics are investigated through an atomic force microscopy tip that is used as a movable (virtual) top-electrode. The charge is injected and read-out respectively by alternating the direct contact of the probe with the oxide, and with non-contact surface potential

A novel, low temperature process for the formation of Si-BC8 phase is obtained while growing Silicon nanowires. The nanowires growth is performed in a CVD reactor under exposure of the substrate to microwaves, employing Sn nanospheres as catalyst and a flux of SiH4 as precursor, respectively. Microwaves allow for selective heating of the metal catalyst while keeping the substrate at low temperature

Thin layers of MoOx have been deposited by thermal evaporation followed by post-deposition annealing. The density of states distributions of the MoOx films were extracted deconvoluting the absorption spectra, measured by a photothermal deflection spectroscopy setup, including the small polaron contribution. Results revealed a sub-band defect distribution centered 1.1 eV below the conduction band; the

Current annealing, which utilizes high level of drain current during device fabrication, is proposed. A semiconductor device β-Ga2O3 field-effect transistor is preferred as test vehicle because of its inherently high drain current. With just a few seconds of current annealing, drain output performance can be boosted more than 50 % without adding other processes. Both electrical measurements and numerical

In recent years, laminates consisting of alternating layers of two binary oxides with layer thicknesses below 1 nm have attracted attention for their high dielectric constant values, reaching values of about 1000 in the case of Al2O3/TiO2 sub-nanometric laminates. This excellent dielectric performance of the sub-nanometric laminates relies on the Maxwell Wagner (MW) relaxation, exploiting the blocking

In this paper, for the first time, we apply the ultra-low-power (ULP) diode concept with Schottky Barrier (SB) transistors and analyze their performance in comparison to standard CMOS, using calibrated TCAD mixed-mode simulations. The negative impedance characteristics obtained in reverse mode with SB devices are shown to offer more stable current characteristics compared to CMOS, especially as a function

This paper deals with the behavior of degradation by NBTI effect in pMOS junctionless nanowire transistors (JNTs). The analysis has been performed through measurements followed by 3D numerical simulations and has shown that the increase in the oxygen precursors density close to the interface leads to the reduction of the saturation in the NBTI effect when the devices operate in partial depletion regime

A cheap, compact and customisable characterisation system for memristor devices, working between ± 10 V, is presented. SPICE (Simulation Program with Integrated Circuit Emphasis) simulations are performed to verify the circuit feasibility and a proper software is developed to drive the system. The potentiality of the realised system is tested by performing several electrical measurements on both Cu/HfO2/Pt

Nature of gap states in chalcogenide semiconductors GexSe1-x is studied by combining X-ray photoelectron (XPS) and absorption (NEXAFS) spectroscopy with photoconductivity (PC) and internal photoemission (IPE) measurements at the semiconductor/insulator interface. It is shown that studied GexSe1-x layers are heterogeneous composite-like matrices and the gap states determining electron transport originate

Two different Kelvin Probe Force Microscopy (KPFM) measurement configurations have been combined to evaluate at the nanoscale the effects of an electrical stress on Organic Thin Film Transistors (OTFTs) properties. As an example, Channel Hot Carrier (CHC) degradation has been induced to provoke some damage in the studied devices. The results show that the use of the two KPFM configurations, together

An Operational Transconductance Amplifier (OTA) designed with SiGe-source nanowire Tunnel-FETs is presented and compared with OTAs designed with Si nanowire (NW) TFETs and Si NW MOSFETs with and without the effect of gate current (IG). The devices were modeled using Verilog-A language through lookup tables obtained by experimental data and they were used to simulate the OTA circuits. It was observed

The reconfigurable field-effect transistor (RFET), is an electronic device whose conduction mechanism can be reversibly reconfigured between n-type and p-type operation modes. To enable this functionality, those devices do not rely on chemical doping caused by impurities but rather on electrostatic doping, i.e. the generation of mobile carriers via an external potential. This functionality has been

28 nm FD-SOI technology is electrically characterized aiming at cryogenic applications. Electrostatics and transport are evaluated and compared while lowering temperature from 300 K down to 4.2 K. Split CV technique is applied in both long and short channel transistors thanks to multiple parallel structures designed to increase the gate area. FD-SOI versatility is shown over a wide temperature range

In this work, we investigated the effects of annealing temperature and metal thickness on the Schottky barrier height in state-of-the-art Ti/4H-SiC rectifiers. By varying these two parameters, a controlled lowering of the Schottky barrier height has been obtained, thus giving the possibility to improve the efficiency of device in terms of power consumption.

In this work, a current-to-transconductance ratio technique is proposed for simultaneous extraction of the threshold voltage (VT) and parasitic source (RS) and drain (RD) resistances in short channel metal–oxide–semiconductor field-effect transistors (MOSFETs). The proposed technique allows simultaneous extraction of RS, RD, and VT in any single MOSFET with the channel length modulation (CLM) and the

In this work, the DC behavior of AlGaN/GaN Metal-Insulator-Semiconductor high electron mobility transistors (MO(I)SHEMTs) with two different gate dielectrics (Al2O3 and Si3N4) is analyzed through the experimental comparison of their basic and analog parameters. The transistors with Si3N4 insulator are more closely related to the normally-off devices (less negative threshold voltage) and less affected

Despite the breathtaking progress already achieved for electronic devices built from 2D materials, they are still far from exploiting their full theoretical performance potential. Many of these problems are due to the lack of suitable insulators which would go along with 2D materials as nicely as SiO2 goes with Si. For instance, amorphous oxides known from Si technologies contain numerous defects which

Nanoribbons built on gateless (GL) Ultra-Thin Body and Buried Oxide (UTBB) Back Enhanced SOI (BESOI) pMOSFET are analyzed as a charge-based (CB) biosensor for different sensing materials and device’s dimensions. Experimental GL UTBB BESOI pMOSFET are used as a reference structure for the CB biosensor and the influence of different materials and the device’s dimensions are studied by numerical simulations

Dipole layers can be formed at epitaxial interfaces of perovskite oxides by intentionally inserting charged atomic layers. Perovskite oxides such as SrTiO3 (STO) can provide dielectrics with very high dielectric constants, but their bandgaps are so small that the suppression of leakage current is one of the critical issues when they are applied for DRAM capacitors. However, their conduction band offset

A study of convolutional neural networks (CNNs) was performed to analyze the influence of quantization and variability in the network synaptic weights. Different CNNs were considered accounting for the number of convolutional layers, size of the filters in the convolutional layer, number of neurons in the final network layers and different sets of quantization levels. The conductance levels of fabricated

In this paper a split-gate LDMOS transistor is investigated. A dedicated terminal, namely split-gate, is introduced in order to control the field plate region separately with respect to the channel region. The performances of the device, in terms of on-resistance, breakdown voltage and capacitances, are compared with those of a conventional device. The hot-carrier-induced degradation of the device

In nowadays deeply scaled CMOS technologies, time-zero and time-dependent variability effects have become important concerns for analog and digital circuit design. For instance, transistor parameter shifts caused by Bias Temperature Instability and Hot-Carrier Injection phenomena can lead to progressive deviations of the circuit performance or even to its catastrophic failure. In this scenario, and

Two-dimensional (2D) materials represent an emerging technology for transistor electronics in view of their attractive electrical and mechanical properties. This work investigates molybdenum disulfide (MoS2) based field-effect transistors (FETs) fabricated on paper substrate for designing both digital and analog circuits, such as inverter, current mirror, and Physical Unclonable Function (PUF) bitcell

Graphene Nanoribbons (GNRs) are an emerging candidate to challenge the place of current semiconductor-based technology. In this work, we extend a model for Armchair Graphene Nanoribbons Field-Effect Transistor (AGNRFET) to the high-k dielectrics realm and examine the influences of quantum capacitance on its transient phenomena. The model is coded with Verilog-A and evaluated through SPICE simulations

The positive flat-band voltage (VFB) shifts of 4H-SiC (0001) MOS capacitors with Al2O3/SiO2 dielectric layers were systematically investigated. After nitridation, there was a negative shift of VFB due to the dipole layer at the SiO2/4H-SiC interface induced by Si-N bonds. However, with Al2O3 layer deposition on thermally grown oxide, an additional dipole layer was formed at the Al2O3/SiO2 interface

In this paper, we explore the use of a 180 nm CMOS single-poly technology platform for realizing analog Deep Neural Network integrated circuits. The analysis focuses on analog vector–matrix multiplier architectures, one of the main building blocks of a neural network, implementing in-memory computation using Floating-Gate multi-level non-volatile memories. We present two memory options, suited either

In this work, we review progress in III-V transistor technologies. Key approaches for silicon integration are described, with a distinction being made between large area layer transfer and selective growth techniques. We show how the integration approach must be tailored for the intended application to maximize performance, functionality and minimize cost. We also highlight performance boosters such

Lead-free magnetoelectric (ME) composites comprises NiFe2O4 (NFO) and BaZr0.2Ti0.8O3 (BZT) were synthesized by using conventional double sintering solid-state reaction technique and it's structural, electric, dielectric, magnetic and ME properties were studied. The spectra of X-ray diffraction displayed the formation of parent phase and presence of two phases within the composites (ferrite-ferroelectric)

In this work, we fabricated the transmission line model test structures of Ti/Al/Ni/Au Ohmic contact on the lattice-matched In0.17Al0.83N/GaN heterostructures, grown on the silicon and sapphire substrates respectively, and studied the temperature-dependent characteristics of the sheet resistance (Rsh) and the specific contact resistivity (ρSC). The ln(Rsh)-ln(T) plot has two distinct linearly dependent

Spin-transfer torque magnetic random-access memory (STT-MRAM) is considered as a premiere candidate for replacing conventional six-transistors static random-access memory (6T-SRAM) in processor caches. This paper explores STT-MRAMs based on double-barrier magnetic tunnel junction with two reference layers (DMTJ), while operating at cryogenic temperatures (77K). To deal with large dynamc energy and

For the first time, we analyse SRAM cells made of ferroelectric based negative capacitance (NC) FinFETs considering both global and local variability via Monte-Carlo circuit simulations. First we compare and explain the impact of variability on the device characteristics and the extracted figures of merit of conventional and NC transistors. Then we show that suppressed relative variability in NCFETs

Resistive switching random access memories are being thoroughly studied as prospective non-volatile memories. In this paper, we report electrical characterization of HfO2:Al2O3based metal-insulator-metal structures devised using atomic layer deposition. Dependences of electrical behavior on HfO2:Al2O3 cycle ratio is studied. An explanation for the differences between the Resistive Switching properties

We demonstrate by means of numerical simulations the switching of a perpendicularly magnetized free layer by spin-orbit torques based on a two-pulse switching scheme with improved writing power efficiency. In this scheme, the first pulse selects the cell, while the second pulse completes the switching deterministically. It is shown that the magnitude of the second current pulse can be reduced to about

This paper presents a study of the physicochemical and the dielectric characteristics of capacitor structures, with an organosilicate polymer fabricated by initiated chemical vapor deposition as dielectric. The polymer evaluated is the poly(trivinyltrimethylcyclotrisiloxane), and a comparative study on different bottom electrodes was performed. Preliminary results demonstrate that iCVD technique permits