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Prof. Debbie G. Senesky has completed her terms as an Editor. On behalf of IEEE ELECTRON DEVICE LETTERS authors, readers, and staff, I would like to express my deepest gratitude for her contributions and service to the journal over the past five years and wish her continued success in her professional endeavors.

Dr. Daewon Ha, having served as an Editor for IEEE ELECTRON DEVICE LETTERS since 2011, has completed his tenure. On behalf of IEEE ELECTRON DEVICE LETTERS staff and readers, I would like to thank him for his excellent contribution and dedicated service to the journal over the past nine years.

It is my pleasure to welcome Prof. Huaqiang Wu to the Editorial Board of IEEE Electron Device Letters. A biography and sketch of Prof. Wu’s research interests can be found below. His subject areas are Memory Device and Technology and Emerging Technologies and Devices.

An on-chip switched tunable inductor based on magnetic flux linkage modification is proposed. The magnetic flux linkage was adjusted through an auxiliary coil that was connected to a flip-flop in parallel with a MOS switch. The inductance was monotonically tuned by applying MOS gate voltages, which had a broad tuning range of 1.32–2.03 nH (42.4%) at 8 GHz. A high quality factor of 61.6 at 8 GHz was

A record high electron mobility of 698 cm 2 / $\text{V}\cdot \text{s}$ in a tensile-strained Ge 0.96 Sn 0.04 nMOSFET is demonstrated in this letter. High-quality GeSn films were epitaxially grown by low-temperature chemical vapor deposition. Different strain conditions in the active GeSn layers were achieved by Ge or GeSn relaxed buffers. A mesa FET structure was used to effectively reduce the OFF

Maximum oscillation frequency ( ${f}_{\textit {MAX}}$ ) of mm-wave transistors is one of the key figures of merit (FOMs) for evaluating the HF-performance of a given technology. However, accurate measurements of ${f}_{\textit {MAX}}$ are very difficult. Determination of ${f}_{\textit {MAX}}$ is significantly affected by the measurement uncertainties in the admittance ( ${y}$ ) parameters. In order

Low-frequency noise (LFN) performances are investigated in a normally-off GaN metal-oxide-semiconductor field-effect transistor (MOSFET) fabricated by utilizing the tetramethylammonium hydroxide (TMAH) wet etching. The normalized power spectral densities ( $\text{S}_{Id}/\text{I}_{d}^{2})$ are measured and perfectly matched with both the correlated mobility fluctuations (CMF) and Hooge mobility fluctuations

By deploying a surface reinforcement layer (SRL) at the interface between Schottky metal and ${p}$ -GaN in the gate stack, a ${p}$ -GaN gate high-electron-mobility transistor (HEMT) with enhanced gate reliability is demonstrated. Prior to the gate metal deposition, the SRL is formed by an oxygen-plasma treatment and a subsequent high-temperature annealing process (at 800 °C) that enables surface reconstruction

A gallium nitride (GaN) ring oscillator based on high-performance one-chip complementary logic (CL) inverters is demonstrated on a conventional ${p}$ -GaN gate power HEMT (high-electron-mobility transistor) platform. It manifests the feasibility of the multiple-stage monolithic integration of GaN CL gates, the most energy-efficient digital circuit configuration, and consequently the potential of deploying

Device-to-device variability of CoFeB/MgO based STT-MRAMs is studied based on experiments and simulations taking into account the influence of interface quality, temperature variation and device dimensionality. Metal-induced gap states resulting from electron transfer at the ferromagnet-tunnel barrier interface significantly influence the effective energy barrier height of these devices irrespective

We demonstrated a resistive random access memory (RRAM) based embedded non-volatile memory (e-NVM) solution integrated in the 0.13 $\mu $ m partially depleted silicon on insulator (PD-SOI) process. The memory devices show excellent reliability. It has good endurance up to 5 electrical cycles without any degradation in low resistance state (LRS) and high resistance state (HRS). It can retain the data

Data retention time distribution of the dynamic random-access memory cell transistor of the 20-nm technology generation has been investigated using the physics-based statistical simulation. Traps cause high leakage current of the leaky cells; however, we found that the reduction of trap is not effective in improving the refresh cycle. Therefore, an effective method is needed to overcome the retention

In this letter, a new multi-level memory cell using low-temperature polycrystalline silicon and oxide (LTPO) thin-film transistor (TFT) backplane is proposed. The multi-bit data storage can be achieved with a simple structure of two transistors and a capacitor, which controls the threshold voltage of a memory cell transistor exactly. In a memory cell, the low-temperature polycrystalline silicon (LTPS)

Wearable and implantable pressure sensors are in great demand for personalized health monitoring. Pressure sensors with low operation voltage and low power-consumption are desired for energy-saving devices. Organic iontronic devices, such as organic electrochemical transistors (OECTs), have demonstrated great potential for low power-consumption bioelectronic sensing applications. The ability to conduct

In this letter, we demonstrate direct high-sensitivity proton detection by novel electrolyte-gated thin-film transistors. Integrating a sol-gel derived oxide channel and liquid electrolytes, a current switching by a factor of $10^{{7}}$ was achieved within a 0.5 V gate window. Manipulation of the ionic strength in the gating solution led to an impressively large electrostatic shift (48 mV/pH), outperforming

Dual-gate (DG) Ion-sensitive thin-film transistor (ISTFT) pH sensors based on tin oxide (SnO x ) channel and Al 2 O 3 sensor membrane have been developed. DG SnO x thin film transistors with Al 2 O 3 dielectrics were fabricated, illustrating effective linear current modulation under top gate bias. The SnO X DG-ISTFTs with 10-nm Al 2 O 3 sensor membrane can operate at a low single supply voltage of

One-dimensional metal-oxide nanowire networks (NNs) are considered as important elements in electronics due to their unique physical and electrical performances. In this letter, Sn 1-x Ga x O NNs were fabricated and field-effect transistors (FETs) based on Sn 1-x Ga x O NNs with different Sn/Ga ratios were constructed. The characteristics of the FETs have been systematically investigated. In order

Oxide semiconductors have emerged as ideal candidate materials for flexible electronics and circuits. However, complementary flip-flops, which are the essential building blocks in sequential circuits, based on all-oxide thin-film transistors (TFTs) have not yet been demonstrated. Here, we employed n-type indium gallium zinc oxide and p-type tin monoxide to achieve J-K flip-flop (JK-FF) and D-type edge-triggered

In this study, we propose a polysilicon (poly-Si) channel thin-film synaptic transistor based on an organic-inorganic hybrid electric-double-layer (EDL) structured gate dielectric. To implement the hybrid EDLs, which play a key role in artificial synaptic transistors, a protonic mobile ion-based bio-inspired chitosan electrolyte and a high- ${k}$ Ta 2 O 5 dielectric thin-film were applied. Synaptic

Two-dimensional (2D) materials with anisotropic electronic structures possess promising prospect for ultra-scaled field effect transistors (FETs), such as black phosphorene. Here, the quantum transport properties of anisotropic 2D group VA-VA monolayers with puckered configuration are studied in 5 nm FETs using density functional theory and nonequilibrium Green’s function. Through evaluating and comparing

A SrSnO 3 high-frequency field-effect transistor (FET) is demonstrated. The device structure consists of a recessed Schottky-gate FET with a heavily doped cap layer. DC measurements on devices with 0.5- $\mu \text{m}$ gate length and 4- $\mu \text{m}$ source/drain spacing show a maximum drain current of 53 mA/mm and a maximum transconductance of 43.2 mS/mm. Radio frequency (RF) characterization reveals

In this work, we demonstrate CMOS integration that is fully compatible with a commercial double-implanted MOS (DMOS) process in 4H-SiC without requiring additional masks and cost. The characteristics of the NMOS, the PMOS, the CMOS inverter, and the ring oscillators are measured up to 175 °C. Propagation delay is reduced from 117 ns at room temperature to 17.8 ns at 175 °C, thanks to the increased

In this letter, we present a new concept for normally-off AlGaN/GaN-on-Si MOS-HEMTs based on the combination of p-GaN, tri-gate and MOS structures to achieve high threshold voltage ( ${V}_{\text {TH}}$ ) and low on-resistance ( ${R}_{ {ON}}$ ). The p-GaN is used to engineer the band structure and reduce the carrier density ( ${N}_{\text {s}}$ ) in the tri-gate structure for a high ${V}_{\text {TH}}$

Multi-channel power devices, in which several AlGaN/GaN layers are stacked to achieve multiple two-dimensional electron gases (2DEGs), have recently led to a significant increase in the device conductivity while maintaining high breakdown voltage, resulting in excellent DC performances. However, their dynamic performance is yet to be demonstrated, especially due to the absence of an effective passivation

In this work, we explore the output-conductance function (G-function) to interpret the device characteristics of two-dimensional (2D) semiconductor transistors. Based on analysis of the device output conductance, the carrier mobility, and the channel as well as contact resistance are extracted. Thereafter the current-voltage (IV) characteristics of black phosphorous (BP) and MoS 2 transistors from

The tri-gate MOSFET is a vertical power transistor with multiple sub-micron FinFET channels. The FinFET structure increases the current-carrying width of the MOS inversion layer without increasing the device area, thereby reducing the specific channel resistance. This is especially useful in silicon carbide where the inversion layer mobility is $\sim 10\times $ lower than in silicon. This innovation

The input/output microwave circuit of a W-band gyrotron traveling-wave tube (gyro-TWT) with a predicted output pulse power of more than 300 kW and a bandwidth of about 8% is under investigation. A distinctive feature of this circuit is the transverse (relative to the axial velocity of the electrons in the gyro-TWT) extraction of the output power and its compatibility for feeding and coupling the microwaves

Compressed sensing with a tunable random sampling strategy has great potential in reducing the energy/time consumption during the constant acquisition of external information, thereby it is considered one of the most promising sensing strategies in edge-terminal. In this letter, a novel tunable stochastic oscillator (TSO) based on the VO 2 /TaO x structure was proposed and employed as the core controlling

Memristor based neuromorphic computing system has recently attracted enormous attention due to its fast and energy-efficient matrix vector multiplication, thus providing a novel approach to implement neural networks for artificial intelligence. However, the widely studied analogue memristors exhibit major flaws in terms of high conductance variation and nonlinear/asymmetric characteristics. In this

Process and parametric variation negatively impact the performance and yield of analog and digital circuits in advanced nodes. To alleviate this effect, we propose a technique to electrically adjust the threshold voltage of CMOS transistors in a post-fabrication setting in a non-volatile manner. This technique, which relies on self-heating assisted trapping of charge in high-k gate dielectric (e.g

A millimeter-wave passive-integrated bandstop filter (BSF) with absorptive/reflectionless behavior is reported. It avoids the creation of RF-power reflections for filtered signals which can deteriorate earlier active stages in integrated RF front-end chains. It exploits a two-path transversal configuration in a multi-layer structure. Specifically, it is composed of a direct transmission line for the

Conduction mechanisms of ferroelectric tunnel junction (FTJ) using metal-ferroelectric-insulator- semiconductor (MFIS) on n- and p-type semiconductor is clarified by a new developed model, which is verified by the experimental results. In the model, electron tunneling from conduction band and valence band, and hole tunneling from valence band are included to calculate the read current in ON/OFF-state

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PProf. Edmundo A. Gutiérrez D., having served as an Editor for IEEE Electron Device Letters since 2011, has completed his tenure. On behalf of IEEE Electron Device Letters staff and readers, I would like to thank him for his excellent contribution and dedicated service to the journal over the past nine years.

It is my pleasure to welcome Prof. Pedro Barquinha to the Editorial Board of IEEE ELECTRON DEVICE LETTERS. A biography and sketch of Prof. Barquinha’s research interests can be found below. His subject area is thin-film transistors.

It is my pleasure to welcome Prof. Annalisa Bonfiglio to the Editorial Board of IEEE ELECTRON DEVICE LETTERS. A biography and sketch of Prof. Bonfiglio’s research interests can be found below. Her subject areas are molecular and organic devices, sensors and actuators, and thin-film transistors.

IEEE Electron Device Letters is one of the most selective rapid publication venues within the field of electron devices. Our goal is to rapidly publish strictly novel research results that are also highly relevant. Accomplishing this goal would not be possible without the strong support of the technical professionals—authors and reviewers from academic, industrial, and government institutions worldwide—who

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The thermal sensitivity and Low Frequency Noise (LFN) of compensation doped Silicon-On-Insulator (SOI) resistors are studied experimentally, down to the cryogenic regime. A high compensation nominal ratio ${K}={N}_{A}/{N}_{D}$ of 0.82 is compared with uncompensated and partially compensated configurations, using Phosphorus and Boron as dopant species. The Temperature Coefficient of Resistance (TCR)

Gate-All-Around Field Effect Transistors (GAAFETs) for the future technology nodes will have highly confined channel cross-sections. Effects like subband separation and geometry dependent density of states result in kinks, peaks and valleys appearing in terminal characteristics like capacitance and transconductance. This has significant effect on the circuit linearity performance, in analog and RF

Substrate ramps and stepped stress transient measurements are applied to study vertical charge transport mechanisms in GaN-on-Si power HEMTs. By choosing appropriate bias points for substrate stress it is possible to single out the dominant charge transport mechanism: at low negative biases transport through carbon-doped GaN manifests itself in negative (decreasing) current transients with apparent

This letter reports an experimental demonstration of charge-balanced GaN super-heterojunction Schottky barrier diodes (SHJ-SBDs). Charge balance between the n-type delta-doping and the p-type doping was achieved by adjusting the thickness of the pGaN. This device structure enabled scaling of breakdown voltage to over 3 kV, and dynamic switching up to 2.8 kV without using any field-plate.

Increasing demands for new computer architectures may require embedded non-volatile memories as for example in-memory computing. Ferroelectric field-effect transistors (FeFETs) add further advantages besides their outstanding properties due to the availability of both n-type and p-type transistors. The latter favor a different channel materials, like SiGe, due to the low hole mobility in silicon. In

Operation characteristics of polycrystalline germanium (poly-Ge) tri-gate junctionless (JL) charge-trapping (CT) flash memory devices with stacked tunneling layer were studied in this work. The programming speeds of poly-Ge tri-gate JL flash device with GeO x /Al 2 O 3 /SiO 2 tunneling layer are faster than those with GeO x /Al 2 O 3 or GeO x /SiO 2 ones, thanks to the modified electric field in the

Time statistics for successive breakdown (BD) events in Al 2 O 3 /HfO 2 -based nanolaminates aimed to the development of multilevel one-time programmable (OTP) memory cells is investigated. The clustering model is shown to account for the departure of the experimental data from the standard Weibull model attributed to the initial leakage current dispersion. An equivalent electrical circuit model is

Ferroelectric switching was studied in 20 nm thick Al 0.68 Sc 0.32 N and Al 0.64 Sc 0.36 N films (with ~4 nm surface oxides) on platinized silicon wafers by multiple electrical characterization methods. Positive up negative down (PUND) measurements were conducted using 100 $\mu \text{s}$ monopolar triangular waveform excitation. At room temperature, Al 0.68 Sc 0.32 N exhibited an apparent remanent

An extraction technique for flat band voltage ( ${V}_{\textit {FB}}$ ) in an amorphous InGaZnO (a-IGZO) thin-film transistor (TFT) using the frequency-independent ${C}-{V}$ relationship which is taken from the measured multi-frequency ${C}-{V}$ characteristics, is proposed. The proposed method comprises the consideration of multiple physical parameters for accurate ${V}_{\textit {FB}}$ extraction,

We report the effect of N 2 O post-fabrication annealing (PFA) on the electrical stability of dual gate, active split amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT). Optimized N 2 O PFA at 360 °C for 3 h results in threshold voltage (V TH ) close to zero and an increase in the on-current almost 2 times than as-fabricated TFT. N 2 O annealed TFT exhibited robust V TH stability