显示样式： 排序： IF:  GO 导出

CMOS realization of OTA based tunable grounded meminductor Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210326
Anamika Raj, Keshab Kumar, Pankaj KumarA simple and robust design for CMOS realization of a tunable grounded meminductor using three operational transconductance amplifier (OTA) and two capacitors have been proposed. Both theoretical analyses and simulation using Cadence Virtuoso at 0.18 \(\upmu {m}\) CMOS technology parameters verify the validity of the meminductor. Its meminductance can be tuned with the help of external bias voltage

CMOS level shifters from 0 to 18 V output Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210403
Joel Gak, Matias Miguez, Alfredo ArnaudA design methodology for level shifters voltage translators, where the output voltage ranges from 0 to 18 V, and the input voltage ranges from 2 to 5.5 V in a 0.6 µm CMOSHV technology, is presented. This family of circuits have a special interest in the case of implantable medical devices where is common to handle previously unknown voltages either positive or negative, above or below the control

A ring oscillator with very low phase noise and wide frequency range using carbon nanotube technology for PLL applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210324
Hamed Sarbazi, Reza SabbaghiNadooshan, Alireza HassanzadehThis paper presents a wide frequency range threestage voltagecontrolled ring oscillator in CNTFET technology. The advantages of CNTFETs are the high speed of charge carriers, high signal to noise ratio, small size and ballistic transport. Therefore in comparison with MOSFETs, they have a higher frequency, and can operate at a wide frequency range with a very low phase noise if forward bulk bias and

A 8–12 GHz, 44.3 dBm RF output class FF −1 DPA using quadmode coupled technique for new configurable frontend 5G transmitters Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210323
Rajesh Kumar, Santanu Dwari, Binod Kumar Kanaujia, Sandeep Kumar, Hanjung SongThis paper presents a highefficiency Class \({\mathrm{FF}}^{1}\) DPA using the quadmode coupled technique for new configurable frontend 5G transmitters. The proposed DPA consists of carrier PA, main PA, input–output matching network and hybrid power network (HPN). The HPN includes a quadmode coupled technique which is foursection Ushaped transmission line. The HPN is used for even–odd mode impedance

Design analysis of GOSHEFET on lower Subthreshold Swing SOI Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210321
B. V. V. Satyanarayana, M. Durga PrakashDue to various kind of BandToBand Tunneling (BTBT) operation, Heterojunction Tunnel Field Effect Transistors (HEFETs) are widely used in ultralow power applications. Anyhow, circuit complexity is a major issue in case of HEFET based memory development because of their uncomfortable size. Device scaling is a better way to eliminate such kind of issues for HEFET based memory development. Thus, development

New floating/grounded FDNC and nonideal grounded FDNR simulators based on VDTA Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210320
Predrag B. PetrovićThe paper proposes a new grounded/floating frequency dependent negative conductance (FDNC) simulator, and a nonideal frequency dependent negative resistance (FDNR) simulator, based on deployment of voltage differencing transconductance amplifiers (VDTA), along with two grounded capacitances. The presented simulators feature electronic controllability of realized negative conductance/resistance via

A 125 GHz millimeterwave phase lock loop with improved VCO and injectionlocked frequency divider in 65 nm CMOS process Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210319
Shilan Neda, Ghader Yosefi, Abdollah EskandarianIn this paper, a CMOS mmwave phase locked loop (PLL) with improved voltage controlled oscillator (VCO) and injectionlocked frequency divider (ILFD) at operational harmonic frequency 125 GHz is presented. The VCO structure uses the bulk effective and MOS varactor capacitor to adjust parasitic capacitor of the cross coupled pair. It obtains 2th harmonic frequency with 24% tuning range (110–140 GHz)

Third order quadrature oscillator and its application using CDBA Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210317
Mourina Ghosh, Shekhar Suman Borah, Ankur Singh, Ashish RanjanThis research article comes with three novel topologies of Voltage Mode (VM) third order Quadrature Sinusoidal Oscillators (QSOs) using Current Differencing Buffered Amplifier (CDBA) as an active device with grounded and virtually grounded passive components. An implementation perspective of the prototype circuits follows a specific class of filter specifically Low pass (LP), High pass (HP) and All

A dualinput extendeddynamicPCE rectifier for dedicated farfield RF energy harvesting systems Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210313
Chee Ming Poo, Gabriel Chong, Harikrishnan RamiahThis paper presents a dualinput extendeddynamicrange, highPCE rectifier for dedicated farfield RF energy harvesting systems. Two identical input RF energy supply source are applied into two individual rectifier. The rectifier with the highest PCE is selected to deliver dc power to a singleload element. A logic control circuit senses Pin from the rectified dc voltage and toggles between the rectifiers

Design of low power singlestage bias current control technique based DVGA for LTE receivers Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210311
Sawssen Lahiani, Houda Daoud, Samir Ben Salem, Rahma Aloulou, Mourad LoulouIn this study, a novel singlestage Digital Variable Gain Amplifier architecture (DVGA) was presented for Long Time Evolution (LTE) receivers. The proposed DVGA combines two transimpedance amplifiers, a transconductance amplifier and a novel digitally controlled current. Using a digital control block, an auxiliary pair to retain a constant current density enabled changing the gain. The Heuristic Method

Highperformance classE power amplifier integrated with a microstrip bandpassfilter for wireless applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210311
Behnam Afzali, Farzin Shama, Hamed AbbasiIn this paper, a classE power amplifier using a harmonic control network consisting of a bandpass filter and a harmonic control circuit is presented. The advantage of using the bandpass filter in the harmonic control network is the elimination of the DCblock capacitor between the transistor and the load. As a result, losses due to this capacitor are eliminated at operating frequencies. In this design

Analog circuit implementation based on median filter for salt and pepper noise reduction in image Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210310
Melih YildirimIn this study, an analog circuit design instead of using a software is utilized to remove Salt and Pepper (S&P) noise in image. For this purpose, a digital image filtering method which is called median filter is carried out. In median filter method, a currentmode nineinput oneoutput circuit architecture is preferred since 3 × 3 filtering mask is employed. Median filter circuit is based on a modified

A 34.3 dB SNDR, 2.3GS/s, Subradix pipeline ADC using incomplete settling technique with background radix detector Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210309
HsinShu Chen, ChienJian Tseng, ChengMing Chen, HsiangWen ChenA 6bit 2.3 GS/s singlechannel subradix pipeline ADC using an incomplete settling concept is presented. A radix detector is proposed to detect stage gain in the background so that low gain and low bandwidth opamps can be utilized to conserve power. The raw ADC output codes can be reconstructed with the detected radix to retrieve its accuracy. The simulated results show that the prototype ADC in 40 nm

Designing series of fractionalorder elements Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210308
Jaroslav Koton, Jan Dvorak, David Kubanek, Norbert HerencsarIn this paper we propose an efficient approach to design fractionalorder elements’ (FOEs) series, while using a very limited set of “seed” FOEs. The proposed approach follows the idea of general immittance inverter/converter, whereas a suitable circuit solution employing operational transconductance amplifiers is also presented and can be used for the design of grounded FOEs with the fractional order

A wideband monobit digital receiver circuit using InP/CMOS 3D heterogeneous integration Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210305
Youtao Zhang, Yang Wang, Xiaopeng Li, Lishu Wu, Wei Cheng, Min Zhang, Yi ZhangA monobit digital receiver circuit for instantaneous frequency measurement is presented. The circuit is codesigned with Indium Phosphide Double Heterojunction Bipolar Transistor and complementary metal oxide semiconductor (CMOS) devices. The chip is fabricated by InP/CMOS threedimensional (3D) heterogeneous integration using the waferlevel bonding technique. The measurable signal frequency within + 15

A circuitlevel inverterbased switched capacitor integrator model justified by postlayout simulations of an incremental sigmadelta converter Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210305
Li Huang, Caroline LelandaisPerrault, Anthony Kolar, Philippe BénabèsThis paper proposes a circuitlevel model of an inverterbased switchedcapacitor (SC) integrator involved in a previously published incremental sigmadelta analogtodigital converter (I\(\Sigma {\Delta }\) ADC) to explain the ADC resolution degradation observed in the postlayout simulation. A fine analysis of postlayout signals led to a new model of the integrator with parasitic capacitors. Then

Analysis of stepwise charging limits and its implementation for efficiency improvement in switched capacitor DC–DC converters Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210304
Francisco Veirano, Pablo Castro Lisboa, Pablo PérezNicoli, Lirida Naviner, Fernando SilveiraIn this work we analysed the stepwise charging technique to find the limits from which it is beneficial in terms of load capacitance and charge–discharge frequency. We included in the analysis practical limitations such as the consumption of auxiliary logic needed to implement the technique and the minimum size of auxiliary switches imposed by the technology. We proposed an ultralowpower logic block

A DTMOSbased power efficient recycling folded cascode operational transconductance amplifier Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210226
Amitkumar S. Khade, Sandeep Musale, Ravikant Suryawanshi, Vibha VyasThe focus of the present study is on a recycling folded cascode (RFC) operational transconductance amplifier (OTA) in which the transconductance, as well as the slew rate of OTA, are enhanced. RFC OTA, proposed in this study, is employed using a Dynamic Threshold Voltage MOSFET (DTMOS) based differential pair with class AB operation. To achieve class AB operation, an adaptive biasing technique comprising

An ultralow power highprecision logarithmiccurvature compensated allCMOS voltage reference in 65 nm CMOS Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210225
Tayebeh Ghanavati Nejad, Ebrahim Farshidi, Henrik Sjöland, Abdolnabi KosarianIn this paper, a lowcomplexity resistorless highprecision sub1 V MOSFETonly voltage reference is presented. To obtain an accurate output, a curvaturecompensation technique is used, canceling its logarithmic temperature dependence regardless of the value of the mobility temperature exponent \((\gamma )\). The circuit is realized in 65 nm CMOS technology and yields an output voltage of 574 mV, a

Design and verification of a high performance analog switch circuit Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210224
Lin Zhang, Jieyu Li, Yang Wang, Jianxiu Hao, Xiangliang Jin, Yan Peng, Jun LuoA doublepole doublethrow analog switch circuit structure with low power consumption, low onresistance and capable of transmitting negative signals is designed in this paper, which has been developed in 0.18 μm BCD technology. The analog switch circuit is providing about 5 V high swing signal transmission for 2.7–5 V supply voltage in the temperature range of − 40 to 85 °C. The shortcomings of traditional

High energyefficient switching scheme for SAR ADC with low commonmode level variation Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210222
Xinyu Li, Jueping Cai, Xin Xin, Tengteng Chen, Zhen LiThis letter presents a novel high energyefficient switching scheme with low commonmode level variation for successive approximation register (SAR) analogtodigital converters. Benefit from the merge capacitor split and C2C techniques, the proposed switching scheme achieves 98% saving in switching energy and 86.91% reduction in capacitor area over the conventional scheme without reset energy. Compared

Concurrent design of Schottky diode limiter and LNA Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210217
Seyed Hossein Alavi Lavasani, Ali MediIn this paper concurrent design of Schottky diode based limiter and low noise amplifier (LNA), based on noise matching, is investigated to achieve minimum noise figure (NF) of the receiver chain. In design procedure of the LNA, the noise figure is minimum, gain at central frequency is 14.5 dB, and limiter structure tolerates up to 5 W continuous wave input power. In the proposed concurrent design,

Power efficiency enhancement analysis of an inverse class D power amplifier for NBIoT applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210217
Mehrdad HarifiMood, Abolfazl Bijari, Hossein Alizadeh, Mehdi Forouzanfar, Nabeeh KandalaftThe power amplifiers (PAs) are generally the most powerconsuming building blocks in Radio Frequency (RF) transceivers. This paper presents a high efficiency fully integrated inverse class D power amplifier for the narrowband Internet of Things (NBIoT) applications. In this design, the PA's power added efficiency (PAE) is improved by inserting two auxiliary PMOS transistors into the conventional topology

Miniaturized uniplanar CSRR based quadband antennaanalysis and investigation Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210215
Mahmoud A. Abdalla, Walaa W. Wahba, Hesham Elreagaily, Abdelmegeed Allam, Zhirun HuThis paper presents the detailed design, analysis and measurements of new configuration of quadband antenna. The antenna is designed using a new uniplanar complementary split ring resonator (UPCSRR) unit cell. The UPCSRR unit cell is etched in the top plane of a microstrip patch which reduces the back radiation and enhances the antenna efficiency. The structure has advantage of the presence of

An automated classification of EEG signals based on spectrogram and CNN for epilepsy diagnosis Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210215
Badreddine Mandhouj, Mohamed Ali Cherni, Mounir SayadiEpilepsy disease is one of the most prevalent neurological disorders caused by malfunction of large symptoms number of neurons. That’s lead us to propose an automated approach to classify Electroencephalography (EEG) signals of the aforementioned pathology. To realize an efficient seizures detection the output of our classification is divided into three classes; normal, preictal and ictal class. In

Design and implementation of couplerbased Kaband CMOS power splitters Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210211
YoSheng Lin, BingTing Yeh, KaiSiang LanWe propose a novel power splitter (or divider) comprising two backtoback quarterwavelength (λ/4) coupled lines (i.e. coupler). To improve the isolation between the output ports (i.e. ports 2 and 3), an isolation resistor R is included. Three power dividers are designed and implemented. To enhance the reflection coefficients, and S21 and S31 and their amplitude imbalance (AI) and phase difference

Transimpedance type MOSC bandpass analog filter core circuits Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210210
Ismail Cevik, Bilgin Metin, Norbert Herencsar, Oguzhan Cicekoglu, H. Hakan KuntmanIn this paper, we present six areaefficient transimpedance type secondorder analog filters. There are many applications where the available signal is current, however the necessary signal for further processing is voltage type. For such applications the presented circuits will be a useful solution. The technique employed is called MOSonly technique and to the best of our knowledge this is the first

Topology Variations of an Amplifierbased MOS Analog Neural Network Implementation and Weights Optimization Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210205
Tiago Oliveira Weber, Fabián Leonardo Cabrera, Diogo da Silva LabresNeural networks are achieving stateoftheart performance in many applications, from speech recognition to computer vision. A neuron in a multilayer network needs to multiply each input by its weight, sum the results and perform an activation function. This paper is an extended version of the article in which we present an implementation of an amplifierbased MOS analog neuron and the optimization

Design and experimentation of VDTA based oscillators using commercially available integrated circuits Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210202
Soumya Gupta, Tajinder Singh AroraWith the focus of employing single Voltage Differencing Transconductance Amplifier (VDTA) in designing of electronically tunable oscillators, three configurations have been proposed in this manuscript. Each configuration enjoys an efficient integrated circuit implementation due to use of grounded capacitors. Unambiguous and independent control of its condition and frequency of oscillation is an additional

Chaos suppression for a Buck converter with the memristive load Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210202
Baiming Zhu, Qiuhua Fan, Guoqiang Li, Dongqing WangThe memristor is a nonlinear device with a particular memory function and is widely used in various circuit researches. This work studies the peak current mode controlled (PCMC) buck converter with the memristive load at the continuous current mode (CCM). Firstly, a state equation for a buck converter with the memristive load is derived and a generic voltagecontrolled memristor simulator is constructed

A novel Zsource boost derived hybrid converter for PV applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210125
S. Jeyasudha, B. Geethalakshmi, Krishnan Saravanan, Raghvendra Kumar, Le Hoang Son, Hoang Viet LongThis paper proposes a novel Zsource boost derived hybrid converter (ZSBDHC) that produces high gain dual output from a single DC input, which is the choice of a solar photovoltaic system. This has multiple advantages as lesser count of switches, high power processing capability and high reliability result in reduction of overall cost. Besides, the prime advantage of this topology is achieving high

A novel tunable bandgap voltage and current reference generation circuit Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210123
H. Prem Sai Kumar, Vivek Sharma, Y. B. Nithin Kumar, M. H. VasanthaThis paper presents a CMOS based tunable bandgap voltage and current reference generation circuit. The proposed circuit is designed without using Bipolar Junction Transistors (BJTs) for ProportionalToAbsoluteTemperature and ComplementaryToAbsoluteTemperature generation, thus eliminating the problem of implementing BJT in CMOS fabrication process. The proposed circuit is simulated in standard

Neuristor based electronically controllable logic gates Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210122
Yunus Babacan, Firat KacarThis paper presents electronically controllable neuron circuitneuristor based logic OR and AND gates using the same circuit topology. Here, only four neuristors are used to obtain both OR and AND gates which have three inputs and one output. The proposed circuit is electronically controllable and can be used as an OR or AND gate by changing only one voltage source without changing any circuit topology

A 36.7 mW, 28 GHz receiver frontend using 40 nm RFCMOS technology with improved Figure of Merit Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210120
Ankita Verma, Pritesh Kumar Yadav, Sunanda Ambulker, Manish Goswami, Prasanna Kumar MisraHigh carrier frequency requirement (Sub 6, 28 GHz) to accomplish the high bandwidth specification for millimeter wave band wireless communication, has reduced the ratio of operating carrier frequency (fc) and unity current gain frequency (ft) of MOSFETs in state of the art RFCMOS technology. This poses a challenge for designing a high gain and low noise receiver with better linearity. In an attempt

A 15.5xgain 0.29mm 2 CMOS readout circuit for 1.5Mpixel 60fps CMOS image sensor Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210118
Ming Chen, Li Zhou, YangJun Yang, Chengbin Zhang, Kunyu Wang, Cen Gao, Wenjing Xu, Jie ChenAn analog signal processing (ASP) circuit used for CMOS image sensor (CIS) readout is presented. The proposed ASP mainly includes a twostage programmable gain amplifier (PGA), a sampleandhold amplifier (SHA) merged by a pipelined analog–digital converter (ADC), and a digitalanalog converter (DAC). Compared with conventional readout architecture, the proposed can provide finer gain, level shifting

A compact multipleinput multipleoutput antenna with high isolation for wireless applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210116
Heba Aboelleil, Ahmed A. Ibrahim, Ashraf A. M. KhalafThis paper presents a highperformance multipleinput multipleoutput (MIMO) antenna with a compact size of 42 × 42 mm2. The proposed antenna operates in the frequency range of 3.2–12 GHz for ultra wide band (UWB) wireless communication systems. The proposed MIMO antenna has four identical elements arranged to be orthogonal to each other to achieve a good performance. To achieve high isolation, stubs

Design of digital pulse width modulator architecture with digital PID controller for DCDC converter using FPGA Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210111
Venkutuswamy Radhika, Karuppanan Srinivasan, Bella Bellie Sharmila, Venkatasalam RukkumaniA digital pulse width modulation architecture (DPWM) along with digital proportional integral derivative (PID) controller to control the DCDC converter is presented in this paper. Difference between the actual output voltage and the reference voltage is calculated as error value. The look up table is created for PID controller to store the duty cycle ratio and the error value of power converters.

Design and implementation of modified BCD digit multiplier for digitbydigit decimal multiplier Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210111
Parthibaraj Anguraj, Thiruvenkadam KrishnanDecimal multiplication is the most common operation in arithmetic applications. This paper presents an areaefficient digitbydigit decimal multiplier using a modified binarycoded decimal digit multiplier. In general, a BinaryCoded Decimal (BCD) digit multiplier consists of two kinds of block, namely binary multiplier, and Partial Product BinarytoDecimal (PPBD) converter. In the BCD digit multiplier

Low power and writeenhancement RHBD 12T SRAM cell for aerospace applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Govind Prasad, Bipin Chandra Mandi, Maifuz AliIn aerospace applications, the conventional Static Random Access Memories (SRAMs) are facing high soft error problems like a single event upset. Several radiationhardened based design (RHBD) like twelvetransistor (12T) Dice, 12T WeQuatro SRAM cells, etc., had been developed to address the soft error problems. But they all are consuming comparatively more total and static power with more delay and

A simple and effective feedback structure for variableQ filter design Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Arman Kheirati Roonizi, Hossein PakniatThis paper proposes a simple and effective feedback structure to implement the variableQ bandpass filter. An effective variableQ bandpass filter can be designed by using integralplusderivative in the feedback pass. The stability of the model is shown in both continuous and discretetime systems. Also, we demonstrate that the model could indeed achieve the desired center frequency as a precise

MSBsplit VCMbased charge recovery symmetrical switching with setanddown asymmetrical switching method for dualcapacitive arrays SAR ADC Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Yewangqing Lu, Ting Zhou, Jiajie Huang, Lulu Wang, Mingyi Chen, Yongfu LiWith the advanced development of CMOS manufacturing process, the capacitivearray in the successive approximation register analogtodigital converters (SAR ADCs) has become the dominant source of energy consumption and silicon area. This requires an immediate attention to design a more energyefficient capacitive switching method while maintaining excellent linearity and noise rejection. A hybrid

An original determination of the maximum phase shift range obtained for an array of N coupled oscillators Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Kaouthar Djemel, Rahma Aloulou, David Cordeau, Hassene Mnif, JeanMarie Paillot, Dorra Mellouli, Mourad LoulouThis paper presents an original approach, using a harmonic balance optimization method, allowing to predict the maximum phase shift range that can be practically obtained for an array of N coupled oscillators. Indeed, unlike what is predicted by the theory, the proposed analysis allows to show that the maximum value of the phase shift decreases by increasing the number N of coupled oscillators in the

Fast SHVC intra prediction mode decision implementation Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Taheni Damak, Ibtissem Wali, Amina Kessentini, Mohamed Ali Ben Ayed, Nouri MasmoudiThe Scalable extension of the High Efficiency Video Coding standard (SHVC) combines the large compression efficiency and high visual quality of HEVC with the possibility of encoding several different versions of the same encoded video in a single bitstream. However, this comes at the cost of a high computational complexity. In order to reduce the SHVC encoding time, an intraprediction mode decision

Energyefficient switching scheme for SAR ADCs using two reference levels Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Junhui Li, Linlin Huang, Lizhen Zhang, Xin Li, Jianhui WuA highly energyefficient capacitor switching scheme for successive approximation register (SAR) analogtodigital converters (ADCs) is proposed. The proposed switching scheme needs only two reference levels by using the mergeandsplit technique, which eliminates the need of the extra reference voltage (Vcm). The switching procedure is performed on the simple binary weighted capacitor arrays without

Design and simulation of fourth order lowpass GmC filter with novel autotuning circuit in 90 nm CMOS Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Mohammad Abdolmaleki, Massoud Dousti, Mohammad Bagher TavakoliA tunable highfrequency operational transconductance amplifier (OTA) is presented along with its application in the implementation of a GmC filter. The OTA is tuned by varying the negative resistance produced by a positive feedback at the output. Postlayout simulation results (using TSMC 90 nm CMOS technology and a 1V supply voltage) show that the differential DC gain, commonmode gain and OTA

A high linearity low power lownoise amplifier designed for ultrawideband receivers Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Behnam Dorostkar Yaghouti, Javad YavandhasaniThis paper presents a new ultrawide band (UWB) CMOS low noise amplifier (LNA) with very high linearity and low power consumption for UWB wireless communication applications, where linearity is a big challenge, due to presence of interference and blocker signals, as well as the inband harmonics of the desired signal components in the lower part of UWB band. The proposed LNA uses a new combination

Correlationbased reconfigurable blind calibration for timing mismatches in TIADCs Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Chengxuan Zhao, Jietao Diao, Hui Xu, Yinan WangMismatches between subchannels limit the dynamic performance of timeinterleaved analogtodigital converters (TIADCs). This paper proposes a correlationbased method of calibration for timing mismatches in Mchannel TIADCs by using the crosscorrelation between subchannels of the output signals to estimate the temporal deviations. The output signal is calibrated by reducing the arbitrary order

A threestage NMC operational amplifier with enhanced slew rate for switchedcapacitor circuits Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Farshad Alizadeh Arand, Mohammad YavariThis paper presents a new architecture for threestage operational transconductance amplifiers (OTAs) with a class AB input stage to improve the slew rate. The nested Miller compensation scheme is utilized to stabilize the proposed OTA. A nonlinear current mirror in the firststage is used to implement the class AB operation. Details of the proposed OTA are described and the circuit level simulation

Design and analysis of reconfigurable fractal antenna with RFswitches on a flexible substrate for Xband applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210104
Bokkisam Venkata Sai Sailaja, Ketavath Kumar NaikThis paper presents a compact reconfigurable elliptical shaped fractal patch (ESFP) antenna with elliptical shaped RF MEMS switch is used for satellite applications at Xband. The proposed work involves the incorporation of RF MEMS switches loaded using parasitic elements with ease of simpler implementation without using DC bias lines. The proposed antenna is integrated with two MEMS switches and reconfigurability

Source injection coupled quadrature oscillator: transient oscillation amplitude and thermally induced phase noise Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210103
Hengameh Azizi, Soolmaz Abbasalizadeh, Hossein MiarNaimiThis paper analyzes the transient oscillation amplitude of the source injection coupled quadrature oscillator (SICQOSC). With the help of the Describing Function Method, we estimate an expression to describe the nonlinear behavior of the negative transconductor. Using the estimated expression, we obtain an accurate closedform formula for the timedomain amplitude of the SICQOSC. The proposed formula

An efficient, scalable, regular clocking scheme based on quantum dot cellular automata Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210103
Jayanta Pal, Amit Kumar Pramanik, Jyotirmoy Sil Sharma, Apu Kumar Saha, Bibhash SenThe present CMOS VLSI technology is facing some challenges like working in nano scale, device density, power dissipation, operating frequency, fast execution, which demands a proper alternative. Quantum dot Cellular Automata (QCA) is one of the feasible substitutes for the same. In QCA, clocking is the primary driving source of power, and the flow of information occurs with the effect of underlying

Performance analysis for reliable nanoscaled FinFET logic circuits Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210103
Umayia Mushtaq, Vijay Kumar SharmaIn the process of continuous miniaturization of devices, it is necessary to look for new devices which overcome the drawbacks of nonscalability and higher static power of metal oxide semiconductor field effect transistor (MOSFET). Finshaped field effect transistor (FinFET) is an important device which uses the concept of multigates and it is not only scalable but also dissipate lower power at lower

Efficient design of dual controlled stacked SRAM cell Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210103
D. Satyaraj, V. BhanumathiIn low power VLSI circuit designs, power dissipation is one of the challenging issues which is associated with threshold voltage. The reduction of threshold voltage increases the subthreshold leakage current by increasing the leakage power dissipation which plays an important role in total power dissipation. Due to this leakage power issue, the devices which are operated by battery for a long time

On the performance of massive MIMO twoway relaying systems using double precision technique Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210103
Sahar Said, Waleed Saad, Mona Shokair, Sayed ElArabyThe practical application for massive MIMO relaying system with a large number of antennas is considered a challenging problem. To solve this problem, a promising solution is to utilize double precision analogtodigital converter (ADC) and digitaltoanalog converter (DAC) at the relay. Depending on the additive quantization noise model, closedform expression for system sum rate is analyzed. Furthermore

A study of phase noise suppression in reference multiple digital PLL without DLLs Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210103
Takahiro Kato, Akira YasudaIn order to suppress the spurious signal resulted from the reference leak and to decrease the oscillator jitter by using phase locked loop (PLL) loop band extension, a reference frequency multiplier that places a delay locked loop (DLL) in front of the PLL has been studied. However, a feedback circuit such as a DLL or an injection locked type voltage controlled oscillator must be used. In this paper

A gain reconfigurable time difference amplifier with selfadaptive linearity control Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210103
Jinhao Li, Jianfei Jiang, Qin Wang, Naifeng Jing, Weiguang Sheng, Guanghui HeTime difference amplifier (TDA) is often used in time domain interconnection, computing and measurement. Gain and linearity control are two main design issues. To reduce the nonlinear distortion, a novel selfadaptive pulse shrink circuit is proposed for the SRlatch based time difference amplifier. The multistage selfadaptive pulse shrink unit can compensate for the gain error caused by the highorder

Chaotic flower pollination algorithm based optimal PID controller design for a buck converter Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
Murat Erhan Çimen, Zeynep B. Garip, Ali Fuat BozThis paper presents a solution based on optimal PID coefficients including antiwind up for buck converter presents using metaheuristic algorithm and chaos theory. A hybrid algorithm is called chaotic based flower pollination algorithm is provided by combining flower pollination algorithm and chaos theory with different maps. Five different choatic maps are used in the aim of increasing the efficacy

ENGTL based antenna for WiFi and 5G Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
Suman NelaturiThis article reported patch antenna functioning at Wi Fi and 5G bands. WiFi band (2.4 GHz) is obtained by loading Epsilon Negative Transmission Line (ENGTL) metamaterials into the patch radiating at 5G band (3.5 GHz). To acquire Circular Polarization (CP) at 5G band, conventional square patch is embedded with poly fractals. The experimental and simulated data are in close proximity. The obtained

Design of Npath notch filter circuit with switchedcapacitor resistor Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
Khilda Afifah, Nicodimus RetdianHum noise such as power line interference is one of the critical problems in biomedical signal acquisition. Various techniques have been proposed to suppress power line interference, such as an Npath notch filter. The notch depth in the conventional Npath notch filter is limited by the number of paths. The previous 10phase Npath notch filter circuit achieved deeper notch depth but has a problem

Design of phase frequency detector with improved output characteristics operating in the range of 1.25 MHz–3.8 GHz Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
Nigidita Pradhan, Sanjay Kumar JanaIn this paper, a CMOS based precharged phase frequency detector (PPFD) with improved output characteristic for phase locked loop (PLL) has been proposed and analyzed. The proposed PFD minimizes the reset time to improve the output characteristics and works upto the frequency of 1.25 MHz–3.8 GHz. In addition, it has an advantage of precharged PFD which has low power consumption capability i.e., 285