In this article, a Schmitt trigger based 12-Transistors(ST12T) static random-access memory (SRAM) bit-cell has been proposed. The Read Power of proposed cell is reduced by 29.17%/ 24.14% /7.66% /5.87% /7.67% /16.62% when compared to 6T/ 7T/ TA8T/ 9T/ PPN10T/ D2p11T SRAM cells. Proposed ST12T cell also shows 1.52\(\times\) and 1.86\(\times\) lesser variability in read current and read power respectively

In this study, a low-dropout voltage regulator (LDO) system composed of two LDOs, which can operate in the temperature range of 77–400 K, has been developed. Cryogenic and typical transistor models of the 180 nm UMC CMOS process have been employed in the design process. Both LDOs can provide a load current of 100 mA while generating four different output voltage levels (0.9 V, 1.2 V, 1.5 V, 1.8 V)

In this work, a CMOS based optical read-out system for biomarker on immunostrips detection is presented. For the proposed system, a CMOS integrated circuit containing an on-chip photodiode is designed in standard 180 nm UMC CMOS Technology. The system also contains cost-effective 3D Printed structures for holding both IC and the sample immunostrip together. The proposed system can be operated in two

This paper focuses on the design and validation of an analog artificial neural network. Basic building blocks of the analog ANN have been constructed in UMC 90 nm device technology. Performance metrics of the building blocks have been demonstrated through circuit simulations. The weights of the ANN have been estimated through an automated back-propagation algorithm, which is running circuit simulations

Circuits consisting of both memristor and bipolar junction transistor (BJT) were found to be extremely beneficial as the current driven by the transistor enhanced the memristive performances. In this work, memristor-BJT pair was considered and its electronic characteristics were investigated. The pair demonstrated the features of tunable current regulator with reduced circuit complexity. Importantly

This paper focuses on observing the aging impact of a DC offset cancellation circuit (DCOC) on the performance of an amplifier subject to time-based degradation, also known as aging. The circuit can be activated or deactivated to reduce the offset voltage that arises due to possible mismatches between the aging transistor in an amplifier. The proposed DCOC is designed along with a fully differential

This work describes the behavior of a piezoelectric energy harvesting system that uses a single inductor and the concept of energy investment for the whole of building a behavioral model for the harvester and a high-level system analysis approach. The harvester modules and control were specified and described in Verilog-A to fully model the energy harvester operation. Simulation results have shown

The process corner refers to the variation into fabrication parameters used to apply during integrated circuit design to the semiconductor wafer. Inconsistency during design and deviation of voltage and temperature during its operation widens the worst-case margin and significantly degrades the performance. The impact of variation is more pronounced at smaller technology node (< 90 nm). In CAD-tool

In some long-reach high-density wires such as flexible flat cables, the crosstalk signal from the aggressor to the victim lanes exhibits the time shift that depends on the cables. This paper proposes a far-end crosstalk (FEXT) cancellation method with controllable injection timing of the crosstalk cancellation (XTC) signals into the victim lanes. The proposed method uses a delay-line-based digital-to-time

A trade-off switching scheme between high efficiency and considerable area overhead for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. During the design process, the higher-side-reset-and-set (HSRS) coarse–fine architecture ensures significant energy saving. There is no energy consumption in the first two comparison cycles. The presented switching scheme achieves

A Vaq-based switching scheme with capacitor-splitting structure is proposed for successive approximation register analog-to-digital converter. Different from common tri-level schemes utilizing Vcm (1/2Vref), a new third reference voltage Vaq (1/4Vref) is applied to the proposed scheme. Benefiting from Vaq, the proposed scheme achieves 87.5% capacitor area reduction over the conventional scheme. Due

A bias stabilization scheme for inverter is introduced. The conventional inverter structure has lent itself as a power-efficient amplifier block for low-power, low-voltage applications. However, its application is restricted due to the limits in its biasing method. This letter introduces an efficient biasing scheme based on forward body bias technique. The proposed biasing scheme relaxes most of the

In the present world, malignant growth in bosom is the commonly prevailing disease among women. Early bosom diagnosis and treatment are compulsory to diminish the death rates of bosom malignancy. Here, a dielectric differentiation is being detected among typical and malignant growth tissues, having applied ideal scope of frequencies. Winding radio wires becomes the most appropriate in this application

Due to scaling effects, integrated circuits are becoming increasingly more sensitive to noise and delay effects caused by interconnect coupling. Crosstalk noise has now become a critical design and verification issue in deep submicron designs. Driver sizing is a practical and a feasible technique for controlling the crosstalk noise in the post route design stage. Although an increased victim driver

This paper presents a novel, real time, high speed and robust chaos-based pseudo random number generator (PRNG) design using the structures of artificial neural network (ANN)-based 2D chaotic oscillator and ring oscillator. In this study, four different robust PRNGs have been implemented using four different approaches (TS-55, Elliott-93, Elliott-2, Cordic-LUT) of TanSig activation functions (TSAF)

In this paper, a novel non-bandgap CMOS voltage reference with sub one-volt power supply is proposed and simulated in 0.18 μm standard CMOS technology. Thermal voltage obtained from ∆VBE with positive and threshold voltage of a nMOS transistor with negative temperature coefficient are utilized to achieve a stable-temperature voltage reference. A current proportional-to- threshold voltage and a current

Abstract Reading the memristor memory cell without changing its resistance state is one of the potential problems to be addressed in the memristor-based memory design. This paper presents a novel read scheme that achieves a non-destructive read operation, consumes less power, provides high endurance and adapts itself based on the process variations. The proposed scheme uses built-in self-tuning circuitry

In this present contribution, a simple chaotic oscillator based on a memcapacitor with only one equilibrium point is reported. The proposed oscillator consists of an inductor (only storage element) and a nonlinear active memcapacitor which is the key component responsible for the complex behaviors exhibited by the circuit. The resulting mathematical model is a simple jerk-type equation system that

An energy efficient switching algorithm for low voltage SAR ADC is presented. By the combination of MSB-split and merge-and-split techniques, this switching method consumes negative energy in the MSB bit switching, which contributes to 99.76% switching energy reduction comparing to the conventional solution. Furthermore, without requiring for a third reference voltage makes it especially suitable for

In this work, the effect of oscillator phase noise on the bit error rate (BER) for high order QAM communication systems is analyzed. Two high frequency oscillators are designed, built and tested to get real phase noise data, and a BER simulation of a 1024 QAM signal through a super-heterodyne frequency down-converter is implemented using the measured data from the two oscillators as local oscillator

A self-adaptive pulse generator featuring with short pulse width to realize lower power consumption and higher reliability of high voltage gate driver IC is proposed. Under the control of the feedback signal from the output of the high voltage level shifter, the pulse width of the input narrow pulse can be decreased adaptively without affecting the normal operating function. The proposed self-adaptive

A novel temperature-compensated LC-VCO is presented for RFID applications. By employing a low pass passive filter and an auxiliary varactor loop, the frequency drift is reduced by 70% without using any other active device. The effectiveness of the technique is demonstrated on a frequency synthesizer of a RFID transceiver. The frequency synthesizer is fabricated on a 0.18 μm RF process with a single

This paper presents a 9-bit, 2-stage cyclic analog to digital converter (ADC) with a variable bias current control circuitry to reduce its power dissipation. Each stage outputs a three-bit digital word and the circuit requires four subcycles to perform a whole conversion. Since the accuracy required is higher in the first stage and first subcycle and decreases in subsequent cycles, the bias current

Heart shaped reconfigurable band notched UWB microstrip line fed monopole antenna using two mushrooms like electromagnetic band gaps (EBGs) loaded by two varactor diodes has been developed, examined and fabricated. The effect of EBG dimensions, on the notch frequency, was first examined. A notched frequency of 5.3 GHz is obtained when two square EBGs with rectangular slits are used with length equal

An output-capacitorless low-dropout regulator (OCL-LDO) using split-length current mirror compensation and overshoot/undershoot reduction circuit are presented in this paper. At a supply of 1.5 V and a quiescent current of 8.2 µA, the proposed scheme can support a maximum load current of 50 mA. The proposed OCL-LDO has a range of output voltage from 0.8 to 1.25 V with 1.5 V supply. The proposed regulator

This paper presents a compact and robust opamp-free noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC). The proposed NS SAR ADC adopts extra one passive feed-forward path summing in realizing second-order noise shaping with the minimum modification to a standard SAR. Compared with previous works, the noise sources of residue sampling and first-order integration

In this work we present least squares (LS) approach to design linear phase Finite Impulse Response (FIR) filter. Since the design of FIR digital filters is non-analytic, we aim at ideal zero-phase magnitude response and minimize the weighted error in passband and stopbands. The problem of least squares can then be solved non-iteratively by solving system of linear equations. Solution of which yields

A 4- bit reusable stage based asynchronous binary search analog to digital converter (ADC) with a smart switching network, and reduced comparator count is presented in this paper. The proposed ADC uses asynchronous logic to activate comparators sequentially while switching network is used to provide reference voltages for selected comparators. In the extended version, the 6-bit ADC is designed using

A controllable constant-power source in 0.35 μm CMOS technology is presented in this paper. It is based on the resistive mirror method, and suitable for thermally-based sensor applications. Two versions have been developed and fabricated: a high-voltage design with a single supply of 10 V, and a low-voltage design with a single supply of 3.6 V. The measured results for the high voltage (low voltage)

A hexagonal shaped fractal Multiple input Multiple Output (MIMO) antenna resonates to six different frequencies is presented. A dumbbell structure with hexagon shaped defected ground structure (DGS) is created in the ground plane. Two antenna elements sharing a common ground plane are positioned orthogonal to each other for better isolation. The antenna is designed, fabricated using FR4 substrate with

In this paper, an analog correlator based analog front end with gain control circuit for hearing aid devices is designed and fabricated with 0.18 \(\upmu \mathrm{m}\) CMOS process. The proposed analog front end consists of an analog correlator comprised of a multiplier, an integrator, and a mixed mode variable gain amplifier. The analog correlator is utilized to ensure the low input referred noise

In this work, a new design of continuous time current differencing buffered amplifier based low-pass, high-pass, band-pass, all-pass and notch fractional-order filters is reported. The design of proposed filters is based on the approximation of fractional-order filters by using an appropriate integer order transfer function. Signal flow graph approach is used for the realization of fractional-order

The performance of a transimpedance amplifier (TIA) can be enhanced by lowering the input impedance and applying the nonconstant gain-bandwidth product (GBP) technique. In this paper, a TIA of utilizing both properties is presented and the performance of the conventional and the proposed TIAs is analyzed theoretically and experimentally. The lowered input impedance increases the operational bandwidth

In this letter, we present a two-stage rail-to-rail fully synthesizable dynamic voltage comparator. To improve the speed and mismatch performance of the NAND&NOR-based synthesizable comparator, we have proposed to replace these logics with OAI&AOI logic gates, respectively. The comparator is implemented on CMOS 45 nm technology, operating with a supply voltage from 350 mV to 1.0 V. The proposed comparator

In this paper, a new population-based evolutionary technique namely symbiotic organisms search (SOS) optimisation algorithm is proposed to optimize the design variables of transistors used in analog circuit. Here length and width of the transistors are considered to be the design variables, the optimisation of which minimizes the input-referred noise, total MOSFET area, and power consumption. This

This paper presents a 12-bit branching Time-to-Digital converter (TDC) fabricated in a 40 nm CMOS technology. It composes of a 6-bit coarse counter TDC, and a 6-bit fine TDC. The fine TDC utilizes a proposed branching technique to interpolate between the phases of a 16-stage gated ring oscillator, increasing its number of phases from 16 to 64. Therefore, the TDC resolution is improved to be 4 times

This paper presents a fully integrated analog baseband circuit with high reconfigurability intended for use in short-range frequency-modulated continuous-wave (FMCW) radar sensors. The fully differential baseband circuitry achieves maximum overall gain of 60 dB which is adjustable with a 3-dB step. Second-order high-pass filter and fifth-order low-pass filter are incorporated in chain and possess tunable

In this letter, a capacitor-splitting switching algorithm for successive approximation register (SAR) analog-to-digital converters is proposed. To achieve low power, the hybrid switching scheme is involved. The monotonic switching technique is used during the last bit cycle; for other bit cycles except the first one, the switching is based on MSB and the former determined bit. Besides, the common-mode

In the present research, the Fermi energy and temperature-dependent performance of a multilayer graphene nanoribbon (MLGNR) in terms of signal delay and power delay product (PDP) at the global interconnect length for three different technology nodes (32 nm, 22 nm, and 16 nm) were investigated in detail. A Fermi energy and temperature-dependent equivalent single conductor (ESC) based on the analytical

Electrocardiogram (ECG) signal monitoring is crucial in the operating room. During surgery, when using an electrosurgical unit (ESU), the ECG signal is corrupted by strong interference generated by the ESU, so-called Electrosurgical Artifacts (EAs). The objective of this study is to enhance the infected ECG signal and to remove the impact of the EAs. Motivated by the fact that the artifacts’ energy

A four-stage eight-way CMOS power amplifier (PA) for 94 GHz radar sensor is reported. The PA constitutes a common-source (CS) input stage, a CS first gain stage, a two-way CS second gain stage, followed by an eight-way CS output stage using miniature triple Y-shaped divider and combiner. Broadband π-match input, inter-stage, and output networks are adopted for broadband impedance or power matching

In this work, a new circuit of delay cell is proposed to design a wide tuning range differential ring oscillator (DRO). Statistical techniques of Taguchi design of experiments and analysis of variance (ANOVA) are used to optimize the performance parameters of the proposed circuit. Three levels and 3 factors of width (w1, w3 and w4) for various MOSFETs of delay cell, are considered as major performance

Nowadays, the size of the hearing aid devices are reduced to make them invisible and function rapidly. As a result of these factors, an EMI is generated inside the chips. The general working principle of the hearing aid SoC is disrupted by this internal EMI. Thus, an open loop fractional dividers based all-digital clock generator is introduced in the proposed hearing aid SoC. The jitter is reduced

Compact, tunable and wide band stop filter (BSF) for wireless application is presented. The proposed filter is composed of compact rectangular microstrip open loop resonator with stub loaded resonator as building blocks of the filter. First, two vertical lumped capacitors are inserted in the open loop resonator from top to bottom of the substrate at the place which has maximum electric field to decrease

This article discusses modern techniques of implementation of a wideband digital modulator in an FPGA kit for use in electrical engineering communications laboratory. Previous configurations proposed in literature present limitations, as lack of details about the methods used in the algorithm developed and test procedures. Those key details can help researchers to develop this modulator more effectively

This paper presents a low leakage power 10T single-ended SRAM cell in the sub-threshold region that improves read, write, and hold stability. While at low voltages, the write-ability is increased by temporarily floating the data node, the read stability of the cell is maintained approximately as equal as the hold state by separating the data-storage node from the read bit line by using only a single

The principle of ∆-modulation has been leveraged in time-domain to cancel the nonlinearity of voltage to frequency transfer function in VCO-based ADCs. The proposed modulation technique features frequency-tracking loop (FTL) to compensate for the imperfection of frequency nonlinearities and to eliminate the analog Op-Amp. Injection locking is used to alleviate the mismatch effect between the feedforward

In this paper, the prototyping of 3rd order, 4th order, 5th order, and 6th order sigma-delta analog to digital converters (Σ∆ ADCs) has been presented. It summarily portrays the method implemented for configuration and reconfiguration of the proposed circuits by using Field Programmable Analog Array (FPAA). Their function was determined in the time domain at a constant 1 V supply voltages which is

Decreasing the electric length of an antenna results in increasing its input reactance that becomes greater than its input resistance, resulting in a significant rise in its quality factor and in a drastic reduction of its potential operating bandwidth. For such small antennas, namely ESA for Electrically Small Antenna, passive matching is restricted by the gain-bandwidth theory, providing narrow bandwidths

This paper presents a 100 MHz to 6 GHz broadband inductor-less single-to-differential balun gm-boosting low-noise amplifier (LNA) for multi-standard radio applications. Two mechanisms of noise cancellation techniques have been innovatively introduced in this work. To achieve the wideband input matching, high gain, and low noise figure simultaneously, a feed-forward thermal noise cancellation technique

This paper focuses on the modeling and symmetry breaking analysis of the large class of chaotic electronic circuits utilizing an antiparallel diodes pair as nonlinear device necessary for chaotic oscillations. A new and relatively simple autonomous jerk circuit is used as a paradigm. Unlike current approaches assuming identical diodes (and thus a perfect symmetric circuit), we consider the more realistic

An open loop analog-to-digital converter based on ring voltage-controlled oscillator (VCO-based ADC) is presented. By introducing the inverse R–2R pre-weighted front-end technique, the nonlinearities of the voltage to frequency conversion of the proposed VCO is kept less than 1% over rail-to-rail input swing. Unlike prior approaches, this proposed method does not suffer from any stability issues or

In this work we propose a design based on a nanoelectromechanical relay acting as a logic gate inverter. The proposed inverter is made of a double cantilever nanobeam actuated by a fixed central electrode carrying the input signals. The static and dynamic behaviors of the ohmic nanoinverter gate are investigated using an electromechanical mathematical model that fully incorporates nonlinear form of

A tail-less, fully differential trans-conductance amplifier is presented in this paper. The proposed structure arranges the inverters as a core amplifier blocks in an elaborate manner to achieve fully differential function with tail-less power optimized elements. As the inverters are current push–pull structures, they reuse the bias current effectively to maximize the trans-conductance of block. The

An energy-efficient switching scheme with low common-mode voltage variation and simple capacitor array for successive approximation register (SAR) analog-to-digital converters (ADCs) is presented. The proposed scheme adopts simple binary weighted capacitor array without capacitor-splitting, and consumes no switching energy in the first two comparison cycles. The behavioural simulation shows the proposed

This work proposes general formulas for designing two different topologies of fractional-order relaxation oscillators. One topology contains an Operational Amplifier and the other one relies on an Operational Trans-Resistance Amplifier. The design procedure hinges on the general fractional-order natural and step responses of RC, which is proved in this work depending on Mittag Leffler function. The

A 0.7 V 5 nW CMOS Sub-Bandgap voltage reference circuit without resistors is presented. The proposed circuits use a new complementary-to-absolute-temperature voltage generator to reduce the power consumption and area. The circuit consists of one single BJT and sub-threshold transistors. The sub-Bandgap voltage reference is implemented in a 0.18-µm CMOS process. Measured results show that the reference

This paper presents a new digital background calibration method to correct MDAC errors. The novelty of this research is to use Newton–Raphson algorithm in order to reduce the number of divisions as well as power in digital domain. This is achieved by combining the conventional slope mismatch averaging and linear approximation technique to compute the correction coefficient in fast iterative method

Schmitt Triggers have found wide spread use in low-power and threshold-based applications such as peak detectors and spectrum analyzers. They are formed by comparators and feedback loops and exhibit hysteresis at nominal supply voltage. When using dynamic comparators, the periodic discharge of internal capacitors prior to each decision process cancels hysteresis. In addition, dynamic comparators produce

In this paper, a new current mode precision rectifier circuit is proposed using a single EXCCII and two nMOS transistors. The novelty of the circuit is that it can provide all the possible rectified outputs, namely ± full wave as well as ± half wave simultaneously without any alteration of topology. Moreover, it has low input impedance and high output impedance, which is suitable for fully cascadable