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Design of digital pulse width modulator architecture with digital PID controller for DCDC converter using FPGA Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210111
Venkutuswamy Radhika, Karuppanan Srinivasan, Bella Bellie Sharmila, Venkatasalam RukkumaniA digital pulse width modulation architecture (DPWM) along with digital proportional integral derivative (PID) controller to control the DCDC converter is presented in this paper. Difference between the actual output voltage and the reference voltage is calculated as error value. The look up table is created for PID controller to store the duty cycle ratio and the error value of power converters.

Design and implementation of modified BCD digit multiplier for digitbydigit decimal multiplier Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210111
Parthibaraj Anguraj, Thiruvenkadam KrishnanDecimal multiplication is the most common operation in arithmetic applications. This paper presents an areaefficient digitbydigit decimal multiplier using a modified binarycoded decimal digit multiplier. In general, a BinaryCoded Decimal (BCD) digit multiplier consists of two kinds of block, namely binary multiplier, and Partial Product BinarytoDecimal (PPBD) converter. In the BCD digit multiplier

Low power and writeenhancement RHBD 12T SRAM cell for aerospace applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Govind Prasad, Bipin Chandra Mandi, Maifuz AliIn aerospace applications, the conventional Static Random Access Memories (SRAMs) are facing high soft error problems like a single event upset. Several radiationhardened based design (RHBD) like twelvetransistor (12T) Dice, 12T WeQuatro SRAM cells, etc., had been developed to address the soft error problems. But they all are consuming comparatively more total and static power with more delay and

A simple and effective feedback structure for variableQ filter design Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Arman Kheirati Roonizi, Hossein PakniatThis paper proposes a simple and effective feedback structure to implement the variableQ bandpass filter. An effective variableQ bandpass filter can be designed by using integralplusderivative in the feedback pass. The stability of the model is shown in both continuous and discretetime systems. Also, we demonstrate that the model could indeed achieve the desired center frequency as a precise

MSBsplit VCMbased charge recovery symmetrical switching with setanddown asymmetrical switching method for dualcapacitive arrays SAR ADC Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Yewangqing Lu, Ting Zhou, Jiajie Huang, Lulu Wang, Mingyi Chen, Yongfu LiWith the advanced development of CMOS manufacturing process, the capacitivearray in the successive approximation register analogtodigital converters (SAR ADCs) has become the dominant source of energy consumption and silicon area. This requires an immediate attention to design a more energyefficient capacitive switching method while maintaining excellent linearity and noise rejection. A hybrid

An original determination of the maximum phase shift range obtained for an array of N coupled oscillators Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Kaouthar Djemel, Rahma Aloulou, David Cordeau, Hassene Mnif, JeanMarie Paillot, Dorra Mellouli, Mourad LoulouThis paper presents an original approach, using a harmonic balance optimization method, allowing to predict the maximum phase shift range that can be practically obtained for an array of N coupled oscillators. Indeed, unlike what is predicted by the theory, the proposed analysis allows to show that the maximum value of the phase shift decreases by increasing the number N of coupled oscillators in the

Fast SHVC intra prediction mode decision implementation Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Taheni Damak, Ibtissem Wali, Amina Kessentini, Mohamed Ali Ben Ayed, Nouri MasmoudiThe Scalable extension of the High Efficiency Video Coding standard (SHVC) combines the large compression efficiency and high visual quality of HEVC with the possibility of encoding several different versions of the same encoded video in a single bitstream. However, this comes at the cost of a high computational complexity. In order to reduce the SHVC encoding time, an intraprediction mode decision

Energyefficient switching scheme for SAR ADCs using two reference levels Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Junhui Li, Linlin Huang, Lizhen Zhang, Xin Li, Jianhui WuA highly energyefficient capacitor switching scheme for successive approximation register (SAR) analogtodigital converters (ADCs) is proposed. The proposed switching scheme needs only two reference levels by using the mergeandsplit technique, which eliminates the need of the extra reference voltage (Vcm). The switching procedure is performed on the simple binary weighted capacitor arrays without

Design and simulation of fourth order lowpass GmC filter with novel autotuning circuit in 90 nm CMOS Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Mohammad Abdolmaleki, Massoud Dousti, Mohammad Bagher TavakoliA tunable highfrequency operational transconductance amplifier (OTA) is presented along with its application in the implementation of a GmC filter. The OTA is tuned by varying the negative resistance produced by a positive feedback at the output. Postlayout simulation results (using TSMC 90 nm CMOS technology and a 1V supply voltage) show that the differential DC gain, commonmode gain and OTA

A high linearity low power lownoise amplifier designed for ultrawideband receivers Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Behnam Dorostkar Yaghouti, Javad YavandhasaniThis paper presents a new ultrawide band (UWB) CMOS low noise amplifier (LNA) with very high linearity and low power consumption for UWB wireless communication applications, where linearity is a big challenge, due to presence of interference and blocker signals, as well as the inband harmonics of the desired signal components in the lower part of UWB band. The proposed LNA uses a new combination

Correlationbased reconfigurable blind calibration for timing mismatches in TIADCs Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Chengxuan Zhao, Jietao Diao, Hui Xu, Yinan WangMismatches between subchannels limit the dynamic performance of timeinterleaved analogtodigital converters (TIADCs). This paper proposes a correlationbased method of calibration for timing mismatches in Mchannel TIADCs by using the crosscorrelation between subchannels of the output signals to estimate the temporal deviations. The output signal is calibrated by reducing the arbitrary order

A threestage NMC operational amplifier with enhanced slew rate for switchedcapacitor circuits Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210107
Farshad Alizadeh Arand, Mohammad YavariThis paper presents a new architecture for threestage operational transconductance amplifiers (OTAs) with a class AB input stage to improve the slew rate. The nested Miller compensation scheme is utilized to stabilize the proposed OTA. A nonlinear current mirror in the firststage is used to implement the class AB operation. Details of the proposed OTA are described and the circuit level simulation

Design and analysis of reconfigurable fractal antenna with RFswitches on a flexible substrate for Xband applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210104
Bokkisam Venkata Sai Sailaja, Ketavath Kumar NaikThis paper presents a compact reconfigurable elliptical shaped fractal patch (ESFP) antenna with elliptical shaped RF MEMS switch is used for satellite applications at Xband. The proposed work involves the incorporation of RF MEMS switches loaded using parasitic elements with ease of simpler implementation without using DC bias lines. The proposed antenna is integrated with two MEMS switches and reconfigurability

Source injection coupled quadrature oscillator: transient oscillation amplitude and thermally induced phase noise Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210103
Hengameh Azizi, Soolmaz Abbasalizadeh, Hossein MiarNaimiThis paper analyzes the transient oscillation amplitude of the source injection coupled quadrature oscillator (SICQOSC). With the help of the Describing Function Method, we estimate an expression to describe the nonlinear behavior of the negative transconductor. Using the estimated expression, we obtain an accurate closedform formula for the timedomain amplitude of the SICQOSC. The proposed formula

An efficient, scalable, regular clocking scheme based on quantum dot cellular automata Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210103
Jayanta Pal, Amit Kumar Pramanik, Jyotirmoy Sil Sharma, Apu Kumar Saha, Bibhash SenThe present CMOS VLSI technology is facing some challenges like working in nano scale, device density, power dissipation, operating frequency, fast execution, which demands a proper alternative. Quantum dot Cellular Automata (QCA) is one of the feasible substitutes for the same. In QCA, clocking is the primary driving source of power, and the flow of information occurs with the effect of underlying

Performance analysis for reliable nanoscaled FinFET logic circuits Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210103
Umayia Mushtaq, Vijay Kumar SharmaIn the process of continuous miniaturization of devices, it is necessary to look for new devices which overcome the drawbacks of nonscalability and higher static power of metal oxide semiconductor field effect transistor (MOSFET). Finshaped field effect transistor (FinFET) is an important device which uses the concept of multigates and it is not only scalable but also dissipate lower power at lower

Efficient design of dual controlled stacked SRAM cell Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210103
D. Satyaraj, V. BhanumathiIn low power VLSI circuit designs, power dissipation is one of the challenging issues which is associated with threshold voltage. The reduction of threshold voltage increases the subthreshold leakage current by increasing the leakage power dissipation which plays an important role in total power dissipation. Due to this leakage power issue, the devices which are operated by battery for a long time

On the performance of massive MIMO twoway relaying systems using double precision technique Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210103
Sahar Said, Waleed Saad, Mona Shokair, Sayed ElArabyThe practical application for massive MIMO relaying system with a large number of antennas is considered a challenging problem. To solve this problem, a promising solution is to utilize double precision analogtodigital converter (ADC) and digitaltoanalog converter (DAC) at the relay. Depending on the additive quantization noise model, closedform expression for system sum rate is analyzed. Furthermore

A study of phase noise suppression in reference multiple digital PLL without DLLs Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210103
Takahiro Kato, Akira YasudaIn order to suppress the spurious signal resulted from the reference leak and to decrease the oscillator jitter by using phase locked loop (PLL) loop band extension, a reference frequency multiplier that places a delay locked loop (DLL) in front of the PLL has been studied. However, a feedback circuit such as a DLL or an injection locked type voltage controlled oscillator must be used. In this paper

A gain reconfigurable time difference amplifier with selfadaptive linearity control Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210103
Jinhao Li, Jianfei Jiang, Qin Wang, Naifeng Jing, Weiguang Sheng, Guanghui HeTime difference amplifier (TDA) is often used in time domain interconnection, computing and measurement. Gain and linearity control are two main design issues. To reduce the nonlinear distortion, a novel selfadaptive pulse shrink circuit is proposed for the SRlatch based time difference amplifier. The multistage selfadaptive pulse shrink unit can compensate for the gain error caused by the highorder

Chaotic flower pollination algorithm based optimal PID controller design for a buck converter Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
Murat Erhan Çimen, Zeynep B. Garip, Ali Fuat BozThis paper presents a solution based on optimal PID coefficients including antiwind up for buck converter presents using metaheuristic algorithm and chaos theory. A hybrid algorithm is called chaotic based flower pollination algorithm is provided by combining flower pollination algorithm and chaos theory with different maps. Five different choatic maps are used in the aim of increasing the efficacy

ENGTL based antenna for WiFi and 5G Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
Suman NelaturiThis article reported patch antenna functioning at Wi Fi and 5G bands. WiFi band (2.4 GHz) is obtained by loading Epsilon Negative Transmission Line (ENGTL) metamaterials into the patch radiating at 5G band (3.5 GHz). To acquire Circular Polarization (CP) at 5G band, conventional square patch is embedded with poly fractals. The experimental and simulated data are in close proximity. The obtained

Design of Npath notch filter circuit with switchedcapacitor resistor Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
Khilda Afifah, Nicodimus RetdianHum noise such as power line interference is one of the critical problems in biomedical signal acquisition. Various techniques have been proposed to suppress power line interference, such as an Npath notch filter. The notch depth in the conventional Npath notch filter is limited by the number of paths. The previous 10phase Npath notch filter circuit achieved deeper notch depth but has a problem

Design of phase frequency detector with improved output characteristics operating in the range of 1.25 MHz–3.8 GHz Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
Nigidita Pradhan, Sanjay Kumar JanaIn this paper, a CMOS based precharged phase frequency detector (PPFD) with improved output characteristic for phase locked loop (PLL) has been proposed and analyzed. The proposed PFD minimizes the reset time to improve the output characteristics and works upto the frequency of 1.25 MHz–3.8 GHz. In addition, it has an advantage of precharged PFD which has low power consumption capability i.e., 285

A novel MIMO antenna with an improved isolation for UWB and multiband applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
Yashar Zehforoosh, Mehdi ZavvariA compact multipleinput–multipleoutput antenna is presented for Ultra Wide Band (UWB) applications. The antenna consists of two separate modified elliptical patches, two separate ground planes including a triangular slot and a step slot for better accommodation of impedance matching, and also separate feed lines for each port. In this design, it has been attempted to isolate the ports by separating

A differential IRUWB transmitter using PAM modulation with adaptive PSD Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
Luiz Carlos Moreira, Marcus Henrique Victor, Osamu Saotome, Guilherme Heck, Ney L. V. Calazans, Fernando Gehm MoraesThe current state of the telecommunications market exhibits a high potential to absorb efficient innovations in wireless connectivity, especially those that can be applied to the Internet of Things and similar domains. Contributing in that direction, this paper describes the design and implementation of a fully differential impulseradio ultrawideband (IRUWB) transmitter using pulseamplitude modulation

An ultraminiature broadband operational transconductance amplifier utilizing 10 nm wrapgate CNTFET technology Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
Mohammad Khaleqi Qaleh Jooq, Ali Bozorgmehr, Sattar MirzakuchakiOperational Transconductance Amplifiers (OTAs) are the most pivotal blocks in analog circuits and systems. With the emersion of catastrophic short channel effects for Complementary Metal Oxide Semiconductor (CMOS) transistors at deep nanometric regime, the microelectronics scientists have focused on designing ultraminiature OTAs based on nonsilicon materials. During the last few years, GateAllAround

Fully integrated CMOS tunable power amplifier using reconfigurable input/interstage/output matching networks Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
S. Babak Hamidi, Debasis DawnThis paper presents a twostage tunable power amplifier (PA) fullyintegrated in 130 nm CMOS process. This multiband PA consists of reconfigurable input, interstage, and output matching networks in order to tune the center frequency in use. The proposed tunable power amplifier enables three different bands with center frequency of 900 MHz, 1450 MHz, and 1900 MHz. By switching these bands, the designed

Energyefficient approximate adders for DSP applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
Anubothula Tirupathireddy, Musala Sarada, Avireni SrinivasuluIn this paper, approximate adders were proposed for DSP processors. DSP processors are mainly composed of adders and multipliers at bottom level. The power is minimized in transistor level design. Proposed adders have less power dissipation when compared to existing approximate adders. Results have shown that the proposed adders have less PDP with more accuracy. The circuits were simulated in Cadence

On the logic performance of bulk junctionless FinFETs Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
Monali Sil, Abhijit MallikIn this paper, a onetoone comparison of the logic performance is made between CMOS circuits built with bulk junctionless (JL) FinFETs and that with SOI JL FinFETs for three different technology nodes as per the ITRS roadmap. For such comparison: (i) the rise time and fall time are evaluated from the transient analysis of a CMOS inverter,(ii) the propagation delay per stage for a threestage ring

Achieving high linearity and conversion gain in double balanced mixer with cascoded RF and LO stage Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
Maran Ponnambalam, Premanand Venkatesh ChandramaniA simple Cascaded double balanced mixer working at 2.4 GHz, for WLAN application was designed and using 90 nm CMOS technology. The proposed mixer incorprates minimum number of transistors in comparing with the gilbercell mixer. Staking LO stage just above the RF stage reducing the voltage headroom of mixer. Differential combination of RF stage has a common source node and the Differential combination

A lowpower 10bit 0.01to12MS/s asynchronous SAR ADC in 65nm CMOS Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
Arthur Lombardi Campos, João Navarro, Maximiliam Luppe, Eduardo Rodrigues de LimaDuring the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analogtodigital converters (ADCs). This work presents the design

A wideband frequency translational resistive feedback receiver resilient to large harmonic blockers Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
Manas Kumar Lenka, Anshaj Shrivastava, Gaurab BanerjeeBy utilizing frequency translational resistive feedback, a recently proposed blocker currentcancelling wideband receiver (Lenka and Banerjee in IEEE Trans Very Large Scale Integr Syst 27(5): 993–1006, 2019), tolerates 0dBm blockers beyond 40 MHz offset with little degradation in performance. However, like most wideband receivers, the architecture is far less tolerant to “harmonic blockers”, that

Design and fabrication of a microstrip lowpass filter with wide tuning range as harmonic suppression with application in Wilkinson power divider Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
Soroush Karimikhorrami, Gholamhosein MoloudianIn this article, a tunable lowpass filter (LPF) with a hexagonal stepped impedance resonator and multi open stubs is designed. The − 3 dB cutoff frequency for the proposed LPF is 2.2 GHz. Insertion loss (IL) and return loss (RL) in the passband zone are 0.3 dB and 15 dB, respectively. The frequency response slope (rolloff rate) for the proposed LPF is very sharp and equal to 142.4 dB/GHz. The tuning

An innovative design of spin transfer torque based ternary content addressable memory with match line sense amplifier Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210102
K. C. Yatheesh, M. J. Shanti PrasadTernary Content Addressable Memory (TCAM) device is integrated with StaticRandom Access Memory unit to attain high production at a lesser cost. Moreover, the TCAM searching device performs faster parallel searching of whole memory in the entire time. Also, TCAM is constrained by its large area of the cell, extensive active state leakage current, and high power consumption for searching. In this present

A compact fractal dual high frequency band notched UWB antenna with a novel SCDGS Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210101
V. N. Koteswara Rao Devana, A. Maheswara RaoA compact and novel fractal dual band notched UWB antenna with time domain characteristics is presented. A tapered microstrip fed circular fractal radiating patch along with a novel semi circular defected ground structure produce − 10 dB bandwidth from 3.73 to 16.7 GHz. The proposed antenna is a miniature size of 16 × 21 mm2 and is printed on FR4 substrate with two high frequency notched bands from

Energyefficient CMOS voltage level shifters with single $$\hbox {V}_{{DD}}$$ V DD for multicore applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210101
Selvakumar Rajendran, Arvind ChakrapaniThe neverending demands for batterypowered applications are driven by technological advances in the field of low power digital CMOS circuits. The voltage level shifters are crucial primitives for SystemsonChip (SoC) applications and systems operating with different voltage domains. In this article, three single supply energyefficient lowpower voltage level shifters are proposed that are suitable

Design of lowvoltage and lowpower currentmode DTMOS transistor based fullwave/halfwave rectifier Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20210101
Melih YildirimA lowvoltage and lowpower current mode rectifier based on dynamic threshold MOS (DTMOS) transistor is proposed in this paper. The suggested one input–two output rectifier architecture provides fullwave rectification and halfwave rectification. Fullwave rectifier consists of only 6 MOS transistors (excluding 1 MOS transistor in halfwave rectifier part) and is designed without the necessity of

A novel method for minimizing transient current test time by exploiting RES in SRAM Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201201
Princy Prince, N. M. SivamangaiAs technology advances, circuit density and complexity increases in integrated circuits which make the devices vulnerable to different types of manufacturing defects. In such cases, even the occurrence of a fault may be critical. Hence, ensuring Static random access memory (SRAM) reliability and quality with high priority is essential. In this paper, an innovative approach to SRAM testing—waveletbased

$$\alpha$$ α order universal filter realization based on single input multioutput differential voltage current conveyor Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201127
Mohamed Ghoneim, Rana Hesham, Heba Yassin, Ahmed MadianTwo voltagemode topologies single input multioutput universal fractional filters with high input impedance are proposed. The proposed analog filters consist of three DVCC+ blocks, two grounded capacitors and two resistors targeting the minimum passive elements. The proposed topologies provide a realization for all standard fractional filter functions (HP, LP, BP, AP and notch filter). The effect

Efficient twolevel reverse converters for the fourmoduli set {2 n−1 , 2 n –1, 2 n−1 –1, 2 n+1 –1} Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201124
Mohammad Obeidi Daghlavi, Mohammad Reza Noorimehr, Mohammad EsmaeildoustIn this paper, 2 efficient reverse converters are introduced for the fourmoduli set {2n−1, 2n–1, 2n−1–1, 2n+1–1} which offers a high speed arithmetic unit due to its balanced modulus in the form of 2 k and 2 k–1. The proposed converters are designed in twolevel architecture. ROM free and adder base structures are the advantages of the proposed converters which result in efficient implementation in

Threelevel buck converter utilizing a DACbased flying capacitor voltage control technique Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201123
JinWoo So, HongReoul Yang, SuMi Park, Jonghwan Lee, Byung Seong Bae, Kwang Sub YoonThis paper proposes a threelevel buck converter utilizing a DigitaltoAnalog Converter (DAC)based flying capacitor voltage control technique, which controls the voltage on a flying capacitor with a differential difference amplifier and common mode feedback circuit for stable operation. Employment of the DACbased flying capacitor voltage control circuit allows the proposed circuit to compensate

Methodology to optimize and reduce the total gate area of robust operational transconductance amplifiers by using diamond layout style for MOSFETs Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201122
José Roberto Banin Júnior, Rodrigo Alves de Lima Moreto, Gabriel Augusto da Silva, Carlos Eduardo Thomaz, Salvador Pinillos GimenezThis paper describes a pioneering methodology to design, optimize, and reduce the total gate area of robust Operational Transconductance Amplifiers (OTAs). The SingleEnded SingleStage (SESS) OTA has been chosen to validate the proposed technique by using the 180 nm planar Complementary MetalOxideSemiconductor (CMOS) Integrated Circuits (ICs) technology. The Electronic Design Automationtool, named

Noise analysis and optimization of VCIIbased SiPM interface circuit Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201121
G. Ferri, L. Safari, G. Barile, L. Pantoli, V. StornelliRecently, second generation voltage conveyor (VCII)based transimpedance amplifiers (TIAs) have begun to find their way in different applications, among which, silicon photomultipliers (SiPMs) interfacing circuitry. There are many advantages which make VCIIbased TIAs attractive over conventional circuits: the intrinsic low impedance at VCII current input Y port is very helpful to mitigate the effect

Design of low power, programmable lowG m OTAs and G m C filters for biomedical applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201120
V. Senthil Rajan, B. VenkataramaniIn this paper, two programmable operational transconductance amplifiers (POTAs)—one using bulk driven attenuator (BDA) and another using programmable current mirror (PCM) are proposed in order to achieve lowGm and high dynamic range. These OTAs are denoted as BDAPOTA and PCMOTA respectively and are realized using composite transistors operated in the subthreshold region. The pseudo resistor is used

A high energyefficiency and lowarea switching scheme for SAR ADCs Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201118
Mahdi Momeni, Mohammad Sharifkhani, Seyed Behnam YazdaniA high energyefficiency and lowarea switching method is proposed for the successive approximation register analogtodigital converters. In the proposed scheme, the threshold voltage for comparison is derived from the charge sharing technique and using a voltage source connected to the bottom plates of the digitaltoanalogue converter (DAC) capacitors. The switching method achieves an average DAC

A compact and wideband ratrace coupler using twosection ring and artificial transmission lines Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201113
Sara Khanmohamadi, Ahmadreza EskandariA compact and wideband microstrip ratrace coupler employing twosection ring and artificial transmission lines (ATLs) is reported in this paper. The bandwidth is highly improved by using a twosection ratrace coupler. The physical size of the planar circuit is reduced based on the substitution of the microstrip line with an ATL. The area of the proposed design footprint is 35% of the area of the

Modified indirect learning applied to neural networkbased predistortion of a concurrent dualband CMOS power amplifier Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201111
Luis Schuartz, Luiza B. C. Freire, Artur T. Hara, André A. Mariano, Bernardo Leite, Eduardo G. LimaCurrent radio communication systems that adopt amplitude and phase modulations demand high linearity and high efficiency. The cascade connection between digital baseband predistorter (DPD) and power amplifier (PA) can be a costeffective solution to guarantee the required linearity without compromising the efficiency. In the design of a DPD for a single band PA, direct learning can be used to extract

Using pulse width modulation with carrier frequency changing for transmission of two separate signals Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201104
Milan StorkPulse width modulation (PWM) is widely used in different applications. PWM transforms the information in the amplitude of a bounded input signal into the pulse width output signal without suffering from quantization noise. The frequency of the output signal is usually constant. In this paper, the new PWM system with frequency changing (PWMFM) is described. In such PWMFM the pulse width and also the

A switching frequency modulated DCtoDC converter with reduced spurious noise for a RF power amplifier in microwatts transmitters Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201030
Eung Jung Kim, Hyoungsoo Kim, ChangHyuk Cho, ChangHo Lee, Joy LaskarVarying a supply voltage using a DCtoDC converter can significantly improve the efficiency of RF power amplifiers (PAs) for lowpower RF transceivers. However, intrinsic switching noise from a conventional DCtoDC converter operating in fixed PulseWidth Modulation (PWM) can affect the system performance since the spectral components in the switching noise are confined in the fundamental switching

An investigation on neuron–astrocyte interaction system: network behavior and synchronization Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201027
Saeed Haghiri, Arash AhmadiAstrocytes, also described as astroglia, are characteristic starshaped glial cells in the brain. The important roles of astrocyte such as extracellular regulation, synaptic information regulation, neuronal synchronization and feedback to neural activity, makes the astrocytes play a vital role in the brain disease. This paper investigates the neuron–astrocyte interaction system for evaluating the network

Neuromorphic analog spikingmodulator for audio signal processing Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201026
Pietro M. Ferreira, Jamel Nebhen, Geoffroy Klisnick, Aziz BenlarbiDelaiWhile CMOS scaling is currently reaching its limits in power dissipation and circuit density, the analogy between biology and silicon is emerging as a solution to ultralowpower signal processing. Urgent applications involving artificial vision and audition, including intelligent sensing, appeal original energy efficient and ultraminiaturized siliconbased solutions. While stateoftheart is focusing

Design and analysis of a wideband compact LNAmixer in millimeter wave frequency Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201022
Tahereh Heidari, Abdolreza NabaviThis paper presents the design and analysis of a millimeterwave LNAmixer, which adopts a lownoise singletodifferential conversion balun with low phase (gain) imbalance, using a commonsource and a commongate stage. Each stage employs a cascode transistor with inductors in the gate and source for improving noise, gain, and bandwidth performance. A new transformerbased network is proposed for

Automated topdown pruning optimization approach in RF power amplifier designs Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201021
Lida Kouhalvandi, Osman Ceylan, Serdar OzoguzThis study presents an automated highaccuracy optimization approach for designing highperformance radio frequency high power amplifiers (HPAs). The amplifier is designed by applying a topdown pruning optimization approach that automatically converts the given HPA with lumped elements (LEs) to the HPA with distributed elements (DEs). Firstly, the lumped element HPA is designed based on a bottomup

Optimization techniques for analog and RF circuit designs: an overview Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201019
Lida Kouhalvandi, Osman Ceylan, Serdar OzoguzOptimizations have gained much consideration from the researchers working in the domains of analog and radio frequency (RF), recently. Dealing with highly nonlinear behavior of active components and aiming to meet design specifications are common issues in all nonlinear circuit designs. As a consequence and accordingly, many studies have been conducted on diverse optimization methods and algorithms

A 6bit hierarchal TDC architecture for timebased ADCs Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201017
Mostafa RashdanA 6bit hieratical timetodigital (TDC) architecture suitable for timebased ADC circuits is presented in this paper. The design consists of similar stages at which each stage recovers one bit. Using the proposed architecture, the total number of bits can be increased without complicating the design as in other conventional TDC architectures. A 6bit 1.3 Gb/s TDC circuit has been designed and simulated

A wideband quasiasymmetric Doherty power amplifier with a twosection matchingphase difference compensator network design using GaAs technology Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201017
Seyedehmarzieh Rouhani, Ahmad Ghanaatian, Adib Abrishamifar, Majid TayaraniIn this paper, a quasiasymmetric Doherty power amplifier (PA) is designed without load modulation using the GaAs 0.25 µm pHEMT technology to reach an enlarged output power backoff (OPBO) with circuitry solutions in order to overcome technology restrictions. To prevent power leakage in auxiliary PA (PAaux) due to its extremely low offstate impedance (Zoff), a Wilkinson power combiner is added to

A CMOS closedloop miniaturized wireless power transfer system for brain implant applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201015
Nishat T. Tasneem, Dipon K. Biswas, Ifana MahbubNearfield inductively coupled wireless power transfer (WPT) system has been extensively utilized for brain implant applications. Still, the efficient and reliable delivery of power is challenging as the received power varies due to different variabilities between the transmitter (TX) and the receiver (RX) coils. A closedloop adaptive control system utilizing load shift keying, designed in the 0.5 µm

Design of a 40 GHz low noise amplifier using multigate technique for cascode devices Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201015
Rana Azhar Shaheen, Timo Rahkonen, Aarno PärssinenIncreased parasitic components in siliconbased nanometer (nm) scale active devices have various performance tradeoffs between optimizing the key parameters, for example, maximum frequency of oscillation (\(f_{max}\), gate resistance and capacitance, etc. A commonsource cascode device is commonly used in amplifier designs at RF/millimeterwave (mmWave) frequencies. In addition to intrinsic parasitic

An evolution of Colpitts VCO for simultaneous optimization of phase noise and FoM in GaAs technologies Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20201012
JingYu Han, Yu Jiang, GuiLiang Guo, Xu ChengThis paper presents a novel cooptimization configuration to simultaneously improve phase noise and FoM in order to solve the longexisting issue of excellent phase noise and mediocre FoM in the light of GaAs technologies. Considering traditional GaAs based Colpitts/classC VCOs, a first step is taken with the introduction of noise shifting structure while a second step is carried out with the presentation