A simple and robust design for CMOS realization of a tunable grounded meminductor using three operational transconductance amplifier (OTA) and two capacitors have been proposed. Both theoretical analyses and simulation using Cadence Virtuoso at 0.18 \(\upmu {m}\) CMOS technology parameters verify the validity of the meminductor. Its meminductance can be tuned with the help of external bias voltage

A design methodology for level shifters voltage translators, where the output voltage ranges from 0 to 18 V, and the input voltage ranges from 2 to 5.5 V in a 0.6 µm CMOS-HV technology, is presented. This family of circuits have a special interest in the case of implantable medical devices where is common to handle previously unknown voltages either positive or negative, above or below the control

This paper presents a wide frequency range three-stage voltage-controlled ring oscillator in CNTFET technology. The advantages of CNTFETs are the high speed of charge carriers, high signal to noise ratio, small size and ballistic transport. Therefore in comparison with MOSFETs, they have a higher frequency, and can operate at a wide frequency range with a very low phase noise if forward bulk bias and

This paper presents a high-efficiency Class \({\mathrm{FF}}^{-1}\) DPA using the quad-mode coupled technique for new configurable front-end 5G transmitters. The proposed DPA consists of carrier PA, main PA, input–output matching network and hybrid power network (HPN). The HPN includes a quad-mode coupled technique which is four-section U-shaped transmission line. The HPN is used for even–odd mode impedance

Due to various kind of Band-To-Band Tunneling (BTBT) operation, Heterojunction Tunnel Field Effect Transistors (HEFETs) are widely used in ultralow power applications. Anyhow, circuit complexity is a major issue in case of HEFET based memory development because of their uncomfortable size. Device scaling is a better way to eliminate such kind of issues for HEFET based memory development. Thus, development

The paper proposes a new grounded/floating frequency dependent negative conductance (FDNC) simulator, and a non-ideal frequency dependent negative resistance (FDNR) simulator, based on deployment of voltage differencing transconductance amplifiers (VDTA), along with two grounded capacitances. The presented simulators feature electronic controllability of realized negative conductance/resistance via

In this paper, a CMOS mm-wave phase locked loop (PLL) with improved voltage controlled oscillator (VCO) and injection-locked frequency divider (ILFD) at operational harmonic frequency 125 GHz is presented. The VCO structure uses the bulk effective and MOS varactor capacitor to adjust parasitic capacitor of the cross coupled pair. It obtains 2th harmonic frequency with 24% tuning range (110–140 GHz)

This research article comes with three novel topologies of Voltage Mode (VM) third order Quadrature Sinusoidal Oscillators (QSOs) using Current Differencing Buffered Amplifier (CDBA) as an active device with grounded and virtually grounded passive components. An implementation perspective of the prototype circuits follows a specific class of filter specifically Low pass (LP), High pass (HP) and All

This paper presents a dual-input extended-dynamic-range, high-PCE rectifier for dedicated far-field RF energy harvesting systems. Two identical input RF energy supply source are applied into two individual rectifier. The rectifier with the highest PCE is selected to deliver dc power to a single-load element. A logic control circuit senses Pin from the rectified dc voltage and toggles between the rectifiers

In this study, a novel single-stage Digital Variable Gain Amplifier architecture (DVGA) was presented for Long Time Evolution (LTE) receivers. The proposed DVGA combines two transimpedance amplifiers, a transconductance amplifier and a novel digitally controlled current. Using a digital control block, an auxiliary pair to retain a constant current density enabled changing the gain. The Heuristic Method

In this paper, a class-E power amplifier using a harmonic control network consisting of a bandpass filter and a harmonic control circuit is presented. The advantage of using the bandpass filter in the harmonic control network is the elimination of the DC-block capacitor between the transistor and the load. As a result, losses due to this capacitor are eliminated at operating frequencies. In this design

In this study, an analog circuit design instead of using a software is utilized to remove Salt and Pepper (S&P) noise in image. For this purpose, a digital image filtering method which is called median filter is carried out. In median filter method, a current-mode nine-input one-output circuit architecture is preferred since 3 × 3 filtering mask is employed. Median filter circuit is based on a modified

A 6-bit 2.3 GS/s single-channel sub-radix pipeline ADC using an incomplete settling concept is presented. A radix detector is proposed to detect stage gain in the background so that low gain and low bandwidth opamps can be utilized to conserve power. The raw ADC output codes can be reconstructed with the detected radix to retrieve its accuracy. The simulated results show that the prototype ADC in 40 nm

In this paper we propose an efficient approach to design fractional-order elements’ (FOEs) series, while using a very limited set of “seed” FOEs. The proposed approach follows the idea of general immittance inverter/converter, whereas a suitable circuit solution employing operational transconductance amplifiers is also presented and can be used for the design of grounded FOEs with the fractional order

A mono-bit digital receiver circuit for instantaneous frequency measurement is presented. The circuit is co-designed with Indium Phosphide Double Heterojunction Bipolar Transistor and complementary metal oxide semiconductor (CMOS) devices. The chip is fabricated by InP/CMOS three-dimensional (3D) heterogeneous integration using the wafer-level bonding technique. The measurable signal frequency within + 15

This paper proposes a circuit-level model of an inverter-based switched-capacitor (SC) integrator involved in a previously published incremental sigma-delta analog-to-digital converter (I\(\Sigma {\Delta }\) ADC) to explain the ADC resolution degradation observed in the post-layout simulation. A fine analysis of post-layout signals led to a new model of the integrator with parasitic capacitors. Then

In this work we analysed the stepwise charging technique to find the limits from which it is beneficial in terms of load capacitance and charge–discharge frequency. We included in the analysis practical limitations such as the consumption of auxiliary logic needed to implement the technique and the minimum size of auxiliary switches imposed by the technology. We proposed an ultra-low-power logic block

The focus of the present study is on a recycling folded cascode (RFC) operational transconductance amplifier (OTA) in which the transconductance, as well as the slew rate of OTA, are enhanced. RFC OTA, proposed in this study, is employed using a Dynamic Threshold Voltage MOSFET (DTMOS) based differential pair with class AB operation. To achieve class AB operation, an adaptive biasing technique comprising

In this paper, a low-complexity resistorless high-precision sub-1 V MOSFET-only voltage reference is presented. To obtain an accurate output, a curvature-compensation technique is used, canceling its logarithmic temperature dependence regardless of the value of the mobility temperature exponent \((\gamma )\). The circuit is realized in 65 nm CMOS technology and yields an output voltage of 574 mV, a

A double-pole double-throw analog switch circuit structure with low power consumption, low on-resistance and capable of transmitting negative signals is designed in this paper, which has been developed in 0.18 μm BCD technology. The analog switch circuit is providing about 5 V high swing signal transmission for 2.7–5 V supply voltage in the temperature range of − 40 to 85 °C. The shortcomings of traditional

This letter presents a novel high energy-efficient switching scheme with low common-mode level variation for successive approximation register (SAR) analog-to-digital converters. Benefit from the merge capacitor split and C-2C techniques, the proposed switching scheme achieves 98% saving in switching energy and 86.91% reduction in capacitor area over the conventional scheme without reset energy. Compared

In this paper concurrent design of Schottky diode based limiter and low noise amplifier (LNA), based on noise matching, is investigated to achieve minimum noise figure (NF) of the receiver chain. In design procedure of the LNA, the noise figure is minimum, gain at central frequency is 14.5 dB, and limiter structure tolerates up to 5 W continuous wave input power. In the proposed concurrent design,

The power amplifiers (PAs) are generally the most power-consuming building blocks in Radio Frequency (RF) transceivers. This paper presents a high efficiency fully integrated inverse class D power amplifier for the narrowband Internet of Things (NB-IoT) applications. In this design, the PA's power added efficiency (PAE) is improved by inserting two auxiliary PMOS transistors into the conventional topology

This paper presents the detailed design, analysis and measurements of new configuration of quad-band antenna. The antenna is designed using a new uni-planar complementary split ring resonator (UP-CSRR) unit cell. The UP-CSRR unit cell is etched in the top plane of a microstrip patch which reduces the back radiation and enhances the antenna efficiency. The structure has advantage of the presence of

Epilepsy disease is one of the most prevalent neurological disorders caused by malfunction of large symptoms number of neurons. That’s lead us to propose an automated approach to classify Electroencephalography (EEG) signals of the aforementioned pathology. To realize an efficient seizures detection the output of our classification is divided into three classes; normal, pre-ictal and ictal class. In

We propose a novel power splitter (or divider) comprising two back-to-back quarter-wavelength (λ/4) coupled lines (i.e. coupler). To improve the isolation between the output ports (i.e. ports 2 and 3), an isolation resistor R is included. Three power dividers are designed and implemented. To enhance the reflection coefficients, and S21 and S31 and their amplitude imbalance (AI) and phase difference

In this paper, we present six area-efficient transimpedance type second-order analog filters. There are many applications where the available signal is current, however the necessary signal for further processing is voltage type. For such applications the presented circuits will be a useful solution. The technique employed is called MOS-only technique and to the best of our knowledge this is the first

Neural networks are achieving state-of-the-art performance in many applications, from speech recognition to computer vision. A neuron in a multi-layer network needs to multiply each input by its weight, sum the results and perform an activation function. This paper is an extended version of the article in which we present an implementation of an amplifier-based MOS analog neuron and the optimization

With the focus of employing single Voltage Differencing Transconductance Amplifier (VDTA) in designing of electronically tunable oscillators, three configurations have been proposed in this manuscript. Each configuration enjoys an efficient integrated circuit implementation due to use of grounded capacitors. Unambiguous and independent control of its condition and frequency of oscillation is an additional

The memristor is a nonlinear device with a particular memory function and is widely used in various circuit researches. This work studies the peak current mode controlled (PCMC) buck converter with the memristive load at the continuous current mode (CCM). Firstly, a state equation for a buck converter with the memristive load is derived and a generic voltage-controlled memristor simulator is constructed

This paper proposes a novel Z-source boost derived hybrid converter (ZSBDHC) that produces high gain dual output from a single DC input, which is the choice of a solar photovoltaic system. This has multiple advantages as lesser count of switches, high power processing capability and high reliability result in reduction of overall cost. Besides, the prime advantage of this topology is achieving high

This paper presents a CMOS based tunable bandgap voltage and current reference generation circuit. The proposed circuit is designed without using Bipolar Junction Transistors (BJTs) for Proportional-To-Absolute-Temperature and Complementary-To-Absolute-Temperature generation, thus eliminating the problem of implementing BJT in CMOS fabrication process. The proposed circuit is simulated in standard

This paper presents electronically controllable neuron circuit-neuristor- based logic OR and AND gates using the same circuit topology. Here, only four neuristors are used to obtain both OR and AND gates which have three inputs and one output. The proposed circuit is electronically controllable and can be used as an OR or AND gate by changing only one voltage source without changing any circuit topology

High carrier frequency requirement (Sub 6, 28 GHz) to accomplish the high bandwidth specification for millimeter wave band wireless communication, has reduced the ratio of operating carrier frequency (fc) and unity current gain frequency (ft) of MOSFETs in state of the art RFCMOS technology. This poses a challenge for designing a high gain and low noise receiver with better linearity. In an attempt

An analog signal processing (ASP) circuit used for CMOS image sensor (CIS) readout is presented. The proposed ASP mainly includes a two-stage programmable gain amplifier (PGA), a sample-and-hold amplifier (SHA) merged by a pipelined analog–digital converter (ADC), and a digital-analog converter (DAC). Compared with conventional readout architecture, the proposed can provide finer gain, level shifting

This paper presents a high-performance multiple-input multiple-output (MIMO) antenna with a compact size of 42 × 42 mm2. The proposed antenna operates in the frequency range of 3.2–12 GHz for ultra wide band (UWB) wireless communication systems. The proposed MIMO antenna has four identical elements arranged to be orthogonal to each other to achieve a good performance. To achieve high isolation, stubs

A digital pulse width modulation architecture (DPWM) along with digital proportional integral derivative (PID) controller to control the DC-DC converter is presented in this paper. Difference between the actual output voltage and the reference voltage is calculated as error value. The look up table is created for PID controller to store the duty cycle ratio and the error value of power converters.

Decimal multiplication is the most common operation in arithmetic applications. This paper presents an area-efficient digit-by-digit decimal multiplier using a modified binary-coded decimal digit multiplier. In general, a Binary-Coded Decimal (BCD) digit multiplier consists of two kinds of block, namely binary multiplier, and Partial Product Binary-to-Decimal (PPBD) converter. In the BCD digit multiplier

In aerospace applications, the conventional Static Random Access Memories (SRAMs) are facing high soft error problems like a single event upset. Several radiation-hardened based design (RHBD) like twelve-transistor (12T) Dice, 12T We-Quatro SRAM cells, etc., had been developed to address the soft error problems. But they all are consuming comparatively more total and static power with more delay and

This paper proposes a simple and effective feedback structure to implement the variable-Q band-pass filter. An effective variable-Q band-pass filter can be designed by using integral-plus-derivative in the feedback pass. The stability of the model is shown in both continuous and discrete-time systems. Also, we demonstrate that the model could indeed achieve the desired center frequency as a precise

With the advanced development of CMOS manufacturing process, the capacitive-array in the successive approximation register analog-to-digital converters (SAR ADCs) has become the dominant source of energy consumption and silicon area. This requires an immediate attention to design a more energy-efficient capacitive switching method while maintaining excellent linearity and noise rejection. A hybrid

This paper presents an original approach, using a harmonic balance optimization method, allowing to predict the maximum phase shift range that can be practically obtained for an array of N coupled oscillators. Indeed, unlike what is predicted by the theory, the proposed analysis allows to show that the maximum value of the phase shift decreases by increasing the number N of coupled oscillators in the

The Scalable extension of the High Efficiency Video Coding standard (SHVC) combines the large compression efficiency and high visual quality of HEVC with the possibility of encoding several different versions of the same encoded video in a single bitstream. However, this comes at the cost of a high computational complexity. In order to reduce the SHVC encoding time, an intra-prediction mode decision

A highly energy-efficient capacitor switching scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. The proposed switching scheme needs only two reference levels by using the merge-and-split technique, which eliminates the need of the extra reference voltage (Vcm). The switching procedure is performed on the simple binary weighted capacitor arrays without

A tunable high-frequency operational transconductance amplifier (OTA) is presented along with its application in the implementation of a Gm-C filter. The OTA is tuned by varying the negative resistance produced by a positive feedback at the output. Post-layout simulation results (using TSMC 90 nm CMOS technology and a 1-V supply voltage) show that the differential DC gain, common-mode gain and OTA

This paper presents a new ultra-wide band (UWB) CMOS low noise amplifier (LNA) with very high linearity and low power consumption for UWB wireless communication applications, where linearity is a big challenge, due to presence of interference and blocker signals, as well as the in-band harmonics of the desired signal components in the lower part of UWB band. The proposed LNA uses a new combination

Mismatches between sub-channels limit the dynamic performance of time-interleaved analog-to-digital converters (TI-ADCs). This paper proposes a correlation-based method of calibration for timing mismatches in M-channel TI-ADCs by using the cross-correlation between sub-channels of the output signals to estimate the temporal deviations. The output signal is calibrated by reducing the arbitrary order

This paper presents a new architecture for three-stage operational transconductance amplifiers (OTAs) with a class AB input stage to improve the slew rate. The nested Miller compensation scheme is utilized to stabilize the proposed OTA. A nonlinear current mirror in the first-stage is used to implement the class AB operation. Details of the proposed OTA are described and the circuit level simulation

This paper presents a compact reconfigurable elliptical shaped fractal patch (ESFP) antenna with elliptical shaped RF MEMS switch is used for satellite applications at X-band. The proposed work involves the incorporation of RF MEMS switches loaded using parasitic elements with ease of simpler implementation without using DC bias lines. The proposed antenna is integrated with two MEMS switches and reconfigurability

This paper analyzes the transient oscillation amplitude of the source injection coupled quadrature oscillator (SIC-QOSC). With the help of the Describing Function Method, we estimate an expression to describe the nonlinear behavior of the negative transconductor. Using the estimated expression, we obtain an accurate closed-form formula for the time-domain amplitude of the SIC-QOSC. The proposed formula

The present CMOS VLSI technology is facing some challenges like working in nano scale, device density, power dissipation, operating frequency, fast execution, which demands a proper alternative. Quantum dot Cellular Automata (QCA) is one of the feasible substitutes for the same. In QCA, clocking is the primary driving source of power, and the flow of information occurs with the effect of underlying

In the process of continuous miniaturization of devices, it is necessary to look for new devices which overcome the drawbacks of non-scalability and higher static power of metal oxide semiconductor field effect transistor (MOSFET). Fin-shaped field effect transistor (FinFET) is an important device which uses the concept of multi-gates and it is not only scalable but also dissipate lower power at lower

In low power VLSI circuit designs, power dissipation is one of the challenging issues which is associated with threshold voltage. The reduction of threshold voltage increases the subthreshold leakage current by increasing the leakage power dissipation which plays an important role in total power dissipation. Due to this leakage power issue, the devices which are operated by battery for a long time

The practical application for massive MIMO relaying system with a large number of antennas is considered a challenging problem. To solve this problem, a promising solution is to utilize double precision analog-to-digital converter (ADC) and digital-to-analog converter (DAC) at the relay. Depending on the additive quantization noise model, closed-form expression for system sum rate is analyzed. Furthermore

In order to suppress the spurious signal resulted from the reference leak and to decrease the oscillator jitter by using phase locked loop (PLL) loop band extension, a reference frequency multiplier that places a delay locked loop (DLL) in front of the PLL has been studied. However, a feedback circuit such as a DLL or an injection locked type voltage controlled oscillator must be used. In this paper

Time difference amplifier (TDA) is often used in time domain interconnection, computing and measurement. Gain and linearity control are two main design issues. To reduce the nonlinear distortion, a novel self-adaptive pulse shrink circuit is proposed for the SR-latch based time difference amplifier. The multi-stage self-adaptive pulse shrink unit can compensate for the gain error caused by the high-order

This paper presents a solution based on optimal PID coefficients including anti-wind up for buck converter presents using meta-heuristic algorithm and chaos theory. A hybrid algorithm is called chaotic based flower pollination algorithm is provided by combining flower pollination algorithm and chaos theory with different maps. Five different choatic maps are used in the aim of increasing the efficacy

This article reported patch antenna functioning at Wi- Fi and 5G bands. Wi-Fi band (2.4 GHz) is obtained by loading Epsilon Negative Transmission Line (ENGTL) metamaterials into the patch radiating at 5G band (3.5 GHz). To acquire Circular Polarization (CP) at 5G band, conventional square patch is embedded with poly fractals. The experimental and simulated data are in close proximity. The obtained

Hum noise such as power line interference is one of the critical problems in biomedical signal acquisition. Various techniques have been proposed to suppress power line interference, such as an N-path notch filter. The notch depth in the conventional N-path notch filter is limited by the number of paths. The previous 10-phase N-path notch filter circuit achieved deeper notch depth but has a problem

In this paper, a CMOS based precharged phase frequency detector (PPFD) with improved output characteristic for phase locked loop (PLL) has been proposed and analyzed. The proposed PFD minimizes the reset time to improve the output characteristics and works upto the frequency of 1.25 MHz–3.8 GHz. In addition, it has an advantage of precharged PFD which has low power consumption capability i.e., 285