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An analog correlator based CMOS analog front end with digital gain control circuit for hearing aid devices Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200703
Hyusim Park, Sungyong Jung, HoonJu ChungIn this paper, an analog correlator based analog front end with gain control circuit for hearing aid devices is designed and fabricated with 0.18 \(\upmu \mathrm{m}\) CMOS process. The proposed analog front end consists of an analog correlator comprised of a multiplier, an integrator, and a mixed mode variable gain amplifier. The analog correlator is utilized to ensure the low input referred noise

Analysis and investigation of CDBA based fractionalorder filters Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200703
Gagandeep Kaur, Abdul Quaiyum Ansari, M. S. HashmiIn this work, a new design of continuous time current differencing buffered amplifier based lowpass, highpass, bandpass, allpass and notch fractionalorder filters is reported. The design of proposed filters is based on the approximation of fractionalorder filters by using an appropriate integer order transfer function. Signal flow graph approach is used for the realization of fractionalorder

Performance analysis of SiGeHBTbased transimpedance amplifiers with nonconstant gainbandwidth technique Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200702
Pujan K. C. Mishu, Seungwoo Jung, Ickhyun SongThe performance of a transimpedance amplifier (TIA) can be enhanced by lowering the input impedance and applying the nonconstant gainbandwidth product (GBP) technique. In this paper, a TIA of utilizing both properties is presented and the performance of the conventional and the proposed TIAs is analyzed theoretically and experimentally. The lowered input impedance increases the operational bandwidth

A 0.35 Vto1.0 V synthesizable railtorail dynamic voltage comparator based OAI & AOI logic Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200701
Xiaocui Li, Ting Zhou, Yuxin Ji, Yongfu LiIn this letter, we present a twostage railtorail fully synthesizable dynamic voltage comparator. To improve the speed and mismatch performance of the NAND&NORbased synthesizable comparator, we have proposed to replace these logics with OAI&AOI logic gates, respectively. The comparator is implemented on CMOS 45 nm technology, operating with a supply voltage from 350 mV to 1.0 V. The proposed comparator

An evolutionarybased design methodology for performance enhancement of a foldedcascode OTA using symbiotic organisms search algorithm and g m /I D technique Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200701
Madhusmita Panda, Santosh Kumar Patnaik, Ashis Kumar Mal, Sumalya GhoshIn this paper, a new populationbased evolutionary technique namely symbiotic organisms search (SOS) optimisation algorithm is proposed to optimize the design variables of transistors used in analog circuit. Here length and width of the transistors are considered to be the design variables, the optimisation of which minimizes the inputreferred noise, total MOSFET area, and power consumption. This

A 12bit branching timetodigital converter with power saving features and digital based resolution tuning for PVT variations Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200629
Jian Sen Teh, Liter SiekThis paper presents a 12bit branching TimetoDigital converter (TDC) fabricated in a 40 nm CMOS technology. It composes of a 6bit coarse counter TDC, and a 6bit fine TDC. The fine TDC utilizes a proposed branching technique to interpolate between the phases of a 16stage gated ring oscillator, increasing its number of phases from 16 to 64. Therefore, the TDC resolution is improved to be 4 times

A highly programmable 60dB gain analog baseband circuit with DCoffset cancellation for shortrange FMCW radar applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200629
Dušan V. Obradović, Ðorđe P. Glavonjić, Dušan P. Krčum, Veljko R. Mihajlović, Ivan M. MilosavljevićThis paper presents a fully integrated analog baseband circuit with high reconfigurability intended for use in shortrange frequencymodulated continuouswave (FMCW) radar sensors. The fully differential baseband circuitry achieves maximum overall gain of 60 dB which is adjustable with a 3dB step. Secondorder highpass filter and fifthorder lowpass filter are incorporated in chain and possess tunable

A capacitorsplitting DAC switching scheme with high powerefficiency and low commonmode voltage variation Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200624
Hao Wang, Zhixin Chen, Wenming Xie, Tianwei Chen, Haiyan OuIn this letter, a capacitorsplitting switching algorithm for successive approximation register (SAR) analogtodigital converters is proposed. To achieve low power, the hybrid switching scheme is involved. The monotonic switching technique is used during the last bit cycle; for other bit cycles except the first one, the switching is based on MSB and the former determined bit. Besides, the commonmode

Investigation on the combined effects of variable Fermi energies and temperatures on the performance of multilayer graphene nanoribbon as interconnects Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200623
Himanshu Sharma, Karmjit Singh SandhaIn the present research, the Fermi energy and temperaturedependent performance of a multilayer graphene nanoribbon (MLGNR) in terms of signal delay and power delay product (PDP) at the global interconnect length for three different technology nodes (32 nm, 22 nm, and 16 nm) were investigated in detail. A Fermi energy and temperaturedependent equivalent single conductor (ESC) based on the analytical

Blind separation of ECG signals from noisy signals affected by electrosurgical artifacts Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200620
Kahina Bensafia, Ali Mansour, AbdelOuahab Boudraa, Salah Haddab, Philippe Ariès, Benoit ClementElectrocardiogram (ECG) signal monitoring is crucial in the operating room. During surgery, when using an electrosurgical unit (ESU), the ECG signal is corrupted by strong interference generated by the ESU, socalled Electrosurgical Artifacts (EAs). The objective of this study is to enhance the infected ECG signal and to remove the impact of the EAs. Motivated by the fact that the artifacts’ energy

94 GHz eightway power amplifier with high output power and poweradded efficiency in 90 nm CMOS Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200616
YoSheng Lin, KaiSiang LanA fourstage eightway CMOS power amplifier (PA) for 94 GHz radar sensor is reported. The PA constitutes a commonsource (CS) input stage, a CS first gain stage, a twoway CS second gain stage, followed by an eightway CS output stage using miniature triple Yshaped divider and combiner. Broadband πmatch input, interstage, and output networks are adopted for broadband impedance or power matching

Effectiveness of Taguchi and ANOVA in design of differential ring oscillator Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200615
Gaurav Kumar Sharma, Arun Kishor Johar, Tangudu Bharat Kumar, Dharmendar BoolchandaniIn this work, a new circuit of delay cell is proposed to design a wide tuning range differential ring oscillator (DRO). Statistical techniques of Taguchi design of experiments and analysis of variance (ANOVA) are used to optimize the performance parameters of the proposed circuit. Three levels and 3 factors of width (w1, w3 and w4) for various MOSFETs of delay cell, are considered as major performance

Openloop digital clock generator based VLSI architecture for electromagnetic interference reduction Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200611
P. Meenakshi Vidya, S. SudhaNowadays, the size of the hearing aid devices are reduced to make them invisible and function rapidly. As a result of these factors, an EMI is generated inside the chips. The general working principle of the hearing aid SoC is disrupted by this internal EMI. Thus, an open loop fractional dividers based alldigital clock generator is introduced in the proposed hearing aid SoC. The jitter is reduced

Compact and wideband microwave bandstop filter for wireless applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200610
Ahmed A. Ibrahim, Omar K. El Shafey, Mahmoud A. AbdallaCompact, tunable and wide band stop filter (BSF) for wireless application is presented. The proposed filter is composed of compact rectangular microstrip open loop resonator with stub loaded resonator as building blocks of the filter. First, two vertical lumped capacitors are inserted in the open loop resonator from top to bottom of the substrate at the place which has maximum electric field to decrease

Wideband FPGAbased digital modulator programming and practical validation techniques Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200609
Luiz A. Corrêa, Iago de A. Oliveira, Alvaro Augusto Machado de Medeiros, Alexandre B. dos Santos, Eduardo P. de Aguiar, Daniel D. SilveiraThis article discusses modern techniques of implementation of a wideband digital modulator in an FPGA kit for use in electrical engineering communications laboratory. Previous configurations proposed in literature present limitations, as lack of details about the methods used in the algorithm developed and test procedures. Those key details can help researchers to develop this modulator more effectively

A singleended low leakage and low voltage 10T SRAM cell with high yield Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200608
Nima Eslami, Behzad Ebrahimi, Erfan Shakouri, Deniz NajafiThis paper presents a low leakage power 10T singleended SRAM cell in the subthreshold region that improves read, write, and hold stability. While at low voltages, the writeability is increased by temporarily floating the data node, the read stability of the cell is maintained approximately as equal as the hold state by separating the datastorage node from the read bit line by using only a single

Phasedomain ADC with ∆modulation frequency tracking loop Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200608
Karama M. ALTamimi, Ezz ElMasry, Kamal ElSankaryThe principle of ∆modulation has been leveraged in timedomain to cancel the nonlinearity of voltage to frequency transfer function in VCObased ADCs. The proposed modulation technique features frequencytracking loop (FTL) to compensate for the imperfection of frequency nonlinearities and to eliminate the analog OpAmp. Injection locking is used to alleviate the mismatch effect between the feedforward

Design and implementation of higher order sigma delta modulator circuits using FPAA Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200608
Daisy Deenrii Roel, Manoj KumarIn this paper, the prototyping of 3rd order, 4th order, 5th order, and 6th order sigmadelta analog to digital converters (Σ∆ ADCs) has been presented. It summarily portrays the method implemented for configuration and reconfiguration of the proposed circuits by using Field Programmable Analog Array (FPAA). Their function was determined in the time domain at a constant 1 V supply voltages which is

Methodology for broadband matching of electrically small antenna using combined nonFoster and passive networks Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200606
Saadou Almokdad, Raafat Lababidi, Marc Le Roy, Sawsan Sadek, André Pérennec, Denis Le JeuneDecreasing the electric length of an antenna results in increasing its input reactance that becomes greater than its input resistance, resulting in a significant rise in its quality factor and in a drastic reduction of its potential operating bandwidth. For such small antennas, namely ESA for Electrically Small Antenna, passive matching is restricted by the gainbandwidth theory, providing narrow bandwidths

An inductorless CMOS broadband balun g m boosting LNA exploiting noise cancellation techniques Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200603
Tingting Han, Zhiqun Li, Mi TianThis paper presents a 100 MHz to 6 GHz broadband inductorless singletodifferential balun gmboosting lownoise amplifier (LNA) for multistandard radio applications. Two mechanisms of noise cancellation techniques have been innovatively introduced in this work. To achieve the wideband input matching, high gain, and low noise figure simultaneously, a feedforward thermal noise cancellation technique

A broken symmetry approach for the modeling and analysis of antiparallel diodesbased chaotic circuits: a case study Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200527
Leandre Kamdjeu Kengne, Herve Thierry Kamdem Tagne, Adelaide Nicole Kengnou Telem, Justin Roger Mboupda Pone, Jacques KengneThis paper focuses on the modeling and symmetry breaking analysis of the large class of chaotic electronic circuits utilizing an antiparallel diodes pair as nonlinear device necessary for chaotic oscillations. A new and relatively simple autonomous jerk circuit is used as a paradigm. Unlike current approaches assuming identical diodes (and thus a perfect symmetric circuit), we consider the more realistic

A 0.2 pJ/step open loop VCObased ADC with inverse R–2R preweighted linearization Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200523
Karama M. ALTamimi, Kamal ElSankaryAn open loop analogtodigital converter based on ring voltagecontrolled oscillator (VCObased ADC) is presented. By introducing the inverse R–2R preweighted frontend technique, the nonlinearities of the voltage to frequency conversion of the proposed VCO is kept less than 1% over railtorail input swing. Unlike prior approaches, this proposed method does not suffer from any stability issues or

Modeling and design of an ultra lowpower NEMS relays: application to logic gate inverters Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200522
Hatem Samaali, Fehmi Najar, Amar ChaalaneIn this work we propose a design based on a nanoelectromechanical relay acting as a logic gate inverter. The proposed inverter is made of a double cantilever nanobeam actuated by a fixed central electrode carrying the input signals. The static and dynamic behaviors of the ohmic nanoinverter gate are investigated using an electromechanical mathematical model that fully incorporates nonlinear form of

A 0.4 V, tailless, fully differential transconductance amplifier: an all inverterbased structure Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200521
Hassan Faraji BaghtashA tailless, fully differential transconductance amplifier is presented in this paper. The proposed structure arranges the inverters as a core amplifier blocks in an elaborate manner to achieve fully differential function with tailless power optimized elements. As the inverters are current push–pull structures, they reuse the bias current effectively to maximize the transconductance of block. The

An energyefficient switching scheme with low commonmode voltage variation and nocapacitorsplitting DAC for SAR ADC Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200511
Junhui Li, Xin Li, Linlin Huang, Jianhui WuAn energyefficient switching scheme with low commonmode voltage variation and simple capacitor array for successive approximation register (SAR) analogtodigital converters (ADCs) is presented. The proposed scheme adopts simple binary weighted capacitor array without capacitorsplitting, and consumes no switching energy in the first two comparison cycles. The behavioural simulation shows the proposed

Two implementations of fractionalorder relaxation oscillators Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200510
Omar Elwy, Amr M. AbdelAty, Lobna A. Said, Ahmed H. Madian, Ahmed G. RadwanThis work proposes general formulas for designing two different topologies of fractionalorder relaxation oscillators. One topology contains an Operational Amplifier and the other one relies on an Operational TransResistance Amplifier. The design procedure hinges on the general fractionalorder natural and step responses of RC, which is proved in this work depending on Mittag Leffler function. The

A 0.7 V 5 nW CMOS subbandgap voltage reference without resistors Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200510
Min Pan, Jiaye Xie, Lili PangA 0.7 V 5 nW CMOS SubBandgap voltage reference circuit without resistors is presented. The proposed circuits use a new complementarytoabsolutetemperature voltage generator to reduce the power consumption and area. The circuit consists of one single BJT and subthreshold transistors. The subBandgap voltage reference is implemented in a 0.18µm CMOS process. Measured results show that the reference

Digital calibration of pipelined ADC using Newton–Raphson algorithm Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200508
Ehsan Zia, Ebrahim Farshidi, Abdolnabi KosarianThis paper presents a new digital background calibration method to correct MDAC errors. The novelty of this research is to use Newton–Raphson algorithm in order to reduce the number of divisions as well as power in digital domain. This is achieved by combining the conventional slope mismatch averaging and linear approximation technique to compute the correction coefficient in fast iterative method

Clock delaybased design for hysteresis programming and noise reduction in dynamic comparators Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200430
Leila Khanfir, Jaouhar MouineSchmitt Triggers have found wide spread use in lowpower and thresholdbased applications such as peak detectors and spectrum analyzers. They are formed by comparators and feedback loops and exhibit hysteresis at nominal supply voltage. When using dynamic comparators, the periodic discharge of internal capacitors prior to each decision process cancels hysteresis. In addition, dynamic comparators produce

Resistorless current mode precision rectifier using EXCCII Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200425
Rupam Das, Sajal K. PaulIn this paper, a new current mode precision rectifier circuit is proposed using a single EXCCII and two nMOS transistors. The novelty of the circuit is that it can provide all the possible rectified outputs, namely ± full wave as well as ± half wave simultaneously without any alteration of topology. Moreover, it has low input impedance and high output impedance, which is suitable for fully cascadable

Extracting method of packet dependence from NoC simulation traces using association rule mining Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200423
Weslley N. Costa, Lucas P. Lima, Otavio A. de Lima JuniorNetworks onchip (NoCs) interconnect complex parallel applications on multiprocessors systemsonchip. In order to rapidly evaluate NoCs, designers replace processing elements by communication traces on simulations. However, tracebased simulations have low accuracy due to the lack of information about packet dependence. The methods to obtain packet dependence require running multiple simulations or

Testing the blade resilient asynchronous template Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200423
Felipe A. Kuentzer, Leonardo R. Juracy, Matheus T. Moreira, Alexandre M. AmoryAs VLSI design moves into ultradeepsubmicron technologies, timing margins added to the clock period are mandatory, to ensure correct circuit behavior under worstcase conditions. Timing resilient architectures emerged as a promising solution to alleviate these worstcase timing margins. These architectures allow improving system performance and reducing energy consumption. Asynchronous systems, on

Evaluating nanomagnetic logic circuit layouts using different clock schemes Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200422
Ruan Evangelista Formigoni, Leandro Lázaro Araújo Vieira, Omar Paranaiba Vilela Neto, Ricardo Ferreira, José Augusto M. NacifThe complementary metal oxide semiconductor technology, CMOS, is reaching its physical limitations, as the transistors’ feature size decreases. A promising alternative is the nanomagnetic logic technology (NML), a paradigm of fieldcoupled nanocomputing. This technology applies single domain nanomagnets to implement digital logic with switching energies that are orders of magnitude lower than a CMOS

A CMOS twoway time interleaved 12bit SAR ADC with 6bit MSBs sharing technique Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200422
HoYong Lee, MinSoo Shim, Jongwhan Lee, Byung Seong Bae, Kwang Sub YoonThis paper describes a twoway time interleaved 12bit SAR ADC with 6bit MSBs sharing technique. The proposed 12bit SAR ADC consists of two SAR ADCs connected in parallel, so that the sampling rate can be doubled. The first 12bit SAR ADC is employed to determine the 12 bits and the second 12bit SAR ADC utilizes the upper 6bits of the first one, so that it can determine the lower 6bits and save

A highly reliable design for twoway binaryGray codes transformation Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200419
FuTeng Cheng, YuCherng Hung, ChiouKou TungIn this study, we design twoway binaryGray codes encoding/decoding circuit. Twoway means that the circuit can be function programmed as either binarytoGray or Graytobinary code transformations. A selfchecking capability is also embedded in circuit design to enhance the function reliability. The proposed circuit will automatically detect the error due to singlefault occurred in chip internal

Utilizing manufacturing variations to design a tristate flipflop PUF for IoT security applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200418
Sajid Khan, Ambika Prasad Shah, Shailesh Singh Chouhan, Sudha Rani, Neha Gupta, Jai Gopal Pandey, Santosh Kumar VishvakarmaPhysically unclonable functions (PUF) are digital fingerprints which generate high entropy, temperresilient keys and/or chipidentifiers for security applications. When considering the miniaturized hardware development for the Internet of Things (IoT), security is of high importance. In this case, PUF designing using SRAM or D flipflops are quite common but with compromised uniqueness due to the

A parallel systemonchip approach for impedance controller for a 7DoF robotic hand Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200418
Sergio A. Pertuz, Carlos Llanos, Cesar Peña, Daniel MuñozRobotic hands tend to have a high number of sensors and actuators in a small space, whose supervising and control must be performed at the same time with precision and, in some cases, at high speed. Usually, a grid of MicroProcessorsUnits or MicroControllerUnits (MCUs) is employed to solve this problem, given the ease of programming. However, this solution can carry some drawbacks like the necessity

Design and implementation of a 60–113 GHz downconversion mixer in 90 nm CMOS Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200415
YoSheng Lin, KaiSiang LanA 60–113 GHz downconversion mixer in 90 nm CMOS is demonstrated. The mixer adopts an RL core IF load, which is based on the series of a peaking inductor (L) and a parallel combination of the crosscoupled PMOS transistors (CCPT) and the diodeconnected NMOS transistors (DCNT), i.e. LCCPT–DCNTbased core IF load. Conversion gain (CG) can be significantly enhanced due to the increase of load impedance

A SPICE model for design of threshold current controlled memristive devices based applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200413
Cesar de Souza Dias, Paulo F. ButzenThis paper presents a generic SPICE model for threshold current controlled memristive devices. This work relates to mathematical development to allow this kind of behavior and it exhibits its relationship with the equivalent circuit adopted to achieve this goal. The operating logic is described and the code for its computational implementation is presented and explained. The functionality of the model

Mechanical stress estimation using PiezoFET octagonal current mirrors Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200412
Jose L. Ramirez, Fabiano FruettThis paper covers the design, characterization and calibration of stress sensors useful to measure the inplane stress at the surface of integrated circuits. Each sensor is based on piezoFET current mirrors aligned in four different directions; the mismatch in the current output in each mirror is related to the stress aligned with the device, then, the changes in the output currents can be used to

Simple charge controlled floating memcapacitor emulator using DXCCDITA Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200411
John Vista, Ashish RanjanThis research article introduces generalized design procedure for incremental/decremental memcapacitor using analog active device that brings a charge controlled floating memcapacitor emulator. The demonstration of generalized model using Dual X current conveyor differential input transconductance amplifier (DXCCDITA) as an analog active device comes with grounded capacitor and single resistor. The

A differential low power wakeup circuit based on systematic offset for BAP UHF RFID tag Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200410
Rafael Cantalice, Daniel Barcelos, Fabricio Mattos, Fernando Paixão CortesThis paper presents a wakeup circuit for batteryassisted passive (BAP) RFID applications. The circuit is composed by a differential envelope detector and a comparator with a systematic offset. The differential RF signal envelope detector and the comparator are designed to increase the wakeup circuit sensitivity and to have low power consumption, improving battery lifetime. The wakeup circuit was

A 1 MHz PVT compensated RC oscillator with $$\hbox {8 ppm}/^{\circ }\hbox {C}$$8 ppm/∘C frequency stability Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200404
Vivek Tyagi, Shivam Kalla, Vikas RanaThis paper presents a 1 MHz PVT compensated dual phase relaxation Oscillator. The oscillator core employs a current controlled voltage bias replica circuit to limit the charging of capacitor. Furthermore, the current starved schmitt trigger circuit is employed in oscillator in place of conventional power consuming comparators. They also provide stable switching threshold voltage across temperature

Robust linear sampling switch for lowvoltage SAR ADCs Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200404
Bhawna Tiwari, Pydi Ganga Bahubalindruni, Sujay Deb, João GoesThis paper presents a linear sampling switch for lowvoltage successiveapproximation register (SAR) analoguetodigital converters (ADCs) operating at a frequency of tens of MHz. The proposed switch employs a bootstrapped transmission gate, where the bulk voltages are generated internally to minimize variations in the threshold voltage of transistors with input signal amplitude. Thus, ensuring almost

Dynamic range improvement of sixport receiver through analysis of output DC offset Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200403
Mehran Hazer Sahlabadi, Abdolali Abdipour, Abbas MohammadiIn this paper, we improved the error vector magnitude (EVM) performance of sixport receiver using a low noise amplifier (LNA) bias control algorithm based on analyzing the correlation between normalized output DC offset voltage and EVM relative to input radio frequency (RF) power variation. In contrast to the other works published in the literature, we consider test setup through which the software

A 1.1 μW biopotential amplifier based on bulkdriven quasifloating gate technique with extremely lowvalue of offset voltage Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200402
Preeti Sharma, Kulbhushan Sharma, H. S. Jatana, Jaya Madan, Rahul Pandey, Rajnish SharmaBiopotential amplifier (BPA) remains one of the most crucial blocks for the successful implementation of any of the biomedical systems. However, design of a BPA remains challenging owing to most of the topologies reported in literature displaying high values of noise, consuming high value of power and working in limited range of bandwidth. Thus, circuit topologies capable of providing an optimum and

Realisation of some currentmode fractionalorder VCOs/SRCOs using multiplication mode current conveyors Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200131
K S. Subhadhra, Ravindra K. Sharma, S. S. GuptaIn this paper for the first time a catalogue of linear voltagecontrolled fractionalorder oscillators employing multiplicationmode current conveyor (MMCC) have been systematically derived using state variable approach. The work also includes detailed relevant analysis of the derived oscillators. Furthermore, three special cases are considered for each of the derived oscillators. Nonideal analysis

Applying design equations in particle swarm optimization for autosizing of multistage opamps: an experimental study Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20191024
Yuejing Ben, Guoyong ShiThis paper presents an experimental study on using analytical design equations in the particle swarm optimization (PSO) for the automatic sizing of multistage operational amplifiers (opamps). Differing from the existing research, this work incorporates design equations in the PSO search process in attempt to reduce the search space dimensionality and the number of PSO iterations without sacrificing

An energyefficient sampleandhold circuit in CNTFET technology for highspeed applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200302
Hamid Mahmoodian, Mehdi DolatshahiIn this paper, a new energyefficient sample and hold (S/H) circuit based on the proper combination of the Millereffect and doublesampling technique is presented in the Carbon Nanotube Field Effect Transistor (CNTFET) technology. In order to improve the accuracy and increase the input dynamic voltage range, a new CNTFETbased linearized switch circuit is introduced to be utilized as both the input

A nature inspired optimization algorithm for VLSI fixedoutline floorplanning Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200205
M. Shunmugathammal, C. Christopher Columbus, S. AnandVLSI floorplan optimization problem aim to minimize the following measures such as, area, wirelength and dead space (unused space) between modules. This paper proposed a method for solving floorplan optimization problem using Genetic Algorithm which is named as ‘Lion Optimization Algorithm’ (LOA). LOA is developed for nonslicing floorplans having soft modules with fixedoutline constraint. Although

Design and analysis of wide tuning range differential ring oscillator (WTRDRO) Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200118
G. K. Sharma, A. K. Johar, T. B. Kumar, D. BoolchandaniA new circuit of delay cell for differential ring oscillator (DRO), to generate wide tuning range, has been proposed. Two architectures of DRO: 3 stage and 4 stage, have been designed and simulated under the power supply constraint of 1.1 V, using GPDK 45 nm CMOS technology. Dual voltages are used to control the tuning frequency range in 3 stage DRO whereas single voltage control is used in 4 stage

Complex dynamics of a novel 3D autonomous system without linear terms having line of equilibria: coexisting bifurcations and circuit design Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200129
Rudolphe Wafo Tapche, Zeric Tabekoueng Njitacke, Jacques Kengne, François Beceau PelapIn recent years, an increasing interest has been devoted to the discovery of new chaotic systems with special properties. In this paper, a novel and singular 3D autonomous system without linear terms is introduced. The singularity of the model is that it is dissipative, possesses rotation symmetry and line of equilibria thus displays complex dynamics. The nonlinear behaviour of the introduced model

Optimization of thermal aware multilevel routing for 3D IC Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20191012
P. Sivakumar, K. Pandiaraj, K. JeyaPrakashDue to the technological advancements, the three dimensional Integrated Circuits become the most popular technology. But it has the major drawback of increased time consumption as well power consumption. This happens because of the increased wire length and routing path for connecting the components in chip. Thus it is essential to reduce the wire length for the purpose of enhancing the circuit speed

Commonmode interference and power conversion efficiency of differential rectifiers in RF energy harvesters Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200313
Zemin Liu, YuPin Hsu, Bassem Fahs, Mona M. HellaThis paper studies the effect of amplitude and phase mismatch on the power conversion efficiency of differentiallydrive rectifiers employing crosscoupled MOSFETs. The analysis begins by defining the different operational regions of the differential rectifier and how the commonmode interference resulting from amplitude and phase mismatches affects the symmetrical operation of the rectifier. A mathematical

Passive–active integrators chaotic oscillator with antiparallel diodes: analysis and its chaosbased encryption application to protect electrocardiogram signals Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20191113
Justin Roger Mboupda Pone, Serdar Çiçek, Sifeu Takougang Kingni, Alain Tiedeu, Martin KomAbstract An autonomous passive–active integrators oscillator with antiparallel diodes is proposed and analysed in this paper. It consists of antiparallel diodes and two main blocks: A secondorder passive RLC integrator and a firstorder active RC integrator. The existence of two Hopf bifurcations is established during the stability analysis of the unique equilibrium point. For a suitable choice

DVCC+ based multifunction and universal filters with the high input impedance features Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200401
Halil Alpaslan, Erkan YuceIn this paper, plustype differential voltage current conveyor based two voltagemode (VM) analog filters with high input impedance properties yielding easy cascadability with other VM circuits are proposed. The first proposed filter can simultaneously provide all the secondorder universal filter responses except allpass one, and employs only grounded passive elements that are canonical in number

Analysis and design of output matching network for Doherty power amplifiers Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200401
Xin Cao, Bowen Luo, QiangMing Cai, Yuyu Zhu, Zuxue XiaIn this paper, a method for designing output matching network is proposed. The impedance matching idea is based on the sufficient condition of the ideal transistors. At this condition, the improved terminal load accommodates to the transistor load at the variation of the input power, which simplifies the design process and increases the matching accuracy. For verification, a Doherty power amplifier

A 17 MS/s SAR ADC with energyefficient switching strategy Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200330
Sina Mahdavi, Sarang Kazeminia, Khayrollah HadidiAbstract A simple energyefficient switching procedure is proposed to reduce the total number of switches and facilitate the capacitors matching requirements in SAR ADCs. The main idea is that the coupling capacitor (CC) is utilized as the same as the unit one, which is applied for LSB charge production. After the reset phase, only the MSB capacitor is connected to the input potential, while the other

A fault recovery protocol for brokers in centralized publishsubscribe systems targeting multiprocessor systemsonchips Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200325
Anderson R. P. Domingues, Jean Carlo Hamerski, Alexandre de Morais AmoryAbstract The publishsubscribe programming model has been an alternative to the design of dataintensive distributed applications in many domains. Recently, this model has been ported to the domain of Multiprocessor SystemsonChips, in which applications must use the underlying NetworkonChip communication infrastructure effectively due to restrictions on the architecture such as low power consumption

Implementation of deep neural networks on FPGACPU platform using Xilinx SDSOC Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200324
Rania O. Hassan, Hassan MostafaAbstract Deep Convolutional Neural Networks (CNNs) are the stateoftheart systems for image classification due to their high accuracy but on the other hand their high computational complexity is very costly. The acceleration is the target in this field nowadays for using these systems in real time applications. The Graphics Processing Units is the solution but its highpower consumption prevents