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A Schmitttrigger based low read power 12T SRAM cell Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200926
Ashish Sachdeva, V. K. TomarIn this article, a Schmitt trigger based 12Transistors(ST12T) static randomaccess memory (SRAM) bitcell has been proposed. The Read Power of proposed cell is reduced by 29.17%/ 24.14% /7.66% /5.87% /7.67% /16.62% when compared to 6T/ 7T/ TA8T/ 9T/ PPN10T/ D2p11T SRAM cells. Proposed ST12T cell also shows 1.52\(\times\) and 1.86\(\times\) lesser variability in read current and read power respectively

A widetemperature range (77–400 K) CMOS lowdropout voltage regulator system Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200925
Halil İbrahim Kayıhan, Benan Beril İnam, Batuhan Doğan, Mustafa Berke YeltenIn this study, a lowdropout voltage regulator (LDO) system composed of two LDOs, which can operate in the temperature range of 77–400 K, has been developed. Cryogenic and typical transistor models of the 180 nm UMC CMOS process have been employed in the design process. Both LDOs can provide a load current of 100 mA while generating four different output voltage levels (0.9 V, 1.2 V, 1.5 V, 1.8 V)

Quantitative detection system for immunostrips in 180nm standard CMOS technology Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200920
Engincan Tekin, Caner Celikdemir, Busra Ucar, Ozgur Gul, Baykal SariogluIn this work, a CMOS based optical readout system for biomarker on immunostrips detection is presented. For the proposed system, a CMOS integrated circuit containing an onchip photodiode is designed in standard 180 nm UMC CMOS Technology. The system also contains costeffective 3D Printed structures for holding both IC and the sample immunostrip together. The proposed system can be operated in two

Design and validation of an artificial neural network based on analog circuits Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200916
Fikret Başar Gencer, Xhesila Xhafa, Benan Beril İnam, Mustafa Berke YeltenThis paper focuses on the design and validation of an analog artificial neural network. Basic building blocks of the analog ANN have been constructed in UMC 90 nm device technology. Performance metrics of the building blocks have been demonstrated through circuit simulations. The weights of the ANN have been estimated through an automated backpropagation algorithm, which is running circuit simulations

Memristor BJT pair based low complex circuits for portable electronics Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200916
P Michael Preetam Raj, Arvind Subramaniam, Souvik KunduCircuits consisting of both memristor and bipolar junction transistor (BJT) were found to be extremely beneficial as the current driven by the transistor enhanced the memristive performances. In this work, memristorBJT pair was considered and its electronic characteristics were investigated. The pair demonstrated the features of tunable current regulator with reduced circuit complexity. Importantly

A switchable DC offset cancellation circuit for timebased degradation correction Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200916
Didem Erol, Ali Doğuş Güngördü, Günhan Dündar, Mustafa Berke YeltenThis paper focuses on observing the aging impact of a DC offset cancellation circuit (DCOC) on the performance of an amplifier subject to timebased degradation, also known as aging. The circuit can be activated or deactivated to reduce the offset voltage that arises due to possible mismatches between the aging transistor in an amplifier. The proposed DCOC is designed along with a fully differential

Behavioral modeling of a piezoelectric harvester with adaptive energyinvestment for improved battery charging Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200914
Tales Luiz Bortolin, André Luiz AitaThis work describes the behavior of a piezoelectric energy harvesting system that uses a single inductor and the concept of energy investment for the whole of building a behavioral model for the harvester and a highlevel system analysis approach. The harvester modules and control were specified and described in VerilogA to fully model the energy harvester operation. Simulation results have shown

SBOX under PVT variation Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200727
Abhishek Kumar, Suman Lata TripathiThe process corner refers to the variation into fabrication parameters used to apply during integrated circuit design to the semiconductor wafer. Inconsistency during design and deviation of voltage and temperature during its operation widens the worstcase margin and significantly degrades the performance. The impact of variation is more pronounced at smaller technology node (< 90 nm). In CADtool

A 40 nm 16 Gb/s differential transmitter with farend crosstalk cancellation using injection timing control for highdensity flexible flat cables Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200914
Daigo Takahashi, Yusuke Fujita, Satoshi Miura, Tetsuya IizukaIn some longreach highdensity wires such as flexible flat cables, the crosstalk signal from the aggressor to the victim lanes exhibits the time shift that depends on the cables. This paper proposes a farend crosstalk (FEXT) cancellation method with controllable injection timing of the crosstalk cancellation (XTC) signals into the victim lanes. The proposed method uses a delaylinebased digitaltotime

A 99.15% energyreduced switching scheme based on HSRS coarse–fine architecture for SAR ADCs Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200905
Peiyi Yue, Yongyuan Li, Shubin Liu, Zhangming ZhuA tradeoff switching scheme between high efficiency and considerable area overhead for successive approximation register (SAR) analogtodigital converters (ADCs) is proposed. During the design process, the highersideresetandset (HSRS) coarse–fine architecture ensures significant energy saving. There is no energy consumption in the first two comparison cycles. The presented switching scheme achieves

A 99.82% energysaving and 87.5% areareducing Vaqbased switching scheme with capacitorsplitting structure for SAR ADC Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200903
Linlin Huang, LiZhen Zhang, Xin Li, Junhui Li, Jianhui WuA Vaqbased switching scheme with capacitorsplitting structure is proposed for successive approximation register analogtodigital converter. Different from common trilevel schemes utilizing Vcm (1/2Vref), a new third reference voltage Vaq (1/4Vref) is applied to the proposed scheme. Benefiting from Vaq, the proposed scheme achieves 87.5% capacitor area reduction over the conventional scheme. Due

Biasstabilized inverteramplifier: an inspiring solution for lowvoltage and lowpower applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200902
Hassan Faraji BaghtashA bias stabilization scheme for inverter is introduced. The conventional inverter structure has lent itself as a powerefficient amplifier block for lowpower, lowvoltage applications. However, its application is restricted due to the limits in its biasing method. This letter introduces an efficient biasing scheme based on forward body bias technique. The proposed biasing scheme relaxes most of the

Design of 4 × 4 antenna array for breast cancer detection Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200831
K. Vijaykumar, M. Baskaran, V. Gayathri, P. GayathriIn the present world, malignant growth in bosom is the commonly prevailing disease among women. Early bosom diagnosis and treatment are compulsory to diminish the death rates of bosom malignancy. Here, a dielectric differentiation is being detected among typical and malignant growth tissues, having applied ideal scope of frequencies. Winding radio wires becomes the most appropriate in this application

Crosstalk noise mitigation using a transmission gate with varied gate bias Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200825
Selahattin Sayil, Subed Lamichhane, Kutay SayilDue to scaling effects, integrated circuits are becoming increasingly more sensitive to noise and delay effects caused by interconnect coupling. Crosstalk noise has now become a critical design and verification issue in deep submicron designs. Driver sizing is a practical and a feasible technique for controlling the crosstalk noise in the post route design stage. Although an increased victim driver

A novel secure chaosbased pseudo random number generator based on ANNbased chaotic and ring oscillator: design and its FPGA implementation Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200818
Murat TunaThis paper presents a novel, real time, high speed and robust chaosbased pseudo random number generator (PRNG) design using the structures of artificial neural network (ANN)based 2D chaotic oscillator and ring oscillator. In this study, four different robust PRNGs have been implemented using four different approaches (TS55, Elliott93, Elliott2, CordicLUT) of TanSig activation functions (TSAF)

Sub 1V supply voltagereference based on mutual temperature cancellation of V T and V TH Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200814
M. RashtianIn this paper, a novel nonbandgap CMOS voltage reference with sub onevolt power supply is proposed and simulated in 0.18 μm standard CMOS technology. Thermal voltage obtained from ∆VBE with positive and threshold voltage of a nMOS transistor with negative temperature coefficient are utilized to achieve a stabletemperature voltage reference. A current proportionalto threshold voltage and a current

Variationtolerant, lowpower, and high endurance read scheme for memristor memories Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200810
V. Ravi, K. Chitra, S. R. S. PrabaharanAbstract Reading the memristor memory cell without changing its resistance state is one of the potential problems to be addressed in the memristorbased memory design. This paper presents a novel read scheme that achieves a nondestructive read operation, consumes less power, provides high endurance and adapts itself based on the process variations. The proposed scheme uses builtin selftuning circuitry

Complex dynamical behaviors in a memcapacitor–inductor circuit Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200809
M. Kountchou, V. R. Folifack Signing, R. L. Tagne Mogue, J. Kengne, SaïdouIn this present contribution, a simple chaotic oscillator based on a memcapacitor with only one equilibrium point is reported. The proposed oscillator consists of an inductor (only storage element) and a nonlinear active memcapacitor which is the key component responsible for the complex behaviors exhibited by the circuit. The resulting mathematical model is a simple jerktype equation system that

Energy efficient switching scheme based on MSBsplit structure for SAR ADC Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200807
Shanshan Han, Lizhen Zhang, Jianhui WuAn energy efficient switching algorithm for low voltage SAR ADC is presented. By the combination of MSBsplit and mergeandsplit techniques, this switching method consumes negative energy in the MSB bit switching, which contributes to 99.76% switching energy reduction comparing to the conventional solution. Furthermore, without requiring for a third reference voltage makes it especially suitable for

Analysis of oscillator phase noise effect on high order QAM links Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200805
Cagri Bicici, Ibrahim Ozdur, Osman CerezciIn this work, the effect of oscillator phase noise on the bit error rate (BER) for high order QAM communication systems is analyzed. Two high frequency oscillators are designed, built and tested to get real phase noise data, and a BER simulation of a 1024 QAM signal through a superheterodyne frequency downconverter is implemented using the measured data from the two oscillators as local oscillator

A selfadaptive pulse generator to realize extremely low power consumption and high reliability of high voltage gate driver IC Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200805
Siyuan Yu, Jing Zhu, Yangyang Lu, Dongdong Li, Yunqi Wang, Ziyue Xiang, Yunwu Zhang, Long Zhang, Weifeng SunA selfadaptive pulse generator featuring with short pulse width to realize lower power consumption and higher reliability of high voltage gate driver IC is proposed. Under the control of the feedback signal from the output of the high voltage level shifter, the pulse width of the input narrow pulse can be decreased adaptively without affecting the normal operating function. The proposed selfadaptive

A 1.8 GHz temperature drift compensated LCVCO for RFID transceiver Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200804
Qingshan Liu, Changchun ChaiA novel temperaturecompensated LCVCO is presented for RFID applications. By employing a low pass passive filter and an auxiliary varactor loop, the frequency drift is reduced by 70% without using any other active device. The effectiveness of the technique is demonstrated on a frequency synthesizer of a RFID transceiver. The frequency synthesizer is fabricated on a 0.18 μm RF process with a single

Low power 9bit 500 kS/s 2stage cyclic ADC using OTA variable bias current Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200804
José Ángel DíazMadrid, Ginés DoménechAsensi, Ramón RuizMerino, Juan Zapata, José Javier MartínezThis paper presents a 9bit, 2stage cyclic analog to digital converter (ADC) with a variable bias current control circuitry to reduce its power dissipation. Each stage outputs a threebit digital word and the circuit requires four subcycles to perform a whole conversion. Since the accuracy required is higher in the first stage and first subcycle and decreases in subsequent cycles, the bias current

Heart shaped reconfigurable bandnotched ultrawide band antenna using electromagnetic bandgap structure and varactor diodes Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200803
Ahmed S. Elkorany, Hesham A. Mohamed, Zeinab F. Elsharkawy, Demyana A. SaleebHeart shaped reconfigurable band notched UWB microstrip line fed monopole antenna using two mushrooms like electromagnetic band gaps (EBGs) loaded by two varactor diodes has been developed, examined and fabricated. The effect of EBG dimensions, on the notch frequency, was first examined. A notched frequency of 5.3 GHz is obtained when two square EBGs with rectangular slits are used with length equal

A voltageadjustable outputcapacitorless LDO regulator with splitlength current mirror compensation and overshoot/undershoot reduction Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200803
Kui Wen, Shubin Liu, Yongyuan LiAn outputcapacitorless lowdropout regulator (OCLLDO) using splitlength current mirror compensation and overshoot/undershoot reduction circuit are presented in this paper. At a supply of 1.5 V and a quiescent current of 8.2 µA, the proposed scheme can support a maximum load current of 50 mA. The proposed OCLLDO has a range of output voltage from 0.8 to 1.25 V with 1.5 V supply. The proposed regulator

An opampfree secondorder noiseshaping SAR ADC with 4 $$\times$$ × passive gain using capacitive charge pump Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200801
Pinyun Yi, Zhangming Zhu, Dengquan Li, Liang FangThis paper presents a compact and robust opampfree noise shaping (NS) successive approximation register (SAR) analogtodigital converter (ADC). The proposed NS SAR ADC adopts extra one passive feedforward path summing in realizing secondorder noise shaping with the minimum modification to a standard SAR. Compared with previous works, the noise sources of residue sampling and firstorder integration

Least squares linear phase FIR filter design and its VLSI implementation Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200722
Mansoor Khan, Shahrukh AghaIn this work we present least squares (LS) approach to design linear phase Finite Impulse Response (FIR) filter. Since the design of FIR digital filters is nonanalytic, we aim at ideal zerophase magnitude response and minimize the weighted error in passband and stopbands. The problem of least squares can then be solved noniteratively by solving system of linear equations. Solution of which yields

A reusable stage based reduced comparator count binary search ADC Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200717
Dipti, Sajai Vir Singh, Rohit Joshi, Prasanna Kumar Misra, Manish GoswamiA 4 bit reusable stage based asynchronous binary search analog to digital converter (ADC) with a smart switching network, and reduced comparator count is presented in this paper. The proposed ADC uses asynchronous logic to activate comparators sequentially while switching network is used to provide reference voltages for selected comparators. In the extended version, the 6bit ADC is designed using

A 40 μW–30 mW generated power, 280 Ω–1.68 kΩ load resistance CMOS controllable constantpower source for thermallybased sensor applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200716
Nikša Tadić, Alija Dervić, Milena Erceg, Horst ZimmermannA controllable constantpower source in 0.35 μm CMOS technology is presented in this paper. It is based on the resistive mirror method, and suitable for thermallybased sensor applications. Two versions have been developed and fabricated: a highvoltage design with a single supply of 10 V, and a lowvoltage design with a single supply of 3.6 V. The measured results for the high voltage (low voltage)

Hexagonal shaped fractal MIMO antenna for multiband wireless applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200708
K. Sumathi, M. AbiramiA hexagonal shaped fractal Multiple input Multiple Output (MIMO) antenna resonates to six different frequencies is presented. A dumbbell structure with hexagon shaped defected ground structure (DGS) is created in the ground plane. Two antenna elements sharing a common ground plane are positioned orthogonal to each other for better isolation. The antenna is designed, fabricated using FR4 substrate with

An analog correlator based CMOS analog front end with digital gain control circuit for hearing aid devices Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200703
Hyusim Park, Sungyong Jung, HoonJu ChungIn this paper, an analog correlator based analog front end with gain control circuit for hearing aid devices is designed and fabricated with 0.18 \(\upmu \mathrm{m}\) CMOS process. The proposed analog front end consists of an analog correlator comprised of a multiplier, an integrator, and a mixed mode variable gain amplifier. The analog correlator is utilized to ensure the low input referred noise

Analysis and investigation of CDBA based fractionalorder filters Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200703
Gagandeep Kaur, Abdul Quaiyum Ansari, M. S. HashmiIn this work, a new design of continuous time current differencing buffered amplifier based lowpass, highpass, bandpass, allpass and notch fractionalorder filters is reported. The design of proposed filters is based on the approximation of fractionalorder filters by using an appropriate integer order transfer function. Signal flow graph approach is used for the realization of fractionalorder

Performance analysis of SiGeHBTbased transimpedance amplifiers with nonconstant gainbandwidth technique Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200702
Pujan K. C. Mishu, Seungwoo Jung, Ickhyun SongThe performance of a transimpedance amplifier (TIA) can be enhanced by lowering the input impedance and applying the nonconstant gainbandwidth product (GBP) technique. In this paper, a TIA of utilizing both properties is presented and the performance of the conventional and the proposed TIAs is analyzed theoretically and experimentally. The lowered input impedance increases the operational bandwidth

A 0.35 Vto1.0 V synthesizable railtorail dynamic voltage comparator based OAI & AOI logic Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200701
Xiaocui Li, Ting Zhou, Yuxin Ji, Yongfu LiIn this letter, we present a twostage railtorail fully synthesizable dynamic voltage comparator. To improve the speed and mismatch performance of the NAND&NORbased synthesizable comparator, we have proposed to replace these logics with OAI&AOI logic gates, respectively. The comparator is implemented on CMOS 45 nm technology, operating with a supply voltage from 350 mV to 1.0 V. The proposed comparator

An evolutionarybased design methodology for performance enhancement of a foldedcascode OTA using symbiotic organisms search algorithm and g m /I D technique Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200701
Madhusmita Panda, Santosh Kumar Patnaik, Ashis Kumar Mal, Sumalya GhoshIn this paper, a new populationbased evolutionary technique namely symbiotic organisms search (SOS) optimisation algorithm is proposed to optimize the design variables of transistors used in analog circuit. Here length and width of the transistors are considered to be the design variables, the optimisation of which minimizes the inputreferred noise, total MOSFET area, and power consumption. This

A 12bit branching timetodigital converter with power saving features and digital based resolution tuning for PVT variations Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200629
Jian Sen Teh, Liter SiekThis paper presents a 12bit branching TimetoDigital converter (TDC) fabricated in a 40 nm CMOS technology. It composes of a 6bit coarse counter TDC, and a 6bit fine TDC. The fine TDC utilizes a proposed branching technique to interpolate between the phases of a 16stage gated ring oscillator, increasing its number of phases from 16 to 64. Therefore, the TDC resolution is improved to be 4 times

A highly programmable 60dB gain analog baseband circuit with DCoffset cancellation for shortrange FMCW radar applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200629
Dušan V. Obradović, Ðorđe P. Glavonjić, Dušan P. Krčum, Veljko R. Mihajlović, Ivan M. MilosavljevićThis paper presents a fully integrated analog baseband circuit with high reconfigurability intended for use in shortrange frequencymodulated continuouswave (FMCW) radar sensors. The fully differential baseband circuitry achieves maximum overall gain of 60 dB which is adjustable with a 3dB step. Secondorder highpass filter and fifthorder lowpass filter are incorporated in chain and possess tunable

A capacitorsplitting DAC switching scheme with high powerefficiency and low commonmode voltage variation Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200624
Hao Wang, Zhixin Chen, Wenming Xie, Tianwei Chen, Haiyan OuIn this letter, a capacitorsplitting switching algorithm for successive approximation register (SAR) analogtodigital converters is proposed. To achieve low power, the hybrid switching scheme is involved. The monotonic switching technique is used during the last bit cycle; for other bit cycles except the first one, the switching is based on MSB and the former determined bit. Besides, the commonmode

Investigation on the combined effects of variable Fermi energies and temperatures on the performance of multilayer graphene nanoribbon as interconnects Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200623
Himanshu Sharma, Karmjit Singh SandhaIn the present research, the Fermi energy and temperaturedependent performance of a multilayer graphene nanoribbon (MLGNR) in terms of signal delay and power delay product (PDP) at the global interconnect length for three different technology nodes (32 nm, 22 nm, and 16 nm) were investigated in detail. A Fermi energy and temperaturedependent equivalent single conductor (ESC) based on the analytical

Blind separation of ECG signals from noisy signals affected by electrosurgical artifacts Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200620
Kahina Bensafia, Ali Mansour, AbdelOuahab Boudraa, Salah Haddab, Philippe Ariès, Benoit ClementElectrocardiogram (ECG) signal monitoring is crucial in the operating room. During surgery, when using an electrosurgical unit (ESU), the ECG signal is corrupted by strong interference generated by the ESU, socalled Electrosurgical Artifacts (EAs). The objective of this study is to enhance the infected ECG signal and to remove the impact of the EAs. Motivated by the fact that the artifacts’ energy

94 GHz eightway power amplifier with high output power and poweradded efficiency in 90 nm CMOS Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200616
YoSheng Lin, KaiSiang LanA fourstage eightway CMOS power amplifier (PA) for 94 GHz radar sensor is reported. The PA constitutes a commonsource (CS) input stage, a CS first gain stage, a twoway CS second gain stage, followed by an eightway CS output stage using miniature triple Yshaped divider and combiner. Broadband πmatch input, interstage, and output networks are adopted for broadband impedance or power matching

Effectiveness of Taguchi and ANOVA in design of differential ring oscillator Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200615
Gaurav Kumar Sharma, Arun Kishor Johar, Tangudu Bharat Kumar, Dharmendar BoolchandaniIn this work, a new circuit of delay cell is proposed to design a wide tuning range differential ring oscillator (DRO). Statistical techniques of Taguchi design of experiments and analysis of variance (ANOVA) are used to optimize the performance parameters of the proposed circuit. Three levels and 3 factors of width (w1, w3 and w4) for various MOSFETs of delay cell, are considered as major performance

Openloop digital clock generator based VLSI architecture for electromagnetic interference reduction Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200611
P. Meenakshi Vidya, S. SudhaNowadays, the size of the hearing aid devices are reduced to make them invisible and function rapidly. As a result of these factors, an EMI is generated inside the chips. The general working principle of the hearing aid SoC is disrupted by this internal EMI. Thus, an open loop fractional dividers based alldigital clock generator is introduced in the proposed hearing aid SoC. The jitter is reduced

Compact and wideband microwave bandstop filter for wireless applications Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200610
Ahmed A. Ibrahim, Omar K. El Shafey, Mahmoud A. AbdallaCompact, tunable and wide band stop filter (BSF) for wireless application is presented. The proposed filter is composed of compact rectangular microstrip open loop resonator with stub loaded resonator as building blocks of the filter. First, two vertical lumped capacitors are inserted in the open loop resonator from top to bottom of the substrate at the place which has maximum electric field to decrease

Wideband FPGAbased digital modulator programming and practical validation techniques Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200609
Luiz A. Corrêa, Iago de A. Oliveira, Alvaro Augusto Machado de Medeiros, Alexandre B. dos Santos, Eduardo P. de Aguiar, Daniel D. SilveiraThis article discusses modern techniques of implementation of a wideband digital modulator in an FPGA kit for use in electrical engineering communications laboratory. Previous configurations proposed in literature present limitations, as lack of details about the methods used in the algorithm developed and test procedures. Those key details can help researchers to develop this modulator more effectively

A singleended low leakage and low voltage 10T SRAM cell with high yield Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200608
Nima Eslami, Behzad Ebrahimi, Erfan Shakouri, Deniz NajafiThis paper presents a low leakage power 10T singleended SRAM cell in the subthreshold region that improves read, write, and hold stability. While at low voltages, the writeability is increased by temporarily floating the data node, the read stability of the cell is maintained approximately as equal as the hold state by separating the datastorage node from the read bit line by using only a single

Phasedomain ADC with ∆modulation frequency tracking loop Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200608
Karama M. ALTamimi, Ezz ElMasry, Kamal ElSankaryThe principle of ∆modulation has been leveraged in timedomain to cancel the nonlinearity of voltage to frequency transfer function in VCObased ADCs. The proposed modulation technique features frequencytracking loop (FTL) to compensate for the imperfection of frequency nonlinearities and to eliminate the analog OpAmp. Injection locking is used to alleviate the mismatch effect between the feedforward

Design and implementation of higher order sigma delta modulator circuits using FPAA Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200608
Daisy Deenrii Roel, Manoj KumarIn this paper, the prototyping of 3rd order, 4th order, 5th order, and 6th order sigmadelta analog to digital converters (Σ∆ ADCs) has been presented. It summarily portrays the method implemented for configuration and reconfiguration of the proposed circuits by using Field Programmable Analog Array (FPAA). Their function was determined in the time domain at a constant 1 V supply voltages which is

Methodology for broadband matching of electrically small antenna using combined nonFoster and passive networks Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200606
Saadou Almokdad, Raafat Lababidi, Marc Le Roy, Sawsan Sadek, André Pérennec, Denis Le JeuneDecreasing the electric length of an antenna results in increasing its input reactance that becomes greater than its input resistance, resulting in a significant rise in its quality factor and in a drastic reduction of its potential operating bandwidth. For such small antennas, namely ESA for Electrically Small Antenna, passive matching is restricted by the gainbandwidth theory, providing narrow bandwidths

An inductorless CMOS broadband balun g m boosting LNA exploiting noise cancellation techniques Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200603
Tingting Han, Zhiqun Li, Mi TianThis paper presents a 100 MHz to 6 GHz broadband inductorless singletodifferential balun gmboosting lownoise amplifier (LNA) for multistandard radio applications. Two mechanisms of noise cancellation techniques have been innovatively introduced in this work. To achieve the wideband input matching, high gain, and low noise figure simultaneously, a feedforward thermal noise cancellation technique

A broken symmetry approach for the modeling and analysis of antiparallel diodesbased chaotic circuits: a case study Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200527
Leandre Kamdjeu Kengne, Herve Thierry Kamdem Tagne, Adelaide Nicole Kengnou Telem, Justin Roger Mboupda Pone, Jacques KengneThis paper focuses on the modeling and symmetry breaking analysis of the large class of chaotic electronic circuits utilizing an antiparallel diodes pair as nonlinear device necessary for chaotic oscillations. A new and relatively simple autonomous jerk circuit is used as a paradigm. Unlike current approaches assuming identical diodes (and thus a perfect symmetric circuit), we consider the more realistic

A 0.2 pJ/step open loop VCObased ADC with inverse R–2R preweighted linearization Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200523
Karama M. ALTamimi, Kamal ElSankaryAn open loop analogtodigital converter based on ring voltagecontrolled oscillator (VCObased ADC) is presented. By introducing the inverse R–2R preweighted frontend technique, the nonlinearities of the voltage to frequency conversion of the proposed VCO is kept less than 1% over railtorail input swing. Unlike prior approaches, this proposed method does not suffer from any stability issues or

Modeling and design of an ultra lowpower NEMS relays: application to logic gate inverters Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200522
Hatem Samaali, Fehmi Najar, Amar ChaalaneIn this work we propose a design based on a nanoelectromechanical relay acting as a logic gate inverter. The proposed inverter is made of a double cantilever nanobeam actuated by a fixed central electrode carrying the input signals. The static and dynamic behaviors of the ohmic nanoinverter gate are investigated using an electromechanical mathematical model that fully incorporates nonlinear form of

A 0.4 V, tailless, fully differential transconductance amplifier: an all inverterbased structure Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200521
Hassan Faraji BaghtashA tailless, fully differential transconductance amplifier is presented in this paper. The proposed structure arranges the inverters as a core amplifier blocks in an elaborate manner to achieve fully differential function with tailless power optimized elements. As the inverters are current push–pull structures, they reuse the bias current effectively to maximize the transconductance of block. The

An energyefficient switching scheme with low commonmode voltage variation and nocapacitorsplitting DAC for SAR ADC Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200511
Junhui Li, Xin Li, Linlin Huang, Jianhui WuAn energyefficient switching scheme with low commonmode voltage variation and simple capacitor array for successive approximation register (SAR) analogtodigital converters (ADCs) is presented. The proposed scheme adopts simple binary weighted capacitor array without capacitorsplitting, and consumes no switching energy in the first two comparison cycles. The behavioural simulation shows the proposed

Two implementations of fractionalorder relaxation oscillators Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200510
Omar Elwy, Amr M. AbdelAty, Lobna A. Said, Ahmed H. Madian, Ahmed G. RadwanThis work proposes general formulas for designing two different topologies of fractionalorder relaxation oscillators. One topology contains an Operational Amplifier and the other one relies on an Operational TransResistance Amplifier. The design procedure hinges on the general fractionalorder natural and step responses of RC, which is proved in this work depending on Mittag Leffler function. The

A 0.7 V 5 nW CMOS subbandgap voltage reference without resistors Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200510
Min Pan, Jiaye Xie, Lili PangA 0.7 V 5 nW CMOS SubBandgap voltage reference circuit without resistors is presented. The proposed circuits use a new complementarytoabsolutetemperature voltage generator to reduce the power consumption and area. The circuit consists of one single BJT and subthreshold transistors. The subBandgap voltage reference is implemented in a 0.18µm CMOS process. Measured results show that the reference

Digital calibration of pipelined ADC using Newton–Raphson algorithm Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200508
Ehsan Zia, Ebrahim Farshidi, Abdolnabi KosarianThis paper presents a new digital background calibration method to correct MDAC errors. The novelty of this research is to use Newton–Raphson algorithm in order to reduce the number of divisions as well as power in digital domain. This is achieved by combining the conventional slope mismatch averaging and linear approximation technique to compute the correction coefficient in fast iterative method

Clock delaybased design for hysteresis programming and noise reduction in dynamic comparators Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200430
Leila Khanfir, Jaouhar MouineSchmitt Triggers have found wide spread use in lowpower and thresholdbased applications such as peak detectors and spectrum analyzers. They are formed by comparators and feedback loops and exhibit hysteresis at nominal supply voltage. When using dynamic comparators, the periodic discharge of internal capacitors prior to each decision process cancels hysteresis. In addition, dynamic comparators produce

Resistorless current mode precision rectifier using EXCCII Analog Integr. Circ. Signal Process. (IF 0.925) Pub Date : 20200425
Rupam Das, Sajal K. PaulIn this paper, a new current mode precision rectifier circuit is proposed using a single EXCCII and two nMOS transistors. The novelty of the circuit is that it can provide all the possible rectified outputs, namely ± full wave as well as ± half wave simultaneously without any alteration of topology. Moreover, it has low input impedance and high output impedance, which is suitable for fully cascadable