In this paper, an analog correlator based analog front end with gain control circuit for hearing aid devices is designed and fabricated with 0.18 \(\upmu \mathrm{m}\) CMOS process. The proposed analog front end consists of an analog correlator comprised of a multiplier, an integrator, and a mixed mode variable gain amplifier. The analog correlator is utilized to ensure the low input referred noise

In this work, a new design of continuous time current differencing buffered amplifier based low-pass, high-pass, band-pass, all-pass and notch fractional-order filters is reported. The design of proposed filters is based on the approximation of fractional-order filters by using an appropriate integer order transfer function. Signal flow graph approach is used for the realization of fractional-order

The performance of a transimpedance amplifier (TIA) can be enhanced by lowering the input impedance and applying the nonconstant gain-bandwidth product (GBP) technique. In this paper, a TIA of utilizing both properties is presented and the performance of the conventional and the proposed TIAs is analyzed theoretically and experimentally. The lowered input impedance increases the operational bandwidth

In this letter, we present a two-stage rail-to-rail fully synthesizable dynamic voltage comparator. To improve the speed and mismatch performance of the NAND&NOR-based synthesizable comparator, we have proposed to replace these logics with OAI&AOI logic gates, respectively. The comparator is implemented on CMOS 45 nm technology, operating with a supply voltage from 350 mV to 1.0 V. The proposed comparator

In this paper, a new population-based evolutionary technique namely symbiotic organisms search (SOS) optimisation algorithm is proposed to optimize the design variables of transistors used in analog circuit. Here length and width of the transistors are considered to be the design variables, the optimisation of which minimizes the input-referred noise, total MOSFET area, and power consumption. This

This paper presents a 12-bit branching Time-to-Digital converter (TDC) fabricated in a 40 nm CMOS technology. It composes of a 6-bit coarse counter TDC, and a 6-bit fine TDC. The fine TDC utilizes a proposed branching technique to interpolate between the phases of a 16-stage gated ring oscillator, increasing its number of phases from 16 to 64. Therefore, the TDC resolution is improved to be 4 times

This paper presents a fully integrated analog baseband circuit with high reconfigurability intended for use in short-range frequency-modulated continuous-wave (FMCW) radar sensors. The fully differential baseband circuitry achieves maximum overall gain of 60 dB which is adjustable with a 3-dB step. Second-order high-pass filter and fifth-order low-pass filter are incorporated in chain and possess tunable

In this letter, a capacitor-splitting switching algorithm for successive approximation register (SAR) analog-to-digital converters is proposed. To achieve low power, the hybrid switching scheme is involved. The monotonic switching technique is used during the last bit cycle; for other bit cycles except the first one, the switching is based on MSB and the former determined bit. Besides, the common-mode

In the present research, the Fermi energy and temperature-dependent performance of a multilayer graphene nanoribbon (MLGNR) in terms of signal delay and power delay product (PDP) at the global interconnect length for three different technology nodes (32 nm, 22 nm, and 16 nm) were investigated in detail. A Fermi energy and temperature-dependent equivalent single conductor (ESC) based on the analytical

Electrocardiogram (ECG) signal monitoring is crucial in the operating room. During surgery, when using an electrosurgical unit (ESU), the ECG signal is corrupted by strong interference generated by the ESU, so-called Electrosurgical Artifacts (EAs). The objective of this study is to enhance the infected ECG signal and to remove the impact of the EAs. Motivated by the fact that the artifacts’ energy

A four-stage eight-way CMOS power amplifier (PA) for 94 GHz radar sensor is reported. The PA constitutes a common-source (CS) input stage, a CS first gain stage, a two-way CS second gain stage, followed by an eight-way CS output stage using miniature triple Y-shaped divider and combiner. Broadband π-match input, inter-stage, and output networks are adopted for broadband impedance or power matching

In this work, a new circuit of delay cell is proposed to design a wide tuning range differential ring oscillator (DRO). Statistical techniques of Taguchi design of experiments and analysis of variance (ANOVA) are used to optimize the performance parameters of the proposed circuit. Three levels and 3 factors of width (w1, w3 and w4) for various MOSFETs of delay cell, are considered as major performance

Nowadays, the size of the hearing aid devices are reduced to make them invisible and function rapidly. As a result of these factors, an EMI is generated inside the chips. The general working principle of the hearing aid SoC is disrupted by this internal EMI. Thus, an open loop fractional dividers based all-digital clock generator is introduced in the proposed hearing aid SoC. The jitter is reduced

Compact, tunable and wide band stop filter (BSF) for wireless application is presented. The proposed filter is composed of compact rectangular microstrip open loop resonator with stub loaded resonator as building blocks of the filter. First, two vertical lumped capacitors are inserted in the open loop resonator from top to bottom of the substrate at the place which has maximum electric field to decrease

This article discusses modern techniques of implementation of a wideband digital modulator in an FPGA kit for use in electrical engineering communications laboratory. Previous configurations proposed in literature present limitations, as lack of details about the methods used in the algorithm developed and test procedures. Those key details can help researchers to develop this modulator more effectively

This paper presents a low leakage power 10T single-ended SRAM cell in the sub-threshold region that improves read, write, and hold stability. While at low voltages, the write-ability is increased by temporarily floating the data node, the read stability of the cell is maintained approximately as equal as the hold state by separating the data-storage node from the read bit line by using only a single

The principle of ∆-modulation has been leveraged in time-domain to cancel the nonlinearity of voltage to frequency transfer function in VCO-based ADCs. The proposed modulation technique features frequency-tracking loop (FTL) to compensate for the imperfection of frequency nonlinearities and to eliminate the analog Op-Amp. Injection locking is used to alleviate the mismatch effect between the feedforward

In this paper, the prototyping of 3rd order, 4th order, 5th order, and 6th order sigma-delta analog to digital converters (Σ∆ ADCs) has been presented. It summarily portrays the method implemented for configuration and reconfiguration of the proposed circuits by using Field Programmable Analog Array (FPAA). Their function was determined in the time domain at a constant 1 V supply voltages which is

Decreasing the electric length of an antenna results in increasing its input reactance that becomes greater than its input resistance, resulting in a significant rise in its quality factor and in a drastic reduction of its potential operating bandwidth. For such small antennas, namely ESA for Electrically Small Antenna, passive matching is restricted by the gain-bandwidth theory, providing narrow bandwidths

This paper presents a 100 MHz to 6 GHz broadband inductor-less single-to-differential balun gm-boosting low-noise amplifier (LNA) for multi-standard radio applications. Two mechanisms of noise cancellation techniques have been innovatively introduced in this work. To achieve the wideband input matching, high gain, and low noise figure simultaneously, a feed-forward thermal noise cancellation technique

This paper focuses on the modeling and symmetry breaking analysis of the large class of chaotic electronic circuits utilizing an antiparallel diodes pair as nonlinear device necessary for chaotic oscillations. A new and relatively simple autonomous jerk circuit is used as a paradigm. Unlike current approaches assuming identical diodes (and thus a perfect symmetric circuit), we consider the more realistic

An open loop analog-to-digital converter based on ring voltage-controlled oscillator (VCO-based ADC) is presented. By introducing the inverse R–2R pre-weighted front-end technique, the nonlinearities of the voltage to frequency conversion of the proposed VCO is kept less than 1% over rail-to-rail input swing. Unlike prior approaches, this proposed method does not suffer from any stability issues or

In this work we propose a design based on a nanoelectromechanical relay acting as a logic gate inverter. The proposed inverter is made of a double cantilever nanobeam actuated by a fixed central electrode carrying the input signals. The static and dynamic behaviors of the ohmic nanoinverter gate are investigated using an electromechanical mathematical model that fully incorporates nonlinear form of

A tail-less, fully differential trans-conductance amplifier is presented in this paper. The proposed structure arranges the inverters as a core amplifier blocks in an elaborate manner to achieve fully differential function with tail-less power optimized elements. As the inverters are current push–pull structures, they reuse the bias current effectively to maximize the trans-conductance of block. The

An energy-efficient switching scheme with low common-mode voltage variation and simple capacitor array for successive approximation register (SAR) analog-to-digital converters (ADCs) is presented. The proposed scheme adopts simple binary weighted capacitor array without capacitor-splitting, and consumes no switching energy in the first two comparison cycles. The behavioural simulation shows the proposed

This work proposes general formulas for designing two different topologies of fractional-order relaxation oscillators. One topology contains an Operational Amplifier and the other one relies on an Operational Trans-Resistance Amplifier. The design procedure hinges on the general fractional-order natural and step responses of RC, which is proved in this work depending on Mittag Leffler function. The

A 0.7 V 5 nW CMOS Sub-Bandgap voltage reference circuit without resistors is presented. The proposed circuits use a new complementary-to-absolute-temperature voltage generator to reduce the power consumption and area. The circuit consists of one single BJT and sub-threshold transistors. The sub-Bandgap voltage reference is implemented in a 0.18-µm CMOS process. Measured results show that the reference

This paper presents a new digital background calibration method to correct MDAC errors. The novelty of this research is to use Newton–Raphson algorithm in order to reduce the number of divisions as well as power in digital domain. This is achieved by combining the conventional slope mismatch averaging and linear approximation technique to compute the correction coefficient in fast iterative method

Schmitt Triggers have found wide spread use in low-power and threshold-based applications such as peak detectors and spectrum analyzers. They are formed by comparators and feedback loops and exhibit hysteresis at nominal supply voltage. When using dynamic comparators, the periodic discharge of internal capacitors prior to each decision process cancels hysteresis. In addition, dynamic comparators produce

In this paper, a new current mode precision rectifier circuit is proposed using a single EXCCII and two nMOS transistors. The novelty of the circuit is that it can provide all the possible rectified outputs, namely ± full wave as well as ± half wave simultaneously without any alteration of topology. Moreover, it has low input impedance and high output impedance, which is suitable for fully cascadable

Networks on-chip (NoCs) interconnect complex parallel applications on multiprocessors systems-on-chip. In order to rapidly evaluate NoCs, designers replace processing elements by communication traces on simulations. However, trace-based simulations have low accuracy due to the lack of information about packet dependence. The methods to obtain packet dependence require running multiple simulations or

As VLSI design moves into ultra-deep-submicron technologies, timing margins added to the clock period are mandatory, to ensure correct circuit behavior under worst-case conditions. Timing resilient architectures emerged as a promising solution to alleviate these worst-case timing margins. These architectures allow improving system performance and reducing energy consumption. Asynchronous systems, on

The complementary metal oxide semiconductor technology, CMOS, is reaching its physical limitations, as the transistors’ feature size decreases. A promising alternative is the nanomagnetic logic technology (NML), a paradigm of field-coupled nanocomputing. This technology applies single domain nanomagnets to implement digital logic with switching energies that are orders of magnitude lower than a CMOS

This paper describes a two-way time interleaved 12-bit SAR ADC with 6-bit MSBs sharing technique. The proposed 12-bit SAR ADC consists of two SAR ADCs connected in parallel, so that the sampling rate can be doubled. The first 12-bit SAR ADC is employed to determine the 12 bits and the second 12-bit SAR ADC utilizes the upper 6-bits of the first one, so that it can determine the lower 6-bits and save

In this study, we design two-way binary-Gray codes encoding/decoding circuit. Two-way means that the circuit can be function programmed as either binary-to-Gray or Gray-to-binary code transformations. A self-checking capability is also embedded in circuit design to enhance the function reliability. The proposed circuit will automatically detect the error due to single-fault occurred in chip internal

Physically unclonable functions (PUF) are digital fingerprints which generate high entropy, temper-resilient keys and/or chip-identifiers for security applications. When considering the miniaturized hardware development for the Internet of Things (IoT), security is of high importance. In this case, PUF designing using SRAM or D flip-flops are quite common but with compromised uniqueness due to the

Robotic hands tend to have a high number of sensors and actuators in a small space, whose supervising and control must be performed at the same time with precision and, in some cases, at high speed. Usually, a grid of Micro-Processors-Units or Micro-Controller-Units (MCUs) is employed to solve this problem, given the ease of programming. However, this solution can carry some drawbacks like the necessity

A 60–113 GHz down-conversion mixer in 90 nm CMOS is demonstrated. The mixer adopts an RL core IF load, which is based on the series of a peaking inductor (L) and a parallel combination of the cross-coupled PMOS transistors (CCPT) and the diode-connected NMOS transistors (DCNT), i.e. L-CCPT–DCNT-based core IF load. Conversion gain (CG) can be significantly enhanced due to the increase of load impedance

This paper presents a generic SPICE model for threshold current controlled memristive devices. This work relates to mathematical development to allow this kind of behavior and it exhibits its relationship with the equivalent circuit adopted to achieve this goal. The operating logic is described and the code for its computational implementation is presented and explained. The functionality of the model

This paper covers the design, characterization and calibration of stress sensors useful to measure the in-plane stress at the surface of integrated circuits. Each sensor is based on piezo-FET current mirrors aligned in four different directions; the mismatch in the current output in each mirror is related to the stress aligned with the device, then, the changes in the output currents can be used to

This research article introduces generalized design procedure for incremental/decremental memcapacitor using analog active device that brings a charge controlled floating memcapacitor emulator. The demonstration of generalized model using Dual X current conveyor differential input transconductance amplifier (DXCCDITA) as an analog active device comes with grounded capacitor and single resistor. The

This paper presents a wake-up circuit for battery-assisted passive (BAP) RFID applications. The circuit is composed by a differential envelope detector and a comparator with a systematic offset. The differential RF signal envelope detector and the comparator are designed to increase the wake-up circuit sensitivity and to have low power consumption, improving battery lifetime. The wake-up circuit was

This paper presents a 1 MHz PVT compensated dual phase relaxation Oscillator. The oscillator core employs a current controlled voltage bias replica circuit to limit the charging of capacitor. Furthermore, the current starved schmitt trigger circuit is employed in oscillator in place of conventional power consuming comparators. They also provide stable switching threshold voltage across temperature

This paper presents a linear sampling switch for low-voltage successive-approximation register (SAR) analogue-to-digital converters (ADCs) operating at a frequency of tens of MHz. The proposed switch employs a bootstrapped transmission gate, where the bulk voltages are generated internally to minimize variations in the threshold voltage of transistors with input signal amplitude. Thus, ensuring almost

In this paper, we improved the error vector magnitude (EVM) performance of six-port receiver using a low noise amplifier (LNA) bias control algorithm based on analyzing the correlation between normalized output DC offset voltage and EVM relative to input radio frequency (RF) power variation. In contrast to the other works published in the literature, we consider test setup through which the software

Biopotential amplifier (BPA) remains one of the most crucial blocks for the successful implementation of any of the biomedical systems. However, design of a BPA remains challenging owing to most of the topologies reported in literature displaying high values of noise, consuming high value of power and working in limited range of bandwidth. Thus, circuit topologies capable of providing an optimum and

In this paper for the first time a catalogue of linear voltage-controlled fractional-order oscillators employing multiplication-mode current conveyor (MMCC) have been systematically derived using state variable approach. The work also includes detailed relevant analysis of the derived oscillators. Furthermore, three special cases are considered for each of the derived oscillators. Non-ideal analysis

This paper presents an experimental study on using analytical design equations in the particle swarm optimization (PSO) for the automatic sizing of multi-stage operational amplifiers (opamps). Differing from the existing research, this work incorporates design equations in the PSO search process in attempt to reduce the search space dimensionality and the number of PSO iterations without sacrificing

In this paper, a new energy-efficient sample and hold (S/H) circuit based on the proper combination of the Miller-effect and double-sampling technique is presented in the Carbon Nanotube Field Effect Transistor (CNTFET) technology. In order to improve the accuracy and increase the input dynamic voltage range, a new CNTFET-based linearized switch circuit is introduced to be utilized as both the input

VLSI floorplan optimization problem aim to minimize the following measures such as, area, wirelength and dead space (unused space) between modules. This paper proposed a method for solving floorplan optimization problem using Genetic Algorithm which is named as ‘Lion Optimization Algorithm’ (LOA). LOA is developed for non-slicing floorplans having soft modules with fixed-outline constraint. Although

A new circuit of delay cell for differential ring oscillator (DRO), to generate wide tuning range, has been proposed. Two architectures of DRO: 3 stage and 4 stage, have been designed and simulated under the power supply constraint of 1.1 V, using GPDK 45 nm CMOS technology. Dual voltages are used to control the tuning frequency range in 3 stage DRO whereas single voltage control is used in 4 stage

In recent years, an increasing interest has been devoted to the discovery of new chaotic systems with special properties. In this paper, a novel and singular 3D autonomous system without linear terms is introduced. The singularity of the model is that it is dissipative, possesses rotation symmetry and line of equilibria thus displays complex dynamics. The nonlinear behaviour of the introduced model

Due to the technological advancements, the three dimensional Integrated Circuits become the most popular technology. But it has the major drawback of increased time consumption as well power consumption. This happens because of the increased wire length and routing path for connecting the components in chip. Thus it is essential to reduce the wire length for the purpose of enhancing the circuit speed

This paper studies the effect of amplitude and phase mismatch on the power conversion efficiency of differentially-drive rectifiers employing cross-coupled MOSFETs. The analysis begins by defining the different operational regions of the differential rectifier and how the common-mode interference resulting from amplitude and phase mismatches affects the symmetrical operation of the rectifier. A mathematical

Abstract An autonomous passive–active integrators oscillator with anti-parallel diodes is proposed and analysed in this paper. It consists of anti-parallel diodes and two main blocks: A second-order passive RLC integrator and a first-order active RC integrator. The existence of two Hopf bifurcations is established during the stability analysis of the unique equilibrium point. For a suitable choice

In this paper, plus-type differential voltage current conveyor based two voltage-mode (VM) analog filters with high input impedance properties yielding easy cascadability with other VM circuits are proposed. The first proposed filter can simultaneously provide all the second-order universal filter responses except all-pass one, and employs only grounded passive elements that are canonical in number

In this paper, a method for designing output matching network is proposed. The impedance matching idea is based on the sufficient condition of the ideal transistors. At this condition, the improved terminal load accommodates to the transistor load at the variation of the input power, which simplifies the design process and increases the matching accuracy. For verification, a Doherty power amplifier

Abstract A simple energy-efficient switching procedure is proposed to reduce the total number of switches and facilitate the capacitors matching requirements in SAR ADCs. The main idea is that the coupling capacitor (CC) is utilized as the same as the unit one, which is applied for LSB charge production. After the reset phase, only the MSB capacitor is connected to the input potential, while the other

Abstract The publish-subscribe programming model has been an alternative to the design of data-intensive distributed applications in many domains. Recently, this model has been ported to the domain of Multiprocessor Systems-on-Chips, in which applications must use the underlying Network-on-Chip communication infrastructure effectively due to restrictions on the architecture such as low power consumption

Abstract Deep Convolutional Neural Networks (CNNs) are the state-of-the-art systems for image classification due to their high accuracy but on the other hand their high computational complexity is very costly. The acceleration is the target in this field nowadays for using these systems in real time applications. The Graphics Processing Units is the solution but its high-power consumption prevents