Abstract This paper presents a 1 MHz PVT compensated dual phase relaxation Oscillator. The oscillator core employs a current controlled voltage bias replica circuit to limit the charging of capacitor. Furthermore, the current starved schmitt trigger circuit is employed in oscillator in place of conventional power consuming comparators. They also provide stable switching threshold voltage across temperature

Abstract This paper presents a linear sampling switch for low-voltage successive-approximation register (SAR) analogue-to-digital converters (ADCs) operating at a frequency of tens of MHz. The proposed switch employs a bootstrapped transmission gate, where the bulk voltages are generated internally to minimize variations in the threshold voltage of transistors with input signal amplitude. Thus, ensuring

Abstract In this paper, we improved the error vector magnitude (EVM) performance of six-port receiver using a low noise amplifier (LNA) bias control algorithm based on analyzing the correlation between normalized output DC offset voltage and EVM relative to input radio frequency (RF) power variation. In contrast to the other works published in the literature, we consider test setup through which the

Abstract Biopotential amplifier (BPA) remains one of the most crucial blocks for the successful implementation of any of the biomedical systems. However, design of a BPA remains challenging owing to most of the topologies reported in literature displaying high values of noise, consuming high value of power and working in limited range of bandwidth. Thus, circuit topologies capable of providing an optimum

Abstract In this paper, plus-type differential voltage current conveyor based two voltage-mode (VM) analog filters with high input impedance properties yielding easy cascadability with other VM circuits are proposed. The first proposed filter can simultaneously provide all the second-order universal filter responses except all-pass one, and employs only grounded passive elements that are canonical

Abstract In this paper, a method for designing output matching network is proposed. The impedance matching idea is based on the sufficient condition of the ideal transistors. At this condition, the improved terminal load accommodates to the transistor load at the variation of the input power, which simplifies the design process and increases the matching accuracy. For verification, a Doherty power

Abstract A simple energy-efficient switching procedure is proposed to reduce the total number of switches and facilitate the capacitors matching requirements in SAR ADCs. The main idea is that the coupling capacitor (CC) is utilized as the same as the unit one, which is applied for LSB charge production. After the reset phase, only the MSB capacitor is connected to the input potential, while the other

Abstract The publish-subscribe programming model has been an alternative to the design of data-intensive distributed applications in many domains. Recently, this model has been ported to the domain of Multiprocessor Systems-on-Chips, in which applications must use the underlying Network-on-Chip communication infrastructure effectively due to restrictions on the architecture such as low power consumption

Abstract Deep Convolutional Neural Networks (CNNs) are the state-of-the-art systems for image classification due to their high accuracy but on the other hand their high computational complexity is very costly. The acceleration is the target in this field nowadays for using these systems in real time applications. The Graphics Processing Units is the solution but its high-power consumption prevents

Abstract This paper presents a detailed design of an innovative feedback technique for boosting quality factor of discrete-time charge-sharing bandpass filters. The technique is verified in a 40-nm bulk CMOS implementation. The design was integrated in silicon as part of a complete super-heterodyne receiver. In the proposed strategy, cross-connected transconductors are used to boost the quality factor

Abstract This work presents an Operation Transconductance Amplifier with improved common mode rejection based in both Nauta’s and Vieru’s push–pull based OTAs operating at a 0.5 V power supply in the 180 nm CMOS process, with an additional biasing circuit that employs an adaptive body bias technique for calibration of output common mode voltage. Equal size CMOS push–pull pair inverter cells comprised

Abstract A successive-approximation-register (SAR) analog-to-digital converter (ADC) topology is presented, which optimizes the time distribution during the conversion. It is based on the semi-synchronous timing and uses a delay-looked loop (DLL) for clock generation. The absence of timing determined by analog delays allows an increase of the conversion speed compared to an asynchronous ADC using the

Abstract A new topology for the design of microwave narrow band-pass filters (NBPFs) based on the alternate right–left handed transmission line (TL) concept is proposed. The proposed NBPF is a three-stage structure which two LH stages and one RH stage are used. The proposed LH stage is implemented by a spiral complementary split ring resonator (spiral CSRRs) and an interdigital capacitor while for

Abstract This paper presents a secure and efficient substitution box (s-box) for speech encryption applications. The proposed s-box data changes every clock cycle to swap the input signal with different data, where it generated based on a new algorithm and a memristor chaotic system. Bifurcation diagrams for all memristor chaotic system parameters are introduced to stand for the chaotic range of each

Abstract Two sub-1-V MOSFETs only voltage reference designs, working in subthreshold region are proposed. They consume ultra-low power, exhibit high temperature and supply voltage independence, operate at sub-1-V supply and are suitable for fabrication using N-well CMOS technology. A voltage reference circuit (circuit-1) with dual-threshold voltage MOSFETs, which can provide a nominal output voltage

Abstract In literature double recycling folded cascode operational transconductance amplifier (DRFC-OTA) is realized to achieve higher transconductance. To realize preamplifier for bio-medical applications, it is necessary to design an OTA with lower noise. In this paper source degeneration is adopted for DRFC-OTA for further reduction of noise and is proposed. To access the efficacy of this technique

Abstract Two W-band CMOS elliptical baluns (i.e. balun-1 and balun-2) for 94 GHz image radar, and one miniature Ka-band CMOS square balun (i.e. balun-3) with short-terminal and input capacitor (for elimination of the inductive imaginary part of the input impedance at the input port) for 28 GHz 5G communication system are demonstrated. These baluns are applicable to a down-conversion mixer for conversion

Abstract This paper presents a wideband blocker-tolerant direct \(\varDelta \varSigma\) receiver (DDSR). Blockers are attenuated through selective input impedance matching and reduced gain design. The selective input impedance profile provides a low impedance at blocker frequencies enabling blocker attenuation, while the in-band impedance is boosted to matched condition through an up-converted positive

Abstract In this paper, we have proposed a highly linear Operational Transconductance Amplifier (OTA) with wide linear input range. The proposed OTA utilizes conventional source degeneration with an auxiliary differential pair which increases the linear range significantly by reducing the distortion components. The proposed OTA is targeted for current mode circuit applications including low-frequency

Abstract Phased array antennas are generally used for the inherent flexibility to beamforming and null-steering electronically. In the phased arrays the side lobes level (SLL) level is main problem which causes waste of energy or saturation of the receiver in the case of presence of the strong spatial blockers. In this paper, a weighting method was first used to reduce the level of SLL. However, this

Abstract This paper studies the effect of amplitude and phase mismatch on the power conversion efficiency of differentially-drive rectifiers employing cross-coupled MOSFETs. The analysis begins by defining the different operational regions of the differential rectifier and how the common-mode interference resulting from amplitude and phase mismatches affects the symmetrical operation of the rectifier

Abstract In this paper, a fully integrated sub threshold LC voltage controlled oscillator (VCO) is presented. A design methodology is also proposed to find the optimal parameters lowering the power consumption. This methodology has been applied to design oscillators for different frequency bands. Furthermore, an adaptive body biasing technique has been used to improve the startup constrains and allows

Abstract The design of CMOS analog integrated circuits presents low level of automation and still depends on the experience of the designer. The sizing procedure for low power applications is challenging, since transistors must be biased in the sub-threshold region, whose modeling is complex and few intuitive if second order effects in sub-micron technologies are considered. This paper presents an

Abstract In this paper a complex filter is presented where the shift in the frequency is obtained using a linear frequency transformation. The linear frequency transformation in the proposed design is implemented using a complex impedance. A complex impedance is also proposed in this paper using a Fully Balanced Second Generation Current Conveyor (FBCCII). The FBCCII design used in this paper consumes

Abstract In this paper, a very small size (20 × 14.75 mm2) triple-band multiple-input multiple-output (MIMO) microstrip patch antenna for WLAN (2.4/5.2/5.8 GHz) and WiMAX (2.5/3.5/5.5 GHz) wireless applications. The goal of this paper is to merge these two wireless standards into a single antenna that can be easily accommodated inside the devices operating in three different frequency ranges. The proposed

Abstract The technology nodes reduction enabled the emergence of NoC-based many-cores with dozens to hundreds of processing elements (PEs). Despite the processing power offered by a large number of processors and communication flexibility due to the adoption of NoCs, it is necessary to manage the many-core resources to ensure scalability. The execution of the management tasks requires a PE reserved

Abstract In this paper a fully integrated DC/DC converter for Thermal Energy Harvesting is presented, it is based on a parallel stages architecture as a technique to increase the conversion efficiency without using frequency or duty cycle modulation. The circuit was designed for a CMOS 180 nm process, with an active area of \(954\,\upmu {\mathrm{m}} \times 341\,\upmu {\mathrm{m}}\). The post-layout

Abstract As the technology node shrinks to the nanoscale, several challenges such as high power density have become more critical. One of the most effective methods for addressing these problems is utilizing spintronic devices based on magnetic tunnel junction (MTJ). Furthermore, approximate computing is an emerging paradigm for reducing the power consumption and design complexity in some applications

Abstract In this paper, a novel energy-efficient and area-efficient two-step asymmetric alternate monotonic switching procedure for successive approximation register ADCs, which consumes zero energy both in the first two comparison cycles and the proposed two-step-reset process, is presented. Due to the adoption of a multiplexing method after the MSB comparison, the connection between the sub-CDAC

Abstract In this paper, a constant-gm rail-to-rail operational amplifier is proposed. The transconductance variation due to the changes in the input common-mode voltage is reduced by controlling the tail-current of the parallel nMOS and pMOS input differential pairs. In addition, a bump-smoothing technique is applied to the circuit to decline sub-threshold effects in transition regions, and therefore

Abstract This paper presents a new highly-simplified and elegant technique for the mid-band analysis of the source-follower which is extended for the analysis of gm-boosted source-follower and a non-ideal drain-loaded source-follower. The accurate analysis of the drain-loaded source-follower is then applied to the superposition-based accurate differential-gain analysis of a mismatched non-ideal di

Abstract A ring oscillator is an important circuit used to evaluate the performance limits of any digital technology. The advantages of Graphene field effect transistor (GFET) over current CMOS technologies make it a prominent candidate for future high-performance electronics. In this paper, a GFET model is implemented in Verilog-A, and GFET design and analysis of a ring oscillator are performed using

Abstract This paper presents for the first time implementation of zig–zag and solenoidal on-chip inductors in standard and cost effective SOI-MUMPs fabrication process. The solenoidal inductor offers high Q-factor and inductance as compared to planar zig–zag inductor. Bonding wires are used to construct the top conductor loop of the solenoidal inductor. The inductors are also characterized at elevated

Abstract In this paper, we have designed and fabricated a novel microstrip diplexer. It has two quite close channels at 1.67 GHz and 1.88 GHz make it suitable for FDD schemes and GSM applications. The proposed structure includes two coupled meandrous open loop resonators which are coupled to spiral cells. An approximated LC model of the presented resonator is proposed and analyzed to give some information

Abstract MCML (MOS Current Mode Logic) based implementation producing fast response and compliment output at the same time gives an impetus to the researcher to replace Bulk CMOS. Moreover, tremendous challenges faced by bulk CMOS at channel lengths below 45 nm induces a need to strive for a technological replacement of silicon in years to come. This introduces a zest in designer's mind to look for

Abstract In this paper, a new energy-efficient sample and hold (S/H) circuit based on the proper combination of the Miller-effect and double-sampling technique is presented in the Carbon Nanotube Field Effect Transistor (CNTFET) technology. In order to improve the accuracy and increase the input dynamic voltage range, a new CNTFET-based linearized switch circuit is introduced to be utilized as both

Abstract This paper presents a 4-bit micro-electromechanical system (MEMS) digital attenuator with improved attenuation accuracy by surface micromachining. The attenuator is consisted of monoblack type radio frequency MEMS switches and TaN film resistors fabricated on a glass substrate to control the reconfigurable power within DC ~ 18 GHz. The simulation results revealed that the device had favorable

Abstract In this paper, the design of asymmetric cantilever radio frequency micro electromechanical system (RF-MEMS) capacitive shunt switch is presented. The analysis and design have considered for single meander, uniform serpentine and non-uniform serpentine asymmetric cantilever RF-MEMS capacitive shunt switches were proposed. The non-uniform serpentine meander cantilever structure shows better

Abstract In this study, the hardware implementation of a TRNG using an alternative post-processing technique is presented. ROs (ROs) are used as the noise source of TRNG and true randomness is obtained from the jitter. The use of an entropy pool composed of discrete-time chaotic systems (quadratic map, cubic map, Bernoulli shift map and tent map) is proposed as the post-processing technique for TRNG

Abstract In this paper, the design of low-noise, low-power transimpedance amplifier (TIA) is presented for a miniaturized amperometric based continuous blood glucose monitoring system for wearable devices. The proposed multi-stage cascode common source transimpedance amplifier circuit is designed and implemented in a 180 nm CMOS technology. It has been demonstrated that the proposed TIA shows a significant

Abstract This article focuses on the dynamics of a modified van der Pol–Duffing circuit (MVDPD hereafter) (Fotsin and Woafo in Chaos Solitons and Fractals 24(5):1363–1371, 2005) whose symmetry is explicitly broken with the presence an offset term. When ignoring offset terms, the system displays an exact symmetry which is reflected in the location of the equilibrium points, the attractor topologies

Abstract This paper provides the essential details of implementing 4-phase bundled data and speed independent asynchronous circuits on FPGAs. The required Xilinx synthesis tools including attributes, constraints and hardware implementation of basic asynchronous elements like Cgate, delay line, and handshaking modules are discussed. Finally, two design and implementation examples of asynchronous circuits

Abstract In order to miniaturize components, planar technology has become essential. For frequency characterization of integrated quadrupole devices, only network vector analyzers can be used, but these instruments cannot be employed for frequencies below a few MHz. At these frequencies, only the impedance-meter allows devices to be measured. But, this instrument only measures dipole devices. Thus

Abstract Because of being imprecision and existence of uncertainty in input variables to fuzzy systems, and also their easy implementation, fuzzy controllers are introduced as one of useful optimization tools in industry especially in DC motors. Given to the growth of controller systems usages in industry, use of optimization methods has been noticed in the recent years; so that improve precision and

Abstract An energy-efficient capacitor switching scheme is proposed for successive approximation register analog-to-digital converter. During the design process, the semi-resting DAC structure and charge characteristic of floating capacitor ensure significant energy saving. There is no switching power consumption in the first two comparison process. Compared with the conventional switching scheme,

Abstract VLSI floorplan optimization problem aim to minimize the following measures such as, area, wirelength and dead space (unused space) between modules. This paper proposed a method for solving floorplan optimization problem using Genetic Algorithm which is named as ‘Lion Optimization Algorithm’ (LOA). LOA is developed for non-slicing floorplans having soft modules with fixed-outline constraint

Abstract A multi-stage amplifier is a frequency compensated via a single and small MOSFET based capacitor. The idea reduces die occupation considerably since removes any passive elements in the compensation network. Also, a normal differential pair and a MOSFET based capacitor form compensation network and boost DC gain simultaneously. The proposed approach is symbolically described via MATLAB and

Abstract This paper describes a voltage mode third-order quadrature sinusoidal oscillator (TOQSO) based on operational transconductance amplifiers (OTAs). The proposed configuration uses three OTAs and three grounded capacitors. Outputs of two voltage mode sinusoids with 90° phase difference are found in the proposed oscillator circuit. The condition of oscillation and frequency of oscillation are

Abstract A novel CMOS transistor implementation of three stage amplifier is presented in this work. The floating gate metal oxide semiconductor (FGMOS) transistor current mirror is exploited here to minimize supply requirements and to overcome the bandwidth reduction due to FGMOS transistor, frequency compensation techniques have been applied in subsequent stages. This amplifier is useful for application

Abstract This paper investigated the improved voltage-controlled delay line (VCDL) suitable for edge-combining delay-locked loops and multiplying delay-locked loops (MDLLs). One of the most important factors in jitter production is to increase the number of delay cells. By generating more delays in each stage of VCDL, further delays with a certain coefficient are produced in each delay cell stage,

Abstract This paper proposes a full-transistor multilevel delay element (DE) implemented by 65 nm/1.8 V CMOS technology. 10 mV/LSB and 50 mV/LSB control voltages are employed to realize the fine-grain and coarse tuning for multilevel delay adjustment while maintain the duty cycle of input pulse. In physical design, a novel transistor array with a compact regularity layout is adopted to mitigate process

Abstract This paper presents a new pulse shaping technique to achieve an improved and optimized power spectral density for wireless body area network applications. A half sine-offset quadrature phase shift keying modulation is chosen to approach the standard demands on a direct modulation transmitter. Proposed technique is based on the direct multiplexing architecture and is implemented with nearly

Abstract In this paper for the first time a catalogue of linear voltage-controlled fractional-order oscillators employing multiplication-mode current conveyor (MMCC) have been systematically derived using state variable approach. The work also includes detailed relevant analysis of the derived oscillators. Furthermore, three special cases are considered for each of the derived oscillators. Non-ideal

Abstract Alternating current (AC) sources which provide currents in micro ampere ranges have become essential for testing of electronic components, simulation of sensors, eddy current analysis, small signal analysis of transistors, electro-cutaneous stimulation in therapeutics, current injection in medical imaging techniques etc. This manuscript proposes a precise voltage mode AC source for extremely

Abstract This paper presents an all-digital 1-1 MASH \(\Delta \Sigma\) time-to-digital converter (TDC) using time-mode signal processing. A cascode time adder with a raised inverter threshold voltage is proposed to minimize the deterministic timing error caused by the current mismatch of the discharge paths of the time adder. A differential time integrator consisting of a pair of identical single-ended

Abstract A high speed low power current-mode square-rooting/geometric-mean circuit is presented in this paper. The up-down topology with MOS translinear loop in sub-threshold is the basic building block of the proposed circuit which leads to lower supply voltage requirement and body effect issues. This design is also helpful to implement the square-rooting operation of a signal and geometric-mean of

Abstract This paper presents for the first time all the steps required in optimal design of carbon nano tube field effect transistor (CNTFET) based single stage operational transconductance amplifier and two stage operational amplifier using transconductance to drain current ratio (\(g_{m}/I_{D}\)) technique for low voltage and low power applications. As square law model failed to produce exact behavior

Abstract This paper presents a 4th-order low-pass continuous-time Diode-RC filter with 24 MHz cut-off frequency. The filter structure is based on the combination of positive (passive) and negative (using cross-coupled MOS transistors) cells to synthesize complex-conjugate-poles pairs. Moreover, the filter is designed and optimized to have high-linearity along all the filter pass-band. The filter exhibits

Abstract Physical unclonable function (PUF) and true random number generator structures are important components used for security in cryptographic systems. Random numbers can be generated for cryptography by using these two components together. In particular, it is desirable that these numbers be unpredictable, non-reproducible and have good statistical properties. This study presents the design of

Abstract This paper describes a readout IC (ROIC), which consists of a capacitively coupled instrumentation amplifier (CCIA) and a discrete-time delta–sigma modulator. An active high-pass filter is embedded in the ripple reduction loop to suppress the noise ripple amplitude due to chop modulation. To accommodate the input with large electrode offset, dc-servo loop (DSL) and a 6 bit capacitive DAC are