A digital pulse width modulation architecture (DPWM) along with digital proportional integral derivative (PID) controller to control the DC-DC converter is presented in this paper. Difference between the actual output voltage and the reference voltage is calculated as error value. The look up table is created for PID controller to store the duty cycle ratio and the error value of power converters.

Decimal multiplication is the most common operation in arithmetic applications. This paper presents an area-efficient digit-by-digit decimal multiplier using a modified binary-coded decimal digit multiplier. In general, a Binary-Coded Decimal (BCD) digit multiplier consists of two kinds of block, namely binary multiplier, and Partial Product Binary-to-Decimal (PPBD) converter. In the BCD digit multiplier

In aerospace applications, the conventional Static Random Access Memories (SRAMs) are facing high soft error problems like a single event upset. Several radiation-hardened based design (RHBD) like twelve-transistor (12T) Dice, 12T We-Quatro SRAM cells, etc., had been developed to address the soft error problems. But they all are consuming comparatively more total and static power with more delay and

This paper proposes a simple and effective feedback structure to implement the variable-Q band-pass filter. An effective variable-Q band-pass filter can be designed by using integral-plus-derivative in the feedback pass. The stability of the model is shown in both continuous and discrete-time systems. Also, we demonstrate that the model could indeed achieve the desired center frequency as a precise

With the advanced development of CMOS manufacturing process, the capacitive-array in the successive approximation register analog-to-digital converters (SAR ADCs) has become the dominant source of energy consumption and silicon area. This requires an immediate attention to design a more energy-efficient capacitive switching method while maintaining excellent linearity and noise rejection. A hybrid

This paper presents an original approach, using a harmonic balance optimization method, allowing to predict the maximum phase shift range that can be practically obtained for an array of N coupled oscillators. Indeed, unlike what is predicted by the theory, the proposed analysis allows to show that the maximum value of the phase shift decreases by increasing the number N of coupled oscillators in the

The Scalable extension of the High Efficiency Video Coding standard (SHVC) combines the large compression efficiency and high visual quality of HEVC with the possibility of encoding several different versions of the same encoded video in a single bitstream. However, this comes at the cost of a high computational complexity. In order to reduce the SHVC encoding time, an intra-prediction mode decision

A highly energy-efficient capacitor switching scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. The proposed switching scheme needs only two reference levels by using the merge-and-split technique, which eliminates the need of the extra reference voltage (Vcm). The switching procedure is performed on the simple binary weighted capacitor arrays without

A tunable high-frequency operational transconductance amplifier (OTA) is presented along with its application in the implementation of a Gm-C filter. The OTA is tuned by varying the negative resistance produced by a positive feedback at the output. Post-layout simulation results (using TSMC 90 nm CMOS technology and a 1-V supply voltage) show that the differential DC gain, common-mode gain and OTA

This paper presents a new ultra-wide band (UWB) CMOS low noise amplifier (LNA) with very high linearity and low power consumption for UWB wireless communication applications, where linearity is a big challenge, due to presence of interference and blocker signals, as well as the in-band harmonics of the desired signal components in the lower part of UWB band. The proposed LNA uses a new combination

Mismatches between sub-channels limit the dynamic performance of time-interleaved analog-to-digital converters (TI-ADCs). This paper proposes a correlation-based method of calibration for timing mismatches in M-channel TI-ADCs by using the cross-correlation between sub-channels of the output signals to estimate the temporal deviations. The output signal is calibrated by reducing the arbitrary order

This paper presents a new architecture for three-stage operational transconductance amplifiers (OTAs) with a class AB input stage to improve the slew rate. The nested Miller compensation scheme is utilized to stabilize the proposed OTA. A nonlinear current mirror in the first-stage is used to implement the class AB operation. Details of the proposed OTA are described and the circuit level simulation

This paper presents a compact reconfigurable elliptical shaped fractal patch (ESFP) antenna with elliptical shaped RF MEMS switch is used for satellite applications at X-band. The proposed work involves the incorporation of RF MEMS switches loaded using parasitic elements with ease of simpler implementation without using DC bias lines. The proposed antenna is integrated with two MEMS switches and reconfigurability

This paper analyzes the transient oscillation amplitude of the source injection coupled quadrature oscillator (SIC-QOSC). With the help of the Describing Function Method, we estimate an expression to describe the nonlinear behavior of the negative transconductor. Using the estimated expression, we obtain an accurate closed-form formula for the time-domain amplitude of the SIC-QOSC. The proposed formula

The present CMOS VLSI technology is facing some challenges like working in nano scale, device density, power dissipation, operating frequency, fast execution, which demands a proper alternative. Quantum dot Cellular Automata (QCA) is one of the feasible substitutes for the same. In QCA, clocking is the primary driving source of power, and the flow of information occurs with the effect of underlying

In the process of continuous miniaturization of devices, it is necessary to look for new devices which overcome the drawbacks of non-scalability and higher static power of metal oxide semiconductor field effect transistor (MOSFET). Fin-shaped field effect transistor (FinFET) is an important device which uses the concept of multi-gates and it is not only scalable but also dissipate lower power at lower

In low power VLSI circuit designs, power dissipation is one of the challenging issues which is associated with threshold voltage. The reduction of threshold voltage increases the subthreshold leakage current by increasing the leakage power dissipation which plays an important role in total power dissipation. Due to this leakage power issue, the devices which are operated by battery for a long time

The practical application for massive MIMO relaying system with a large number of antennas is considered a challenging problem. To solve this problem, a promising solution is to utilize double precision analog-to-digital converter (ADC) and digital-to-analog converter (DAC) at the relay. Depending on the additive quantization noise model, closed-form expression for system sum rate is analyzed. Furthermore

In order to suppress the spurious signal resulted from the reference leak and to decrease the oscillator jitter by using phase locked loop (PLL) loop band extension, a reference frequency multiplier that places a delay locked loop (DLL) in front of the PLL has been studied. However, a feedback circuit such as a DLL or an injection locked type voltage controlled oscillator must be used. In this paper

Time difference amplifier (TDA) is often used in time domain interconnection, computing and measurement. Gain and linearity control are two main design issues. To reduce the nonlinear distortion, a novel self-adaptive pulse shrink circuit is proposed for the SR-latch based time difference amplifier. The multi-stage self-adaptive pulse shrink unit can compensate for the gain error caused by the high-order

This paper presents a solution based on optimal PID coefficients including anti-wind up for buck converter presents using meta-heuristic algorithm and chaos theory. A hybrid algorithm is called chaotic based flower pollination algorithm is provided by combining flower pollination algorithm and chaos theory with different maps. Five different choatic maps are used in the aim of increasing the efficacy

This article reported patch antenna functioning at Wi- Fi and 5G bands. Wi-Fi band (2.4 GHz) is obtained by loading Epsilon Negative Transmission Line (ENGTL) metamaterials into the patch radiating at 5G band (3.5 GHz). To acquire Circular Polarization (CP) at 5G band, conventional square patch is embedded with poly fractals. The experimental and simulated data are in close proximity. The obtained

Hum noise such as power line interference is one of the critical problems in biomedical signal acquisition. Various techniques have been proposed to suppress power line interference, such as an N-path notch filter. The notch depth in the conventional N-path notch filter is limited by the number of paths. The previous 10-phase N-path notch filter circuit achieved deeper notch depth but has a problem

In this paper, a CMOS based precharged phase frequency detector (PPFD) with improved output characteristic for phase locked loop (PLL) has been proposed and analyzed. The proposed PFD minimizes the reset time to improve the output characteristics and works upto the frequency of 1.25 MHz–3.8 GHz. In addition, it has an advantage of precharged PFD which has low power consumption capability i.e., 285

A compact multiple-input–multiple-output antenna is presented for Ultra Wide Band (UWB) applications. The antenna consists of two separate modified elliptical patches, two separate ground planes including a triangular slot and a step slot for better accommodation of impedance matching, and also separate feed lines for each port. In this design, it has been attempted to isolate the ports by separating

The current state of the telecommunications market exhibits a high potential to absorb efficient innovations in wireless connectivity, especially those that can be applied to the Internet of Things and similar domains. Contributing in that direction, this paper describes the design and implementation of a fully differential impulse-radio ultra-wideband (IR-UWB) transmitter using pulse-amplitude modulation

Operational Transconductance Amplifiers (OTAs) are the most pivotal blocks in analog circuits and systems. With the emersion of catastrophic short channel effects for Complementary Metal Oxide Semiconductor (CMOS) transistors at deep nanometric regime, the microelectronics scientists have focused on designing ultra-miniature OTAs based on non-silicon materials. During the last few years, Gate-All-Around

This paper presents a two-stage tunable power amplifier (PA) fully-integrated in 130 nm CMOS process. This multi-band PA consists of reconfigurable input, interstage, and output matching networks in order to tune the center frequency in use. The proposed tunable power amplifier enables three different bands with center frequency of 900 MHz, 1450 MHz, and 1900 MHz. By switching these bands, the designed

In this paper, approximate adders were proposed for DSP processors. DSP processors are mainly composed of adders and multipliers at bottom level. The power is minimized in transistor level design. Proposed adders have less power dissipation when compared to existing approximate adders. Results have shown that the proposed adders have less PDP with more accuracy. The circuits were simulated in Cadence

In this paper, a one-to-one comparison of the logic performance is made between CMOS circuits built with bulk junctionless (JL) FinFETs and that with SOI JL FinFETs for three different technology nodes as per the ITRS roadmap. For such comparison: (i) the rise time and fall time are evaluated from the transient analysis of a CMOS inverter,(ii) the propagation delay per stage for a three-stage ring

A simple Cascaded double balanced mixer working at 2.4 GHz, for WLAN application was designed and using 90 nm CMOS technology. The proposed mixer incorprates minimum number of transistors in comparing with the gilbercell mixer. Staking LO stage just above the RF stage reducing the voltage headroom of mixer. Differential combination of RF stage has a common source node and the Differential combination

During the last decades we have witnessed the performance improvement and the aggressive growth of the complexity of integrated circuits (ICs). The progressive size reduction of transistors in recent technological nodes has allowed and even compelled IC designers to perform analog tasks in the digital domain, increasing the demand for analog-to-digital converters (ADCs). This work presents the design

By utilizing frequency translational resistive feedback, a recently proposed blocker current-cancelling wideband receiver (Lenka and Banerjee in IEEE Trans Very Large Scale Integr Syst 27(5): 993–1006, 2019), tolerates 0-dBm blockers beyond 40 MHz offset with little degradation in performance. However, like most wideband receivers, the architecture is far less tolerant to “harmonic blockers”, that

In this article, a tunable lowpass filter (LPF) with a hexagonal stepped impedance resonator and multi open stubs is designed. The − 3 dB cut-off frequency for the proposed LPF is 2.2 GHz. Insertion loss (IL) and return loss (RL) in the passband zone are 0.3 dB and 15 dB, respectively. The frequency response slope (roll-off rate) for the proposed LPF is very sharp and equal to 142.4 dB/GHz. The tuning

Ternary Content Addressable Memory (TCAM) device is integrated with Static-Random Access Memory unit to attain high production at a lesser cost. Moreover, the TCAM searching device performs faster parallel searching of whole memory in the entire time. Also, TCAM is constrained by its large area of the cell, extensive active state leakage current, and high power consumption for searching. In this present

A compact and novel fractal dual band notched UWB antenna with time domain characteristics is presented. A tapered microstrip fed circular fractal radiating patch along with a novel semi circular defected ground structure produce − 10 dB bandwidth from 3.73 to 16.7 GHz. The proposed antenna is a miniature size of 16 × 21 mm2 and is printed on FR-4 substrate with two high frequency notched bands from

The never-ending demands for battery-powered applications are driven by technological advances in the field of low power digital CMOS circuits. The voltage level shifters are crucial primitives for Systems-on-Chip (SoC) applications and systems operating with different voltage domains. In this article, three single supply energy-efficient low-power voltage level shifters are proposed that are suitable

A low-voltage and low-power current mode rectifier based on dynamic threshold MOS (DTMOS) transistor is proposed in this paper. The suggested one input–two output rectifier architecture provides full-wave rectification and half-wave rectification. Full-wave rectifier consists of only 6 MOS transistors (excluding 1 MOS transistor in half-wave rectifier part) and is designed without the necessity of

As technology advances, circuit density and complexity increases in integrated circuits which make the devices vulnerable to different types of manufacturing defects. In such cases, even the occurrence of a fault may be critical. Hence, ensuring Static random access memory (SRAM) reliability and quality with high priority is essential. In this paper, an innovative approach to SRAM testing—wavelet-based

Two voltage-mode topologies single input multi-output universal fractional filters with high input impedance are proposed. The proposed analog filters consist of three DVCC+ blocks, two grounded capacitors and two resistors targeting the minimum passive elements. The proposed topologies provide a realization for all standard fractional filter functions (HP, LP, BP, AP and notch filter). The effect

In this paper, 2 efficient reverse converters are introduced for the four-moduli set {2n−1, 2n–1, 2n−1–1, 2n+1–1} which offers a high speed arithmetic unit due to its balanced modulus in the form of 2 k and 2 k–1. The proposed converters are designed in two-level architecture. ROM free and adder base structures are the advantages of the proposed converters which result in efficient implementation in

This paper proposes a three-level buck converter utilizing a Digital-to-Analog Converter (DAC)-based flying capacitor voltage control technique, which controls the voltage on a flying capacitor with a differential difference amplifier and common mode feedback circuit for stable operation. Employment of the DAC-based flying capacitor voltage control circuit allows the proposed circuit to compensate

This paper describes a pioneering methodology to design, optimize, and reduce the total gate area of robust Operational Transconductance Amplifiers (OTAs). The Single-Ended Single-Stage (SESS) OTA has been chosen to validate the proposed technique by using the 180 nm planar Complementary Metal-Oxide-Semiconductor (CMOS) Integrated Circuits (ICs) technology. The Electronic Design Automationtool, named

Recently, second generation voltage conveyor (VCII)-based transimpedance amplifiers (TIAs) have begun to find their way in different applications, among which, silicon photomultipliers (SiPMs) interfacing circuitry. There are many advantages which make VCII-based TIAs attractive over conventional circuits: the intrinsic low impedance at VCII current input Y port is very helpful to mitigate the effect

In this paper, two programmable operational transconductance amplifiers (POTAs)—one using bulk driven attenuator (BDA) and another using programmable current mirror (PCM) are proposed in order to achieve low-Gm and high dynamic range. These OTAs are denoted as BDA-POTA and PCM-OTA respectively and are realized using composite transistors operated in the subthreshold region. The pseudo resistor is used

A high energy-efficiency and low-area switching method is proposed for the successive approximation register analog-to-digital converters. In the proposed scheme, the threshold voltage for comparison is derived from the charge sharing technique and using a voltage source connected to the bottom plates of the digital-to-analogue converter (DAC) capacitors. The switching method achieves an average DAC

A compact and wideband microstrip rat-race coupler employing two-section ring and artificial transmission lines (ATLs) is reported in this paper. The bandwidth is highly improved by using a two-section rat-race coupler. The physical size of the planar circuit is reduced based on the substitution of the microstrip line with an ATL. The area of the proposed design footprint is 35% of the area of the

Current radio communication systems that adopt amplitude and phase modulations demand high linearity and high efficiency. The cascade connection between digital baseband pre-distorter (DPD) and power amplifier (PA) can be a cost-effective solution to guarantee the required linearity without compromising the efficiency. In the design of a DPD for a single band PA, direct learning can be used to extract

Pulse width modulation (PWM) is widely used in different applications. PWM transforms the information in the amplitude of a bounded input signal into the pulse width output signal without suffering from quantization noise. The frequency of the output signal is usually constant. In this paper, the new PWM system with frequency changing (PWMFM) is described. In such PWMFM the pulse width and also the

Varying a supply voltage using a DC-to-DC converter can significantly improve the efficiency of RF power amplifiers (PAs) for low-power RF transceivers. However, intrinsic switching noise from a conventional DC-to-DC converter operating in fixed Pulse-Width Modulation (PWM) can affect the system performance since the spectral components in the switching noise are confined in the fundamental switching

Astrocytes, also described as astroglia, are characteristic star-shaped glial cells in the brain. The important roles of astrocyte such as extracellular regulation, synaptic information regulation, neuronal synchronization and feedback to neural activity, makes the astrocytes play a vital role in the brain disease. This paper investigates the neuron–astrocyte interaction system for evaluating the network

While CMOS scaling is currently reaching its limits in power dissipation and circuit density, the analogy between biology and silicon is emerging as a solution to ultra-low-power signal processing. Urgent applications involving artificial vision and audition, including intelligent sensing, appeal original energy efficient and ultra-miniaturized silicon-based solutions. While state-of-the-art is focusing

This paper presents the design and analysis of a millimeter-wave LNA-mixer, which adopts a low-noise single-to-differential conversion balun with low phase (gain) imbalance, using a common-source and a common-gate stage. Each stage employs a cascode transistor with inductors in the gate and source for improving noise, gain, and bandwidth performance. A new transformer-based network is proposed for

This study presents an automated high-accuracy optimization approach for designing high-performance radio frequency high power amplifiers (HPAs). The amplifier is designed by applying a top-down pruning optimization approach that automatically converts the given HPA with lumped elements (LEs) to the HPA with distributed elements (DEs). Firstly, the lumped element HPA is designed based on a bottom-up

Optimizations have gained much consideration from the researchers working in the domains of analog and radio frequency (RF), recently. Dealing with highly nonlinear behavior of active components and aiming to meet design specifications are common issues in all nonlinear circuit designs. As a consequence and accordingly, many studies have been conducted on diverse optimization methods and algorithms

A 6-bit hieratical time-to-digital (TDC) architecture suitable for time-based ADC circuits is presented in this paper. The design consists of similar stages at which each stage recovers one bit. Using the proposed architecture, the total number of bits can be increased without complicating the design as in other conventional TDC architectures. A 6-bit 1.3 Gb/s TDC circuit has been designed and simulated

In this paper, a quasi-asymmetric Doherty power amplifier (PA) is designed without load modulation using the GaAs 0.25 µm pHEMT technology to reach an enlarged output power back-off (OPBO) with circuitry solutions in order to overcome technology restrictions. To prevent power leakage in auxiliary PA (PAaux) due to its extremely low off-state impedance (Zoff), a Wilkinson power combiner is added to

Near-field inductively coupled wireless power transfer (WPT) system has been extensively utilized for brain implant applications. Still, the efficient and reliable delivery of power is challenging as the received power varies due to different variabilities between the transmitter (TX) and the receiver (RX) coils. A closed-loop adaptive control system utilizing load shift keying, designed in the 0.5 µm

Increased parasitic components in silicon-based nanometer (nm) scale active devices have various performance trade-offs between optimizing the key parameters, for example, maximum frequency of oscillation (\(f_{max}\), gate resistance and capacitance, etc. A common-source cascode device is commonly used in amplifier designs at RF/millimeter-wave (mmWave) frequencies. In addition to intrinsic parasitic

This paper presents a novel co-optimization configuration to simultaneously improve phase noise and FoM in order to solve the long-existing issue of excellent phase noise and mediocre FoM in the light of GaAs technologies. Considering traditional GaAs based Colpitts/class-C VCOs, a first step is taken with the introduction of noise shifting structure while a second step is carried out with the presentation