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This paper presents a two-way time-interleaved (TI) 7-bit 2-GS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 28 nm CMOS. The design achieves wideband operation with an effective resolution bandwidth (ERBW) in the 3 rd Nyquist zone. The converter’s front-end employs current integrating (CI) sampler that provide both buffering and anti-alias (AA) filtering at low power

N-path commutated capacitive networks provide a practical solution to implement highly sought on-chip high-Q filtering applications in which the use of lumped inductors is undesirable due to their significant footprints and low Q-factors. Recently, it has been also revealed that N-path networks can also exhibit other interesting functionalities, such as nonreciprocal phase-shifting and ultra-wideband

This article presents a high temperature model for gallium nitride (GaN) high electron mobility transistor (HEMT) on silicon carbide (SiC). The proposed model for the channel resistance $\text {R}_{\text {ds}}$ is based on an empirical nonlinear model. The model is applied to design a resistive mixer of a high temperature transceiver for downhole communications through a systematic approach and estimate

This work demonstrates a Continuous-Time (CT) Ladder filter using transconductance amplifiers as an approximate delay stage implemented on a large-scale Field Programmable Analog Array (FPAA) and characterized on an SoC FPAA. We experimentally demonstrate a reprogrammable CT Analog linear-phase filter by utilizing the ladder filter delay element and Vector-Matrix Multiplication (VMM) both compiled

In this paper, a fully-synthesizable digital-to-time (DTC)-based fractional- ${N}$ multiplying delay-locked loop(MDLL) is presented. Noise and linearity of synthesizable DTCs are analyzed, and a two-stage synthesizable DTC is proposed in which a path-selection DTC is used as the coarse stage and a variable-slope DTC is used as the fine stage. To calibrate the DTC nonlinearity, a highly robust zero-order

This paper presents a low-area and low-power consumption CMOS differential current controlled oscillator (CCO) for neuromorphic applications. The oscillation frequency is improved over the conventional one by reducing the number of MOS transistors thus lowering the load capacitor in each stage. The analysis shows that for the same power consumption, the oscillation frequency can be increased about

An analytical approach to evaluate performance of analog integrated circuits and make a comparative study in different technology nodes is presented. To provide closed-form solutions, this article proposes using $\mathscr {C} = \text {C}/\text {I}_{\text {DS}}$ as an independent design variable, where C refers to any physical or parasitic capacitance associated with a Field-Effect Transistor (FET)

This paper presents a single-coarse dual-fine architecture that improves energy-efficiency of pipelined-SAR analog-to-digital converters (ADCs). A coarse and fast sub-ADC is used to quantize the most significant bits (MSBs), which are encoded with a proposed residue transformation method to control the residue generation of the first stages in two fine channels. The residue voltages generate on the

Analog integer order notch filters (IONF) are practically realised by using two or more capacitors. If the dissipation factor of capacitors (used in the IONF) increases then the overall order of the circuit reduces. Reduction in the order causes attenuation-loss at the notch frequency. Once the order reduces, the loss can only be compensated by reducing the quality factor of the IONF circuit, which

A novel 4T2C ternary embedded DRAM (eDRAM) cell is proposed for computing a vector-matrix multiplication in the memory array. The proposed eDRAM-based compute-in-memory (CIM) architecture addresses a well-known Von Neumann bottle-neck in the traditional computer architecture and improves both latency and energy in processing neural networks. The proposed ternary eDRAM cell takes a smaller area than

In this paper we propose a methodology to design high-speed, power-efficient static frequency dividers based on the low-voltage Folded MOS Current Mode Logic (FMCML) approach. A modeling strategy to analyze the dependence of propagation delay and power consumption on the bias currents of the divide-by-2 ( DIV2 ) cell is introduced. We demonstrate that the behavior of the FMCML DIV2 cell is different

A 28.8-GB/s 96-MB 3D-stacked SRAM is presented. A total of eight SRAM dies, designed in a 40-nm CMOS process, are vertically stacked and connected using an inductive coupling wireless link with a low-voltage NMOS push-pull transmitter that reduces the power of the link by 35% with a 0.4-V power supply. The SRAM utilizes an inverted bit insertion scheme that compensates for the degradation of the first

In recent years, convolutional neural network (CNN) has gained popularity in many engineering applications especially for computer vision. In order to achieve better performance, more complex structures and advanced operations are incorporated into neural networks, which results in very long inference time. For time-critical tasks such as autonomous driving and virtual reality, real-time processing

State-of-the-art approaches that perform root computations based on the COordinate Rotation Digital Computer (CORDIC) algorithm suffer from high latency in performing multiple iterations. Therefore, root computations based on the CORDIC algorithm cannot meet the strict latency requirements of some applications. In this paper, we propose a methodology for performing ${N}$ th root computations on floating-point

Deep convolutional neural networks (DCNNs) have achieved state-of-the-art performance in classification, natural language processing (NLP), and regression tasks. However, there is still a great gap between DCNNs and the human brain in terms of computation efficiency. Inspired by neural synaptic plasticity and stochastic computing (SC), we propose neural synaptic plasticity-inspired computing (NSPC)

Under the requirement of highly reliable encryption, the design of true random number generators (TRNGs) based on field-programmable gate arrays (FPGAs) is receiving increased attention. Although TRNGs based on ring oscillators (ROs) and phase-locked loops (PLLs) have the advantages of small resource overhead and high throughput, there are problems such as instability of randomness and poor portability

The increase in the number of edge devices has led to the emergence of edge computing where the computations are performed on the device. In recent years, deep neural networks (DNNs) have become the state-of-the-art method in a broad range of applications, from image recognition, to cognitive tasks to control. However, neural network models are typically large and computationally expensive and therefore

This paper addresses and experimentally demonstrates a programmable linear equation solver by analog computation. A set of differential equations using transconductance devices directly translated from circuit theory converges to the linear equation solution. These energy-efficient analog techniques are experimentally demonstrated in a configurable analog platform. The resulting analog linear equation

In this paper, the resilient control for linear discrete-time multi-agent networks subjected to unconfined cyber-attacks is investigated based on a data-driven method. Firstly, according to the evolution of the original network dynamics, a distributed data-driven estimation algorithm is presented. On this basis, a switching control law is proposed to solve the resilient consensus problem for the discrete-time

In this article, the sliding mode control (SMC) design is studied for a class of stochastic switching systems subject to semi-Markov process via an adaptive event-triggered mechanism. Network-induced communication constraints, semi-Markov switching parameters, and uncertain parameters are considered in a unified framework for the SMC design. Due to the constraint of measuring transducers, the system

As large-scale power systems are more and more closely integrated with remote transmission technologies, they are also affected by malicious factors in the cyber and physical layers when bringing convenience. In this article, we propose a novel adaptive event-triggered strategy and apply to the multi-area power system to deal with the load frequency control (LFC) problem with network-induced delay

This paper investigates the problem of dynamic event-triggered output feedback tracking control for a class of $p$ -normal nonlinear systems with unknown growth rate. To cope with the unknown growth rate imposed on the system nonlinearities, a dynamic gain technique is introduced and a constructive coordinate transformation is given. On the other hand, an event-triggered strategy combining with the

In this paper, the $\mathcal {H}_{\infty }$ stabilization problem is studied for discrete-time semi-Markov jump singularly perturbed systems (SMJSPSs) with repeated scalar nonlinearities. As the exact statistical information of the sojourn time or the mode transition is difficult to obtain, the case with only partial semi-Markov kernel information available is considered. Furthermore, introducing an

Aimed at the problem that the unmanned aerial vehicle (UAV) close formation cannot maintain its desired formation shape due to the wind field disturbances, a novel distributed adaptive control approach is proposed to counteract the lateral and forward distance errors caused by uncertain wind field disturbances. Firstly, based on the “leader-follower” model, an adaptive control law is designed to accurately

This paper investigates the regularity, non-impulsiveness, stability and admissibility of the singular fractional-order systems with the fractional-order $\alpha \in (0,1)$ . Firstly, the structure, existence and uniqueness of the time domain solutions of singular fractional-order systems are analyzed based on the Kronecker equivalent standard form. The necessary and sufficient condition for the regularity

This article is concerned with the issue of dynamic event-based non-fragile dissipative state estimation for a type of stochastic complex networks (CNs) subject to a randomly varying coupling as well as fading measurements, where the variation of coupling is governed by a Markov chain. To characterize the measurement fading phenomenon for different nodes, a Rice fading model is considered with known

Low-density parity-check (LDPC) code as a very promising error-correction code has been adopted as the channel coding scheme in the fifth-generation (5G) new radio. However, it is very challenging to design a high-performance decoder for 5G LDPC codes because their inherent numerous degree-1 variable-nodes are very prone to be erroneous. In this article, the problem is solved gracefully by developing

A reconfigurable parallel mixing subharmonic mixer (SHM)-based time-interleaved RF channelizer is proposed for fast spectrum sensing. The reconfigurable mixer operates as a double-balanced mixer (DBM), a double-balanced mixer with harmonic rejection (DBM&HR), and an SHM. In contrast to conventional spectrum sensing receivers to detect RF frequency bands by sweeping local oscillator (LO) frequencies

In the generalized spatial modulation (GenSM) multiple input multiple output (MIMO) system, each block of data bits is mapped to a set of spatially multiplexed (SMX) symbols and an index of transmit antenna combination (TAC) of active antennas. The difficulty for the GenSM MIMO receiver is to detect the SMX symbols and TAC index simultaneously. Recently, we applied the conventional sphere decoding

Multi-functional grid-tied inverters (MFGTIs) have been investigated recently for improving the power quality (PQ) of microgrids (MGs) by exploiting the residual capacity (RC) of distributed generators. Several centralized and decentralized methods have been proposed to coordinate the MFGTIs. However, with the increasing number of the MFGTIs, it demands a method with improved reliability and flexibility

A design methodology for making magnetic coupling wireless power transfer (MC-WPT) systems resonate at given frequencies is proposed in this paper. Proposing such a method not only can improve the energy efficiency against frequency splitting, but also can satisfy the requirement of frequency standards and then promote its industrial application. The method is based on eigenvalues configuration and

Because of the different working principles between conventional flyback and active-clamped flyback (ACF), the existing primary-side regulation (PSR) technology cannot be applied to ACF. And in order to achieve PSR of ACF, a low-cost digital sampling method based on the auxiliary winding of the transformer is proposed. In the conventional peak current mode (PCM) controlled ACF, the sampling resistor

The perturb & observe (P&O) algorithm is very popular for maximum power point tracking (MPPT) for solar photovoltaic (PV) systems. However, it has tracking problems during varying irradiations as well as the nuisance of oscillations around the maximum power point (MPP). This work introduces a circle center-line concept based P&O (CCCP&O) algorithm for MPPT, where, the concept of circle and its center

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This Special Issue is a collection of selected papers presented at the IEEE Asia Pacific Conference of Circuits and Systems (APCCAS) 2019 that was held in Bangkok, Thailand, November 11–14, 2019, and the IEEE International Conference on Electronics, Circuits and Systems (ICECS) 2019 that was held in Genova, Italy, on November 27–29, 2019. As the flagship conferences of the IEEE Circuits and Systems

Variable-rate transceivers, which adapt to the conditions, will be central to energy-efficient communication. However, fiber-optic communication systems with high bit-rate requirements make design of flexible transceivers challenging, since additional circuits needed to orchestrate the flexibility will increase area and degrade speed. We propose a variable-rate VLSI architecture of a forward error

Recent years have seen an increasing interest in the development of artificial intelligence circuits and systems for edge computing applications. In-memory computing mixed-signal neuromorphic architectures provide promising ultra-low-power solutions for edge-computing sensory-processing applications, thanks to their ability to emulate spiking neural networks in real-time. The fine-grain parallelism

Arithmetic precision scaling is mandatory to deploy Convolutional Neural Networks (CNNs) on resource-constrained devices such as microcontrollers (MCUs), and quantization via fixed-point or binarization are the most adopted techniques today. Despite being born by the same concept of bit-width lowering , these two strategies differ substantially each other, and hence are often conceived and implemented

This paper reports a half-rate bang-bang clock and data recovery (BBCDR) circuit supporting the trimodal (NRZ/PAM-4/PAM-8) operation. The observation of their crossover- points distribution at the transitions introduces the single-loop phase tracking technique. In addition, low-power techniques at both the architecture and circuit levels are employed to greatly improve the overall energy efficiency

Reconfigurable FETs (RFETs) are ambipolar transistors featuring the ability to conduct both electrons and holes, which is often achieved through the use of silicon nanowires or similar gate-all-around topologies. In this article, we present initial results for standard cell synthesis based on our planar RFET device, featuring top-down planar silicon based technology, lower fabrication complexity than

The divider controller can contribute significantly to the phase noise and spur pattern in the output of a nonlinear fractional- $N$ frequency synthesizer. A type of time-varying spurs caused by a MASH DDSM divider controller, termed wandering spurs, has been observed in simulations and measurements of real synthesizers. In this work, we propose and analyze several MASH-based divider controller architectures

This work is focused on the design of broadband amplifiers by exploiting dissipative reciprocal matching networks. Unlike the classical approach, which makes use of lossless reciprocal matching networks, there is no need to trade-off the gain flatness with the input/output matching levels. In this contribution the flat gain condition is obtained partially by exploiting the mismatch loss at a certain

This paper deals with the frequency design of lossless passive electronic filters under magnitude constraints. With the huge increase in design complexity for mobile applications, new systematic and efficient methods are required. This paper focuses on the direct synthesis approach, an historical design approach that has not been recently updated. It consists in directly synthesizing the $LC$ values

This work presents an approach for a complete noise analysis and optimization flow for switched-capacitor MEMS readout frontend circuits. The flow starts with an early noise evaluation on a high abstraction level. The evaluation is performed using analytical calculations as well as simulations in MATLAB/Simulink. The presented approach is applied to a charge-balanced readout circuit example, which

This work presents a low noise active pixel sensor. It uses one additional transistor compared to standard 4T pixel to obtain 1/f noise reduction and high conversion gain. 1/f noise is reduced by periodically switching the in-pixel source follower between depletion and inversion. The depletion state is achieved by re-configuring the source follower into a MOS capacitor and depleting the channel by

This article presents a small-area Bluetooth Low-Energy (BLE) transceiver (TRX) for short-range Internet-of-Things (IoT) applications in 65-nm CMOS. An integrated Radio-Frequency Input-Output (RFIO) circuitry embedded with transmitter/receiver (TX/RX) switch function and on-chip impedance matching is proposed. A hybrid-loop TRX structure based on a wide-bandwidth fractional-N digital phase-locked loop

Use of modern GPUs has been extended from traditional 3D graphic processing to computing acceleration of many scientific, engineering, and enterprise applications. In modern GPUs, on-chip memory capacity keeps increasing to support thousands of chip-resident threads. For example, a large register file is needed in order to efficiently process highly-parallel threads in single instruction multiple thread

The pass transistor logic (PTL) family enables compact circuits to reduce area and power consumption, but inter-stage inverters are required for signal integrity and complementary signals. Similarly, dual-gate ambipolar field-effect transistors are exceptionally logically expressive and provide a single-transistor XNOR operation, but numerous inverters are required to provide complementary signals

In this work, we present an asynchronous MTJ-CMOS hybrid system with extremely fine-grained voltage scaling (EFGVS) technique. The supply voltage of the system is turned on/off by asynchronous bundled-data handshake signals. The MTJ write circuit is variation robust, self-terminated and redundant-write preventing. Besides, EFGVS and asynchronous data driven handshake enhance the timing robustness by

In this paper, new digital predistortion (DPD) solutions for power amplifier (PA) linearization are proposed, with particular emphasis on reduced processing complexity in future 5G and beyond wideband radio systems. The first proposed method, referred to as the spline-based Hammerstein (SPH) approach, builds on complex spline-interpolated lookup table (LUT) followed by a linear finite impulse response

This paper proposes a distributed hierarchical control framework for energy storage systems (ESSs) in DC microgrid clusters, which achieves voltage regulation and current sharing for ESSs in each microgrid as well as the whole microgrid cluster. The primary control stage adopts a droop controller which only requires local information while the secondary control stage provides correction terms for ESSs

This paper is concerned with the fault reconstruction observer design problem with unknown nonlinearities, external disturbances and faults. First, a neural-network-based fault estimation approach is developed to generate the estimations of the actuator failures. In this design, the neural network strategy is utilized to approximate the totally unknown nonlinear functions. Then, an iterative adaptive

In this paper, the finite-time sliding mode control issue is studied for a series of semi-Markov jump systems subject to actuator faults, where an asynchronous control method is adopted to overcome the non-synchronous phenomenon between the system mode and controller mode. Additionally, the event-triggered protocol, which determines whether the transmission of data should be performed according to

The development, analysis, and experimental validation of an energy storage algorithmic scheme for performance optimization of resonant inductive power receivers are presented. Motivated by the crucial role of efficient energy storage in the next generation of brain-implantable devices, we introduce an energy management strategy in the design of wireless powering links, in which, the key performance