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The benefits of the ordering technique to improve the static linearity performances of digital-to-analog converters are discussed. Different techniques of grouping or sequencing elements are studied for segmented, binary or unary DAC architectures. The statistic of ordered elements and their properties are reviewed and studied. Then, the optimal selection of elements for a binary or unary use is discussed

In this paper, we present a compact design for the code based signature called LEDAsig with side channel resistance. Existing implementations concentrate on the high-speed feature while few of them have considerations on area or power efficiency which are particularly decisive for low-cost or power constrained IoT applications. We propose an area-efficient FPGA architecture for systematically rotating

Analog-to-digital and digital-to-analog conversion devices for signals with very large bandwidth are not always available due to technical or cost issues. This limits the realization of very high data-rate digital communication systems. In this paper, we propose a dual pulse shaping (DPS) transmission scheme, which can achieve full Nyquist rate transmission with only a half of the sampling rate for

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This paper presents a high-performance solar energy harvesting system with improved adaptive maximum power point tracking (AMPPT) method utilizing neural network (NN) model as assistance. Under the guidance of the negative feedback control (NFC) model, a BJT based voltage control oscillator with three off-chip reconfigurable resistors is designed in this paper to improve the reusability of the solar

In this work, we investigate for the first time the impact of Negative Capacitance FinFET (NC-FinFET) technology on the performance of processors under the effects of process variations for various operating voltages. The industry compact model of FinFETs (BSIM-CMG) is fully calibrated to reproduce Intel 14nm FinFET data of high volume manufacturing process. A physics-based negative capacitance (NC)

This paper applies new analytical techniques to evaluate the stability and mean-square error (MSE) convergence of a multi-loop LMS pseudo-random noise canceller which applies to a variety of known mixed-signal circuit calibration techniques. To the authors’ knowledge, it is the first published MSE analysis of any multi-loop LMS system, and, unlike most published MSE analyses of single-loop LMS systems

We propose a logic synthesis methodology with a novel low-power circuit structure for ternary logic. The proposed methodology synthesizes a ternary function as a ternary logic gate using carbon nanotube field-effect transistors (CNTFETs). The circuit structure uses the body effect to mitigate the excessive power consumption for the third logic value. Energy-efficient ternary logic circuits are designed

This paper aims to solve the problem of the coordination of cloud-based model-free multiagent systems (CBMF-MASs) with communication constraints. To improve the data processing ability of multiagent systems for massive real-time data and decrease the communication burden of individual agents, cloud computing systems are utilized to establish the multiagent system. To actively compensate for network

In this study, a local positive feedback technique is proposed to enhance the performance of the folded cascode (FC) operational transconductance amplifier (OTA) when working in its saturation region. The enhanced FC-OTA has a higher gain bandwidth (GBW), higher DC gain and higher slew rate (SR) over its conventional counterparts and popular recycling FC-OTAs. The proposed enhanced FC-OTA is implemented

The biological inner ear, or cochlea, is a sophisticated signal processing system that performs spectrum analysis over an ultra-broadband frequency range of ~20 Hz to 20 kHz with exquisite sensitivity and high energy efficiency. Electronic cochlear models, which mimic the exponentially-tapered structure of the biological inner ear using bidirectional transmission lines or filter cascades, act as fast

Approximate multipliers attract a large interest in the scientific literature that proposes several circuits built with approximate 4-2 compressors. Due to the large number of proposed solutions, the designer who wishes to use an approximate 4-2 compressor is faced with the problem of selecting the right topology. In this paper, we present a comprehensive survey and comparison of approximate 4-2 compressors

This work focuses on the design of downlink receiver for future generation cellular systems. In the multipath division multiple access (MDMA) system, the initial synchronization process includes timing and carrier frequency synchronization as well as home cell search. For the proposed system, the user data is transmitted in time domain and the cell search is based on control signals transmitted in

This paper presents a study of compact multiple-output switched-capacitor voltage regulators (MOSCVRs). Two methods to produce multiple outputs with an SCVR and their effects on performance – power efficiency and cross-regulation, are examined with output impedance analysis. Moreover, to help a circuit designer to implement a compact MOSCVR, a design method to determine the number of outputs and their

Compact integrated thermal sensors are utilized to measure hot / cold spots in CPU cores in multiple locations and are important for the power/performance of the chip. Bipolar junction transistors (BJT) are the industry standard for temperature sensing elements because of their predictable physics. This paper reports on one of the smallest PNP BJT bandgap based thermal sensors to date. Miniaturization

In this paper, we propose O 4 -DNN, a high-performance FPGA-based architecture for convolutional neural network (CNN) accelerators relying on o peration packing and o ut- o f- o rder ( OoO ) execution for DSP blocks augmented with LUT-based glue logic. The high-level architecture is comprised of a systolic array of processing elements (PEs), supporting output stationary dataflow. In this architecture

In this paper, we analyze how to calculate the matrix transposition in continuous flow by using a memory or group of memories. The proposed approach studies this problem for specific conditions such as square and non-square matrices, use of limited access memories and use of several memories in parallel. Contrary to previous approaches, which are based on specific cases or examples, the proposed approach

This paper presents an Analog Front-End for integrated Wake-Up Radios. The proposed Analog Front-End is composed of an envelope detector, a Schmitt trigger and a biasing block and has three distinctive features: i) clockless solution, which does not require an always-on oscillator; ii) an envelope detector with band-pass response which leads to smaller capacitance, thus easier integration, and low-frequency

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This Special Issue is a collection of selected papers presented at the IEEE Latin American Symposium on Circuits and Systems (LASCAS) 2019 that was held in Armenia, Quindio, Colombia, on February 24–27, 2019, and the IEEE NEWCAS 2019 Conference that was held in Munich, Germany, on June 23–26, 2019. As the flagship conferences of the IEEE Circuits and Systems Society (CASS) in the IEEE Regions 9 and

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This article describes a 10.7b 300MS/s two-step digital-slope analog-to-digital converter using an on-chip digital-offset correction. The proposed two-step digital-slope ADC is implemented using a passive track-and-hold followed by the input-polarity comparison and the two-step digital-slope conversion. The polarity of the input signal must be determined to control the level-shifting process and specify

This paper is concerned with the $H_\infty $ control problem for switched systems under the event-triggered sampling, the quantization control and the state-dependent switching. The dynamic event-triggered strategy and the quantization control are utilized to adjust the signal transmission and relieve the transmission load. Different from the existing dynamic event-triggered strategies, the triggering

To better understand the correlation between network topological features and the robustness of network controllability in a general setting, this paper suggests a practical approach to searching for optimal network topologies with given numbers of nodes and edges. Since theoretical analysis seems impossible at least in the present time, exhaustive search based on optimization techniques is employed

Conventional numerical circuit analysis tools typically scale superlinearly with the number of nodes. With the rapid increase in nodes in modern VLSI systems, alternative methods are required. The effective resistance is an important characteristic of electrical systems, which is used to simplify the circuit analysis process. An infinite resistive rectangular mesh is commonly assumed in the analysis

We combine 2-tap feed-forward amplitude equalization with phase equalization by 4-tap integrated pulse-width modulation. In a $\text{V}_{\mathbf {SS}}$ -terminated transmitter, amplitude equalization is selected for pull-up data transmission, and phase equalization for pull-down data transmission, and the strength of equalization can be controlled depending on channel losses. This combines the strength

This paper presents an iterative and decoupled perturbative stochastic Galerkin (SG) method for the variability analysis of stochastic linear circuits with a large number of uncertain parameters. State-of-the-art implementations of polynomial chaos expansion and SG projection produce a large deterministic circuit that is fully coupled, thus becoming cumbersome to implement and inefficient to solve

This paper addresses the consensus problem for two-layered MASs (multi-agent systems) subject to attacks on communication edges. Unlike most existing two-layered MAS models, the considered MASs are allowed to have heterogeneous inner communication topologies between the different layers. By using the linear transformation technique, some sufficient criteria are first given to achieve consensus among

In [1] , there are minor mistakes including the misuse of notations, the related description, the footnote and the reference. These minor mistakes do not influence on the discussion and the conclusions in the paper. The related mistakes are described as follows:

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This special section is a collection of selected papers presented at the IEEE International Symposium on Circuits and Systems (ISCAS) 2019 that was held in Sapporo, Japan, on May 26–29, 2019. As the flagship of the IEEE Circuits and Systems Society (CASS), ISCAS attracts researchers across all the main themes associated with the circuits and systems domain. ISCAS conferences are attended by more than

This paper presents an implantable fluorescence system with a composite emission filter and fiber-coupled laser excitation. The composite structure of the short-pass interference filter and absorption filters exhibited a band-pass spectrum between 510 and 570 nm, which is close to green fluorescent protein (GFP) emission. A high-quality excitation light was achieved by utilizing a blue laser through

In a more and more digital world, the protection of sensitive data is an essential challenge. Current cryptographic methods rely on one-way functions based on computationally challenging problems. However, there are several candidates for runtime efficient computing that might require new methods for data security. Among them are Universal Memcomputing Machines (UMM) for which a memristive circuit

This paper presents experimental results from a system that comprises a fully autonomous energy harvester with a solar cell of 1 mm 2 as energy transducer and a Power Management Unit (PMU) on the same silicon substrate, and an output voltage regulator. Both chips are implemented in standard $0.18~\mu \text{m}$ CMOS technology with total layout areas of 1.575 mm 2 and 0.0126 mm 2 , respectively. The

This work proposes a new theory to reduce the phase noise of K-band Voltage-Controlled Oscillators (VCOs) in Complementary Metal Oxide Semiconductor (CMOS) process by introducing one or more transmission poles around the parallel resonance of an LC-tank circuit. Introduction of transmission poles beside the parallel resonance of the LC-tank circuit sharpens the skirt characteristics of the Scattering

This paper describes the design of a touch screen panel (TSP) readout IC having an in-band noise immunity. The proposed IC employs a cascaded spread spectrum TSP driving scheme combining chirp spread spectrum (CSS) and pseudo-random (PR) orthogonal sequences. The CSS shows the 12-dB spread gain prior to an application of PR sequences, resulting in total -24-dB in-band noise immunity. The proposed IC

This paper proposes a low power 10-bit 2b/cycle time and voltage based-successive approximation register (SAR) analog-to-digital converter (ADC). At low supply voltage, there will be a significant difference in comparator decision time for different input voltages. By taking advantage of the fact, this ADC converts the reference voltage to the corresponding comparator decision time, achieving 2b/cycle

A continuous-time (CT) second-order $\Delta \Sigma $ current-to-digital converter (CDC) is presented in this paper. The proposed CDC uses two current-controlled ring oscillators as phase-domain integrators to achieve second-order quantization noise shaping. The proposed CDC uses a current-reuse architecture in which the feedback digital-to-analog converter (DAC) is used to bias the first integrator

This work presents a low-power all-digital approach to multiphase delay locked loop (DLL) design by the use of a scalable phase-to-digital converter (PDC) based on asynchronous sampling. The PDC is used as a linear phase detector (PD) with the ability to measure any phase difference leading to a shorter delay line with less power consumption. Two different approaches for the delay cell implementation

This article describes the cross-correlation function as an alternative method to adapt loop gain in digital CDRs. Cross-correlation function inherent properties and their link with the cross-power spectral density help consolidating the adaptive loop gain technique, XCALG, for clock and data recovery systems that implement bang-bang phase detector. Considering the modulation of the loop gain due to

A low power face recognition (FR) convolutional neural network (CNN) processor is proposed with high power efficiency to achieve always-on FR in mobile devices. Three key features enable a power-efficient FR CNN. First, tile-based clustering (THC) is proposed for reducing the computation overhead of hierarchical clustering. It generates an average of 37.2% duplicated input features in the entire network

Lyra2REv2 is a hashing algorithm that consists of a chain of individual hashing algorithms, and it is used as a proof-of-work function in several cryptocurrencies. The most crucial and exotic hashing algorithm in the Lyra2REv2 chain is a specific instance of the general Lyra2 algorithm. This work presents the first hardware implementation of the specific instance of Lyra2 that is used in Lyra2REv2

The rise of data-intensive applications has resulted in an increasing demand for high-density and low-power on-chip embedded memories. Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible alternative to conventional static random access memory (SRAM) which offers higher density, lower leakage power, and two-ported operation. However, in order to maintain the stored data, GC-eDRAM requires periodic

This work presents a compact CMOS Image Sensor (CIS) architecture enabling embedded object recognition facilitated by a dedicated end-of-column Compressive Sensing (CS), reducing on-chip memory needs. Our sensing scheme is based on a combination of random modulations and permutations leading to an implementation with very limited hardware impacts. It is designed to meet both theoretical ( i.e. , stable

Acceleration and compression on deep Convolutional Neural Networks (CNNs) have become a critical problem to develop intelligence on resource-constrained devices. Previous channel pruning can be easily deployed and accelerated without specialized hardware and software. However, weight-level redundancy is not well explored in channel pruning, which results in a relatively low compression ratio. In this

Block floating point quantization (BFPQ) exploits signal statistics so that one common exponent is shared among a block of data. The output signal-to-quantization-noise ratio (SQNR) may drop due to the increase in quantization error resulted from the increment of the exponent, especially for the non-uniformly distributed input signals. The tunable BFPQ is then proposed. With the aid of the tuning parameter

More compact Switch-Mode Power Supplies (SMPSs) satisfying typical design specifications can be obtained by exploiting ferrite core inductors working in partial saturation. In this case, the inductance is no longer a constant parameter, since it exhibits a sharp drop as the inductor current increases. A behavioral model was recently proposed, which provides the inductance at steady state as a function

Operating systems (OS) are critical infrastructures for information system. To design a highly reliable software, it is essential to understand the architecture feature of operating systems, which is recently explored by network analysis. While most focus is on the topological properties, the network reliability is rarely studied. In this paper, based on percolation method, we analyze the function-call

In this paper, the start-up response of a digitally controlled dc-dc boost converter with a constant power load is studied. A mathematical expression of the system response during start-up is derived using a nonlinear averaged model. The time-domain response of the system during start-up when the converter is operating under current limitation mode is derived by analytically integrating the mathematical

This paper studies the impacts of stochastic load fluctuations, namely the fluctuation intensity and the load power variation speed, on power system dynamic voltage stability. Additionally, the trade-off relationship between the two parameters is revealed, which provides important insights regarding the potential of using energy storage to maintain voltage stability under high uncertainty. To this