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Expectation-Maximization Based Disturbance Identification and Velocity Tracking for Gimbal Servo Systems With Dynamic Imbalance IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-14 Xiaoyu Guo, Wenshuo Li, Yangyang Cui, Chenliang Wang, Zhengtao Ding
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Approximate Belief-Selective Propagation Detector for Massive MIMO Systems IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-14 Wenyue Zhou, Zhenhao Ji, Zeqiong Tan, Zhuangzhuang You, Xiaosi Tan, Xiaohu You, Chuan Zhang
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A 3.0$\mu$Vrms, 2.4 ppm/$^{\circ}$C BGR With Feedback Coefficient Enhancement and Bowl-Shaped Curvature Compensation IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-14 Xufeng Liao, Yuxiang Zhang, Shaohua Zhang, Lianxi Liu
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A 0.5–2.5 GHz Mixer First Receiver With 200 MHz RF Bandwidth and $+$18.5 dBm OB-IIP3 in 180 nm CMOS for 5G NR Band IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-13 Anupam Kumari, Darshak Bhatt
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$H_{\infty}$ State Estimation for Two-Time-Scale Markov Jump Complex Networks Under Analog Fading Channels: A Hidden-Markov-Model-Based Method IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-12 Feng Li, Youzhi Cai, Lei Su, Hao Shen, Shengyuan Xu
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Infinite Horizon Stabilization and Linear Quadratic Optimal Control of Descriptor Stochastic Markov Jump Systems IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-12 Yichun Li, Shuping Ma, Xiaotai Wu, Yang Tang
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A Wide-Input-Range Time-Based Buck Converter With Adaptive Gain and Continuous Phase Preset for Seamless PFM/PWM Transitions IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-11 Paolo Melillo, Simone Zaffin, Mauro Leoncini, Alberto Brunero, Alessandro Gasparini, Salvatore Levantino, Massimo Ghioni
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110–170 GHz On-Chip Calibration Using Deep Neural Networks IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-11 Haowen Cai, Sanming Hu, Xinge Huang, Yizhu Shen
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Observerless Output Feedback Control of DC-DC Converters Feeding a Class of Unknown Nonlinear Loads via Power Shaping IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-08 Wei He, Yanqin Zhang, Wangping Zhou
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A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-08 Yuqing Ren, Hassan Harb, Yifei Shen, Alexios Balatsoukas-Stimming, Andreas Burg
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A 0.14-nJ/b 200-Mb/s 2.7–3.5-GHz Quasi-Balanced FSK Transceiver With PLL-Based Modulation and Sideband Energy Detection IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-07 Bowen Wang, Cong Ding, Yunzhao Nie, Woogeun Rhee, Zhihua Wang
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Fixed-Time Fuzzy Control for Uncertain Nonlinear Systems With Prescribed Performance and Event-Triggered Communication IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-07 Chen Wang, Qing Guo, Jianhui Wang, Zhi Liu, C. L. Philip Chen
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A Coupling Matrix Synthesized Three-Dimensional Filtering Power Amplifier IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-07 Yang Gao, Weiming Ma, Di Lu, Baoqi Zhu, Pengcheng Jia, Ming Yu
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Parallel Implementation of SPHINCS$+$ With GPUs IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-06 DongCheon Kim, HoJin Choi, Seog Chung Seo
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Dynamic Event-Triggered Consensus Control for Interval Type-2 Fuzzy Multi-Agent Systems IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-06 Zhenbin Du, Xiangpeng Xie, Zifang Qu, Yangyang Hu, Vladimir Stojanovic
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Low Complexity Deep Learning Augmented Wireless Channel Estimation for Pilot-Based OFDM on Zynq System on Chip IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-06 Animesh Sharma, Syed Asrar Ul Haq, Sumit J. Darak
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ACE-CNN: Approximate Carry Disregard Multipliers for Energy-Efficient CNN-Based Image Classification IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-03-01 Salar Shakibhamedan, Nima Amirafshar, Ahmad Sedigh Baroughi, Hadi Shahriar Shahhoseini, Nima Taherinejad
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A Low-Latency Power Series Approximate Computing and Architecture for Co-Calculation of Division and Square Root IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-29 Dian Tian, Ningmei Yu, Minghui Xie, Jiahao Tang, Zhuang Feng, Álvaro Hernández, Jesús Ureña
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Load-Independent Class-E Frequency Multipliers IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-29 Yinchen Xie, Wenqi Zhu, Yutaro Komiyama, Ayano Komanaka, Akihiro Konishi, Xiuqin Wei, Kien Nguyen, Hiroo Sekiya
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A Multi-Mode SPAD-Based Ranging System Integrated Nonlinear Histogram and FIR With Adaptive Coefficient Adjustment IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-28 Dong Li, Rui Ma, Jin Hu, Xiayu Wang, Zhangming Zhu
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Random Flip Bit Aware Reading for Improving High-Density 3-D NAND Flash Performance IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-28 Hua Feng, Debao Wei, Shipeng Gu, Zhelong Piao, Yongchao Wang, Liyan Qiao
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Sampled-Data Control for Buck-Boost Converter Using a Switched Affine Systems Approach IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-28 Xiaozeng Xu, Yanzheng Zhu, Fen Wu, Choon Ki Ahn
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IEEE Circuits and Systems Society Information IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-27
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A High Sensitivity CMOS Rectifier for 5G mm-Wave Energy Harvesting IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-27 Edoh Shaulov, Tal Elazar, Eran Socher
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IEEE Transactions on Circuits and Systems--I: Regular Papers Publication Information IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-27
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IEEE Transactions on Circuits and Systems--I: Regular Papers Information for Authors IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-27
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A 0.6-to-1.2 V Scaling-Friendly Discrete-Time OTA-Free Linear VCO-Based TEXPRESERVE0 ADC Suitable for DVFS IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-27 Kyung-Chan An, Neelakantan Narasimman, Tony Tae-Hyoung Kim
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A Control-Bounded Quadrature Leapfrog ADC IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-27 Hampus Malmberg, Fredrik Feyling, José M. de la Rosa
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Stereo Matching Accelerator With Re-Computation Scheme and Data-Reused Pipeline for Autonomous Vehicles IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-27 Ke Li, Xiwei Fang, Yunhao Ma, Wenyue Zhang, Pingcheng Dong, Zhuoyu Chen, Lei Chen, Fengwei An
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Guest Editorial Special Issue on the IEEE Latin American Symposium on Circuits and Systems (LASCAS 2023) IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-27 Alexandra Zimpeck, Alexander Fish
This Special Issue of IEEE Transactions on Circuits and Systems—I: Regular Papers (TCAS-I) includes papers presented at the IEEE Latin American Symposium on Circuits and Systems (LASCAS). This annual symposium provides a high-quality exchange and networking forum for researchers, professionals, and students, gathering an international audience with experts from all over the world. The symposium is
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MARLIN: A Co-Design Methodology for Approximate ReconfigurabLe Inference of Neural Networks at the Edge IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-27 Flavia Guella, Emanuele Valpreda, Michele Caon, Guido Masera, Maurizio Martina
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ET-SRCKF-Based Dynamic State Estimation for Cyber-Physical Distribution Systems With Delayed Measurements IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-26 Xiao Hu, Xinghua Liu, Huaicheng Yan, Gaoxi Xiao, Peng Wang
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An Output Voltage Tracking Control Method With Overcurrent Protection Property for Disturbed DC–DC Boost Converters IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-26 Saijin Huang, Tianliang Guo, Xiangyu Wang, Shihua Li, Qi Li
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Unified Adaptive Performance Control of MIMO Input-Quantized Nonlinear Systems IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-23 Qian Bai, Kai Zhao, Yongduan Song
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Data-Driven Distributed $H_\infty$ Current Sharing Consensus Optimal Control of DC Microgrids via Reinforcement Learning IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-23 Xu Dong, Huaguang Zhang, Xiangpeng Xie, Zhongyang Ming
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Finite-Time Decentralized Sliding Mode Control for Interconnected Systems and Its Application to Electrical Power Systems: A GA-Assisted Design Method IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-23 Hao Xu, Tao Yu, Chengcheng Ren, Shuping He
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MA-Opt: Reinforcement Learning-Based Analog Circuit Optimization Using Multi-Actors IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-23 Youngchang Choi, Sejin Park, Minjeong Choi, Kyongsu Lee, Seokhyeong Kang
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KERNTROL: Kernel Shape Control Toward Ultimate Memory Utilization for In-Memory Convolutional Weight Mapping IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-22 Johnny Rhe, Kang Eun Jeon, Joo Chan Lee, Seongmoon Jeong, Jong Hwan Ko
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DQ-STP: An Efficient Sparse On-Device Training Processor Based on Low-Rank Decomposition and Quantization for DNN IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-22 Baoting Li, Danqing Zhang, Pengfei Zhao, Hang Wang, Xuchong Zhang, Hongbin Sun, Nanning Zheng
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Optimized and Automated Secure IC Design Flow: A Defense-in-Depth Approach IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-22 Kevin Immanuel Gubbi, Banafsheh Saber Latibari, Muhtasim Alam Chowdhury, Afrooz Jalilzadeh, Erfan Yazdandoost Hamedani, Setareh Rafatirad, Avesta Sasan, Houman Homayoun, Soheil Salehi
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A Computing In-Memory Multibit Multiplication Based on Decoupling and In-Array Storing IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-22 Jin Zhang, Zhongzhen Tong, Hao Wang, Xin Wang, Qiang Zhao, Jian Zhou, Jiaqun Wang, Zhiting Lin, Xiulong Wu
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NeuroSim V1.4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-21 Junmo Lee, Anni Lu, Wantong Li, Shimeng Yu
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Fixed-Time Stabilization of Multi-Weighted Complex Networks via Novel Adaptive Pinning Chatter-Free Control and Its Applications IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-21 Fangmin Ren, Xiaoping Wang, Yangmin Li, Zhanfei Chen, Chen Wei, Zhigang Zeng
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A Heterogeneous Platform for 3D NAND-Based In-Memory Hyperdimensional Computing Engine for Genome Sequencing Applications IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-21 Po-Kai Hsu, Vaidehi Garg, Anni Lu, Shimeng Yu
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Design of Artificial Neurons of Memristive Neuromorphic Networks Based on Biological Neural Dynamics and Structures IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-20 Xiaosong Li, Jingru Sun, Yichuang Sun, Chunhua Wang, Qinghui Hong, Sichun Du, Jiliang Zhang
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Variation Aware Evaluation Approach and Design Methodology for SOT-MRAM IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-15 Chao Wang, Zhaohao Wang, Shixing Li, Zhongkui Zhang, Youguang Zhang
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Calculation of the Worst-Case Voltage Noise for a Power Distribution Network Based on Ramp Current IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-15 Yuhuan Luo, Jun Wang, Haiyue Yuan, Tao Wei, Yuhao Huang, Feng Wu, Yang Liu, Xiuqin Chu
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Kalman Filters Based Distributed Cyber-Attack Mitigation Layers for DC Microgrids IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-02-05 Ahmed H. El-Ebiary, Mahmoud A. Attia, Fathy H. Awad, Mostafa I. Marei, Mohamed Mokhtar
The use of communication links between microgrid components has made the transmitted data vulnerable to cyber-attacks. This paper presents distributed cyber-attack detection and mitigation layers integrated with the primary and secondary control loops of a meshed DC microgrid. Voltage and current cyber-attacks mitigation layers based on the Kalman Filter (KF), as a robust state estimator, are proposed
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Spatiotemporal Chaos in a Sine Map Lattice With Discrete Memristor Coupling IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-01-31 Shaobo He, Bo Yan, Xianming Wu, Huihai Wang, Mengjiao Wang, Herbert Ho-Ching Iu
At present, design of discrete memristor based chaotic maps starts to attract the attention of the scientists, but it is still in its incipient stage. In this paper, spatiotemporal chaos in the Sine map lattice with discrete memristor coupling is investigated. Firstly, the $3\times m$ higher dimensional chaotic map is proposed, where there are $m$ discrete memristors and $m$ state variable difference
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Hybrid Batch-Normalized Deep Feedforward Neural Network Incorporating Polynomial Regression for High-Dimensional Microwave Modeling IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-01-09 Amin Faraji, Sayed Alireza Sadrossadat, Jing Jin, Weicong Na, Feng Feng, Qi-Jun Zhang
This paper proposes a new hybrid structure and microwave modeling method that combines polynomial regression with batch-normalized deep feedforward neural network (BN-DFN) to be used in high-dimensional microwave circuit modeling. Utilizing the proposed BN-DFN method results in a remarkably faster training procedure compared to the conventional DFN. In addition, the superiority of the BN-DFN method
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Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-01-09 Bi Wu, Tianyang Yu, Ke Chen, Weiqiang Liu
With the rapid development of the Internet of Things (IoT), it has become a common concern of academia and industry to provide real-time high performance services for edge-side applications and to bestow intelligence on massive edge-side devices. Due to the limitations of storage space, volume and power consumption of edge side devices, it is difficult for existing convolutional neural networks with
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Flocking Dynamics for Cooperation-Antagonism Multi-Agent Networks Subject to Limited Communication Resources IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-01-09 Lei Shi, Zhuangzhuang Ma, Shuaiming Yan, Tianyong Ao
This contribution explores the flocking dynamic behavior of multi-agent networks with limited communication resources, where there are both cooperative and antagonistic relationships among agents. Taking into account the shortage of communication resources, a distributed control protocol with edge-asynchronous communications is designed, in which only part of the communication links are awakened at
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DNN-Based Optimization to Significantly Speed Up and Increase the Accuracy of Electronic Circuit Design IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-01-09 Sayed Alireza Sajjadi, Sayed Alireza Sadrossadat, Ali Moftakharzadeh, Morteza Nabavi, Mohamad Sawan
Efficient design and optimization of flip-flops can significantly affect overall circuit performance as they have many applications in digital systems which can impact the overall power consumption and timings of the emerging system on chips (SOCs). In this paper, modeling, design, and optimization of transmission gate-based master-slave positive-edge-triggered flip-flop (TGFF) in 16 nm complementary
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Distributed Dynamic Event-Triggered Resilient Control for AC Microgrids Under FDI Attacks IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-01-08 Binjie Xia, Sha Fan, Lei Ding, Chao Deng
In this paper, we investigate the distributed resilient control problem of voltage and frequency restoration in AC microgrids (MGs) subject to false data injection (FDI) attacks under event-triggered communication. To solve the problem, new distributed dynamic event-triggered $k$ -step attack observers are primarily designed for the accurate estimation of attacks while avoiding continuous communication
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A Novel Online Adaptive Dynamic Programming Algorithm With Adjustable Convergence Rate IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-01-05 Yonghua Wang, Zheliang Zhang, Yongwei Zhang, Mingming Liang, Derong Liu
This article develops a novel online adaptive dynamic programming algorithm with adjustable convergence rate to address the optimal control problem of nonlinear systems. Relaxation factors are introduced to tune the convergence rate of value function sequence online. A novel update law based on recursive least squares is developed to adjust the weight of critic neural network at the sampling instant
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Characterization of Oscillator Phase Noise Arising From Multiple Sources for ASIC True Random Number Generation IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-01-05 Adriaan Peetermans, Ingrid Verbauwhede
This paper presents an analytical study together with an oscillator phase measurement technique to assess the magnitude of the five most prevalent noise types found in free-running oscillators, intended for use in true random number generation. The noise types under study range from white thermal- to flicker- and random walk noise, acting either on the oscillator phase or frequency. A time domain study
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Fast FPGA Prototyping to Explore and Compare New SPWM Strategies IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2024-01-01 Sergio R. Geninatti, Manuel Ortiz-López, Fco. Javier Quiles-Latorre, Tomás Morales-Leal, Andrés Gersnoviez, Antonio Moreno-Muñoz
This study presents a Flexible Test Bench (FTB) implemented with FPGA that synthesises of a large number of strategies that apply “Spread Spectrum” to reduce the energy of the fundamental harmonics present in a conventional Pulse Width Modulation (PWM). The FTB not only incorporates most of the known spread spectrum techniques but also allows to combine them and even to easily create new ones, thus
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TT-CIM: Tensor Train Decomposition for Neural Network in RRAM-Based Compute-in-Memory Systems IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2023-12-29 Fan-Hsuan Meng, Yuting Wu, Zhengya Zhang, Wei D. Lu
Compute-in-Memory (CIM) implemented with Resistive-Random-Access-Memory (RRAM) crossbars is a promising approach for accelerating Convolutional Neural Network (CNN) computations. The growing size in the number of parameters in state-of-the-art CNN models, however, creates challenge for on-chip weight storage for CIM implementations, and CNN compression becomes a crucial topic of exploration. Tensor
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Stability Analysis for On-Off Voltage-Mode Controlled VHF Converter Combining Short-Period and Long-Period Discrete Map Models IEEE Trans. Circuits Syst. I Regul. Pap. (IF 5.1) Pub Date : 2023-12-29 Shikai Chen, Yanfeng Chen, Bo Zhang, Dongyuan Qiu
Benefited from harmonics well-defined and easy design of filter, the ON-OFF voltage-mode control strategy suitable for the very-high-frequency (VHF, 30~300MHz) dc-dc converter has been developed in recent year. However, the potential risk of this control strategy is that unreasonable parameter design will lead to system instability. Moreover, the conventional stability methods are also difficult to