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When applied to artificial intelligence edge devices, the conventionally von Neumann computing architecture imposes numerous challenges (e.g., improving the energy efficiency), due to the memory-wall bottleneck involving the frequent movement of data between the memory and the processing elements (PE). Computing-in-memory (CIM) is a promising candidate approach to breaking through this so-called memory

This Special Issue is a collection of selected papers presented at the IEEE Latin American Symposium on Circuits and Systems (LASCAS) 2020 that was held in San José, Costa Rica, on February 25–28, 2020. As the flagship conference of the IEEE Circuits and Systems Society (CASS) in IEEE Region 9, this conference welcomes contributions across the themes within the scope of the society, including analog

The approximate computing paradigm emerged as a key alternative for trading off accuracy and energy efficiency. Error-tolerant applications, such as multimedia and signal processing, can process the information with lower-than-standard accuracy at the circuit level while still fulfilling a good and acceptable service quality at the application level. The automatic detection of R-peaks in an electrocardiogram

An imaging pixel unit-cell topology leveraging a photodetector in the forward-bias region is proposed. Connecting the anode of the photodiode to the gate of a NMOS device operating in the subthreshold region provides the basis for a new open-circuit voltage pixel (VocP) architecture. Theoretical analysis is presented to show the response and performance benefits of the VocP in comparison to a conventional

This paper demonstrates a wideband 2.4 GHz $2\times 9$ -bit Cartesian radio-frequency digital-to-analog converter (RFDAC). Active-under-coil integration is introduced in the physical implementation, where all key active circuitry is located underneath the matching-network transformer, achieving a core area of merely 0.35 mm 2 . An $8\times $ analog linear interpolation at the RF rate is proposed to

This article presents a $Ku$ -band power amplifier with a series-shunt $LC$ notch filter in 65-nm CMOS. The notch filter is integrated into the inter-stage matching network to attenuate the receiver-band noise, thereby reducing transmitter-to-receiver interference. A comprehensive analysis of the series and the shunt notch filters, as well as the position to apply the notch filter is discussed. Besides

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique

Always-on keyword spotting (KWS) that detects wake-up words has been the indispensable module in the voice interaction system. However, the ultra-low-power embedded devices put forward strict requirements on energy consumption, latency, and recognition accuracy of KWS. In this work, we propose a near-sensor processing architecture of feature-configurable distributed network (NS-FDN) for always-on KWS

This article presents a novel circuit modeling method for online training and testing process of the neuromorphic chip crossbar array based on the resistive random access memory (RRAM). A modified RRAM compact model is developed to realize the fast and accurate update of multiple conductance levels. Two training mechanisms with and without write-verify scheme are modeled and investigated for classifying

Emerging computation-in-memory (CIM) paradigm offers processing and storage of data at the same physical location, thus alleviating critical memory-processor communication bottlenecks suffered by conventional von-Neumann architecture. Storage of data in a CIM architecture is analog in nature and therefore computation is performed in analog domain i.e. inputs and outputs are analog values. Since the

In-memory computing provides unprecedented power and area efficiency for the execution of convolutional neural networks by using memory bitcells to perform dot-product (DP) operations in the analog domain. Yet, these operators suffer from analog non-idealities (ANIs) that degrade the inference accuracy. This paper proposes design guidelines inferred from a holistic simulation-based analysis of the

This paper proposes a technique to enhance the maximum achievable power gain ( $G_{MAX}$ ) of the two-port active network (2PAN) in the near- $f_{MAX}$ region. This technique is based on using the optimized passive-linear-lossy-reciprocal (PLLR) embedding to increase the unilateral power gain ( $U$ ) of the 2PAN and accordingly the $G_{MAX}$ . Due to the possibility to increase $U$ , it shows the potential

Polar codes have been officially selected as the channel coding in 5G standard. To meet the requirements of enhanced mobile broadband (eMBB), most published polar decoder chips aim to improve throughput rate and error-correction performance. However, to meet with the requirements of another two 5G new radio (NR) application scenarios, ultra-reliable low-latency communications (URLLC), and massive machine-type

We propose a co-design approach for compute-in-memory inference for deep neural networks (DNN). We use multiplication-free function approximators based on $\ell _{1}$ norm along with a co-adapted processing array and compute flow. Using the approach, we overcame many deficiencies in the current art of in-SRAM DNN processing such as the need for digital-to-analog converters (DACs) at each operating

Superconducting digital electronics, especially Single Flux Quantum (SFQ), has emerged as a promising beyond-CMOS technology with Josephson junctions (JJ) as the active device. It has the potential to meet the booming demands of lower power consumption and higher operation speeds in the electronics industry and future exascale supercomputing systems. Despite these promises, scaling SFQ circuits remains

Dynamic power is a major source of power dissipation for high speed designs. Domain isolation methodology is a recently-proposed technique for reducing dynamic power based on controlling the evaluation phase of dynamic logic (toggling control). This work demonstrates some design issues in the domain isolation methodology and explains why it is inefficient with pipelined systems. We propose fixes for

This paper presents a convolution process and its hardware architecture for energy-efficient deep neural network (DNN) processing. A DNN in general consists of a number of convolutional layers, and the number of input features involved in the convolution of a shallow layer is larger than that of kernels. As the layer deepens, however, the number of input features decreases, while that of kernels increases

Integrating Deep Neural Networks (DNNs) into the Internet of Thing (IoT) devices could result in the emergence of complex sensing and recognition tasks that support a new era of human interactions with surrounding environments. However, DNNs are power-hungry, performing billions of computations in terms of one inference. Spatial DNN accelerators in principle can support computation-pruning techniques

Public key cryptography lies among the most important bases of security protocols. The classic instances of these cryptosystems are no longer secure when a large-scale quantum computer emerges. These cryptosystems must be replaced by post-quantum ones, such as isogeny-based cryptographic schemes. Supersingular isogeny Diffie-Hellman (SIDH) and key encapsulation (SIKE) are two of the most important

The Discrete Hirschman Transform (DHT) is more computationally attractive than the Discrete Fourier Transform (DFT). Based on its derived linear convolution, we have confirmed that the DHT-based convolution filter shows its superiority in reducing computations conditionally, while compared with the conventional DFT-based convolution filter in our previous work. Since the DHT-based convolution has many

Venture capital market is one of the most important financial markets, which plays an important role in promoting industrial innovation and economic development. In this study, the complete data set of all venture capital events occurred in China from 2009 to 2020 was used to construct two kinds of complex networks, whose topological property and dynamic evolution trend of the network are studied.

In this paper, we present an approach to nonlinear system approximation, called the lattice trajectory piecewise linear (LTPWL) model. The approach involves determining a lattice piecewise linear (PWL) approximation to the state trajectory of a nonlinear system. It has been shown in the literature that the lattice PWL expression can represent any PWL function in any dimension. After the LTPWL approximation

The main focus of this paper is the presentation of reliable methods for the determination of the optimum coloring of a graph, commonly known in the literature as vertex coloring problem. It has been shown that networks of capacitively coupled oscillators can be used to solve vertex coloring problems. In this paper we address the negative impact of an unbalanced number of couplings for the oscillators

Silicon Carbide (SiC) MOSFETs are usually paralleled to increase the current capability for high power applications. While, the asymmetrical parasitic parameters of the wide-used laminated busbar can cause current imbalance for paralleled MOSFETs. The fast switching of SiC devices can further deteriorate the imbalance. However, the complex current paths and their mutual effects are seldom considered

Two synthesis algorithms of multiport network with desired unequal complex port-impedances are developed considering the multiport network as an interconnection of two-port networks (TPNs). The first one is direct-synthesis using Y-matrix, and the second one is port-impedance transformation method. The techniques are single-frequency methods, as the scattering parameters of known multiport networks

This paper investigates the fixed-time time-varying formation control problems for heterogeneous multi-agent systems (MASs) composed of multiple Unmanned Ground Vehicles (UGVs) and multiple Unmanned Aerial Vehicles (UAVs) in the presence of actuator faults, parameter uncertainties, matched and mismatched disturbances. Besides achieving the desired formation configurations, each follower can also track

This paper presents two efficient algorithms to determine whether a bivariate polynomial, possibly with complex coefficients, does not vanish in the cross product of two closed right-half planes (is “2-C stable”). A 2-C stable polynomial in the denominator of a two-dimensional analog filter has been proved (not long ago) to imply bounded-input bounded-output (BIBO) stability. The two algorithms are

This article is concerned with quasi-synchronization of grid-connected systems in electrical networks, where heterogeneous Inductance-Capacitance (LC) oscillators are coupled via electrical inductance subject to time-varying delays. Note that complete synchronization fails to be accomplished due to the existence of nonidentical parameters and quasi-synchronization cannot be achieved via non-delayed

To avoid the bumps of the control signal in the switching instants, this paper proposes a bumpless transfer control method which guarantees the continuous of control signal while keeping the asymptotic stability of the closed-loop system. Firstly, the presented bumpless transfer control method possesses a simple structure and meanwhile not have to redesign sub-controllers, which is easy to implement

This article is concerned with the co-design of fault detection and consensus control protocol for a class of multi-agent systems (MASs) subject to Denial-of-Service attack, where the attack behavior is hidden to the defender as the adversary may launch the attack with different durations but the defender may not know the real situation at each time instant. Due to the complicated attack behavior,

In this paper, we combine practically verified results from circuit theory with communication-theoretic laws. As a result, we obtain closed-form theoretical expressions linking fundamental system design and environment parameters with the power consumption of analog front ends (AFEs) for communication receivers. This collection of scaling laws and bounds is meant to serve as a theoretical reference

MOS N-path mixer-first receivers are capable of providing instantly-reconfigurable RF impedance and bandwidth while achieving moderate noise figure (NF) and high linearity, but their frequency tuning range is limited by both LO (local oscillator) generation and the RF port input capacitance. State-of-the-art mm-wave MOS N-path receivers often compromise performance to cover the mm-wave range, but this

Beyond 5G systems are expected to approach 1 Tb/s throughput. This poses a significant challenge to the channel decoder. In this paper, we propose a multi-core architecture based on full row parallel layered LDPC decoder with frame interleaving. Compared with conventional partially parallel layered architectures, the proposed architecture increases the throughput by applying frame interleaving into

Digital-to-time converters (DTCs) are a promising technology for radio frequency (RF) transceivers but are prone to spur generation. A common approach to change the spurious emissions to a spur-free shape is a method called dithering. The power added due to dithering is an important aspect of this approach and gives raise to investigations on additive dither as well as methods for subtractive dithering

Nonlinear couplings among units (nodes) are ubiquitous in engineering systems including, e.g., radar and sonar systems, which have been ignored in most works. In this article, the problem of distributed synchronization of nonlinear networked systems with nonlinear couplings is studied. Specifically, two kinds of nodes’ communication couplings including nonlinear relative and nonlinear absolute state

This paper proposes a novel T-type multilevel inverter (MLI) based on the switched-capacitor technique. The proposed inverter not only achieves that the maximum voltage stress of the switches is less than the input voltage but also has a voltage boost capability, which makes it suitable in high voltage applications. It is worth mentioning that the proposed inverter features two topology extension schemes

In wireless charging devices, different wireless charging standards have caused charging incompatibility, and the utilization rate of the DC voltage at the transmitter is not high, which brings challenges to the application of wireless charging. To solve these two problems, this paper proposes a multi-frequency multi-amplitude (MFMA) superimposition modulation method. This method superimposes multiple

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Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

Presents the table of contents for this issue of the publication.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

As new applications impose jitter values in the range of a few tens of femtoseconds, the design of phase-locked loops faces daunting challenges. This paper derives basic relations between the tolerable jitter and the power consumption, predicting severe issues as jitters below 10 fs are sought. The results are also applied to the sampling clocks in analog-to-digital converters and suggest that clock

A novel galvanic isolated amplifier based on CMOS integrated Hall sensors is presented in this paper. Two serially connected Hall-effect sensors are integrated along with their instrumentation amplifiers using the TSMC 65nm process. A printed-circuit board is employed to validate the proposed isolation amplifier by assembling the chip with chopper modulator, coil driver, miniature coil, variable gain

This paper presents a passive vector-modulated phase shifter (VMPS). The passive X-type attenuator consisting of digitally controlled transistor-array units is employed to perform the phase-invertible gain tuning, and thus enables phase shift in all four quadrants. The Wilkinson-like power combiner is utilized to sum up the quadrature signals and avoid impedance mismatches. Analysis proves that the

This paper presents an ultrasound rangefinder system able to find relative distances among energy-constrained sensor nodes. The nodes build a swarm that is operated in collision and multipath rich environments. A new distance measurement technique combining Wake-up and Frequency Modulated Continuous Wave (FMCW) is proposed to enable the ranging while neglecting the echoes from passive reflectors in

This article presents a design strategy to improve the bandwidth of the three-stage Doherty Power Amplifier (DPA) by controlling the phase difference between the dual RF inputs digitally. The theory also proposes multiple back-off reconfigurability without using tuning elements and extra circuitry. The proposed theory is validated by demonstration of a dual-input three-stage DPA which is designed and

In the transmit signal path of a cellular terminal that supports the Long-Term Evolution (LTE) standard, the third-order counter-intermodulation (CIM3) product can be a significant contributor to spurious emissions in protected bands, primarily in cases where all the transmit power is concentrated in one resource block at the edge of the allocated bandwidth. This problem can be addressed with a harmonic

The time-interleaved analog-to-digital converter has shown to be a key component of the latest ultra-wide band systems. Unfortunately, the sub-analog-to-digital converters are prone to parameter deviations caused by process-voltage-temperature, which can affect the output linearity. This article presents a foreground time-interleaved analog-to-digital converter mismatch calibration, which is one of

This paper presents a low-profile and autonomous piezoelectric energy harvesting system consisting of an extraction rectifier and a maximum power point tracking (MPPT) circuit for powering portable electronics. Synchronized switch harvesting on capacitor-inductor (SSHCI) technique with its unique two-step voltage flipping process is utilized to downsize the ponderous external inductor and extend application

In this paper, a novel mode composite waveguide based on hybrid substrate integrated waveguide and spoof surface plasmon polariton (SIW-SSPP) is proposed. Through different feeding methods, the odd mode and even mode of SSPP are excited simultaneously and operate at the same frequency band. Thus, co-frequency mode multiplexing is achieved for the proposed odd-even mode composite waveguide (OEMCW).

Approximate computing is established as a design alternative to improve the energy requirements of a vast number of applications, leveraging their intrinsic error tolerance. Voltage over-scaling (VOS) is one of the most energy-efficient approximation techniques, but its exploitation is still limited due to the large errors it induces. In this work, we investigate, for the first time, the resiliency

This paper proposes a high-performance bidirectional architecture for the quasi-comparison-free sorting algorithm. Our architecture improves the performance of the conventional unidirectional architecture by reducing the total number of sorting cycles via bidirectional sorting along with two auxiliary methods. Bidirectional sorting allows the sorting tasks to be conducted concurrently in the high-

Training of Deep Neural Network (DNN) at the edge faces the challenge of high energy consumption due to the requirements of a large number of memory accesses for gradient calculations. Therefore, it is necessary to minimize data fetches to perform training of a DNN model on the edge. In this paper, a novel technique has been proposed to reduce the memory access for the training of fully connected layers

In-SRAM Computation improves the throughput and energy-efficiency of data-intensive applications by utilizing parallelism and reducing the data transfers. However, when multiple wordlines are accessed simultaneously, a short-circuit path will likely incur dynamic read disturbance and generate extra direct current in 6T Compute SRAM (CSRAM). In order to mitigate this issue, existing works either degrade

Machine learning inference is of broad interest, increasingly in energy-constrained applications. However, platforms are often pushed to their energy limits, especially with deep learning models, which provide state-of-the-art inference performance but are also computationally intensive. This has motivated algorithmic co-design, where flexibility in the model and model parameters, derived from training

In the recent years, the spiking neural network (SNN) has attracted increasing attention due to its low energy consumption and online learning potential. However, the design of SNN processor has not been thoroughly investigated in the past, resulting in limited performance and energy consumption. In this work, a fast and energy-efficient SNN processor with adaptive clock/event-driven computation scheme

Once there are constant or infrequently changed bits (COIBs) in two adjacent input messages of SHA-2, the switching power of input messages data registers (IMD-REGs) used for COIBs will disappear. Meanwhile, when full pipeline SHA-2 is applied in a certain application scenario where the IMD-REGs used for COIBs can be removed, more area of full pipeline SHA-2 can be saved as the proportion of IMD-REGs

Under process, voltage, and temperature variations, SRAM cell stability largely fluctuates from the nominal value. In the design step, SRAM cell optimization while ignoring the fluctuation induces the yield loss for the stability. Variation-aware optimization of an SRAM cell can prevent the yield loss problem by considering the mean and variance of SRAM cell stability when finding optimal design parameters