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The benefits of the ordering technique to improve the static linearity performances of digital-to-analog converters are discussed. Different techniques of grouping or sequencing elements are studied for segmented, binary or unary DAC architectures. The statistic of ordered elements and their properties are reviewed and studied. Then, the optimal selection of elements for a binary or unary use is discussed

In this paper, we present a compact design for the code based signature called LEDAsig with side channel resistance. Existing implementations concentrate on the high-speed feature while few of them have considerations on area or power efficiency which are particularly decisive for low-cost or power constrained IoT applications. We propose an area-efficient FPGA architecture for systematically rotating

Analog-to-digital and digital-to-analog conversion devices for signals with very large bandwidth are not always available due to technical or cost issues. This limits the realization of very high data-rate digital communication systems. In this paper, we propose a dual pulse shaping (DPS) transmission scheme, which can achieve full Nyquist rate transmission with only a half of the sampling rate for

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This Special Issue is a collection of selected papers presented at the IEEE Latin American Symposium on Circuits and Systems (LASCAS) 2019 that was held in Armenia, Quindio, Colombia, on February 24–27, 2019, and the IEEE NEWCAS 2019 Conference that was held in Munich, Germany, on June 23–26, 2019. As the flagship conferences of the IEEE Circuits and Systems Society (CASS) in the IEEE Regions 9 and

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In [1] , there are minor mistakes including the misuse of notations, the related description, the footnote and the reference. These minor mistakes do not influence on the discussion and the conclusions in the paper. The related mistakes are described as follows:

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This special section is a collection of selected papers presented at the IEEE International Symposium on Circuits and Systems (ISCAS) 2019 that was held in Sapporo, Japan, on May 26–29, 2019. As the flagship of the IEEE Circuits and Systems Society (CASS), ISCAS attracts researchers across all the main themes associated with the circuits and systems domain. ISCAS conferences are attended by more than

This paper presents an implantable fluorescence system with a composite emission filter and fiber-coupled laser excitation. The composite structure of the short-pass interference filter and absorption filters exhibited a band-pass spectrum between 510 and 570 nm, which is close to green fluorescent protein (GFP) emission. A high-quality excitation light was achieved by utilizing a blue laser through

In a more and more digital world, the protection of sensitive data is an essential challenge. Current cryptographic methods rely on one-way functions based on computationally challenging problems. However, there are several candidates for runtime efficient computing that might require new methods for data security. Among them are Universal Memcomputing Machines (UMM) for which a memristive circuit

This paper presents experimental results from a system that comprises a fully autonomous energy harvester with a solar cell of 1 mm 2 as energy transducer and a Power Management Unit (PMU) on the same silicon substrate, and an output voltage regulator. Both chips are implemented in standard $0.18~\mu \text{m}$ CMOS technology with total layout areas of 1.575 mm 2 and 0.0126 mm 2 , respectively. The

This work proposes a new theory to reduce the phase noise of K-band Voltage-Controlled Oscillators (VCOs) in Complementary Metal Oxide Semiconductor (CMOS) process by introducing one or more transmission poles around the parallel resonance of an LC-tank circuit. Introduction of transmission poles beside the parallel resonance of the LC-tank circuit sharpens the skirt characteristics of the Scattering

This paper describes the design of a touch screen panel (TSP) readout IC having an in-band noise immunity. The proposed IC employs a cascaded spread spectrum TSP driving scheme combining chirp spread spectrum (CSS) and pseudo-random (PR) orthogonal sequences. The CSS shows the 12-dB spread gain prior to an application of PR sequences, resulting in total -24-dB in-band noise immunity. The proposed IC

This paper proposes a low power 10-bit 2b/cycle time and voltage based-successive approximation register (SAR) analog-to-digital converter (ADC). At low supply voltage, there will be a significant difference in comparator decision time for different input voltages. By taking advantage of the fact, this ADC converts the reference voltage to the corresponding comparator decision time, achieving 2b/cycle

A continuous-time (CT) second-order $\Delta \Sigma $ current-to-digital converter (CDC) is presented in this paper. The proposed CDC uses two current-controlled ring oscillators as phase-domain integrators to achieve second-order quantization noise shaping. The proposed CDC uses a current-reuse architecture in which the feedback digital-to-analog converter (DAC) is used to bias the first integrator

This work presents a low-power all-digital approach to multiphase delay locked loop (DLL) design by the use of a scalable phase-to-digital converter (PDC) based on asynchronous sampling. The PDC is used as a linear phase detector (PD) with the ability to measure any phase difference leading to a shorter delay line with less power consumption. Two different approaches for the delay cell implementation

This article describes the cross-correlation function as an alternative method to adapt loop gain in digital CDRs. Cross-correlation function inherent properties and their link with the cross-power spectral density help consolidating the adaptive loop gain technique, XCALG, for clock and data recovery systems that implement bang-bang phase detector. Considering the modulation of the loop gain due to

A low power face recognition (FR) convolutional neural network (CNN) processor is proposed with high power efficiency to achieve always-on FR in mobile devices. Three key features enable a power-efficient FR CNN. First, tile-based clustering (THC) is proposed for reducing the computation overhead of hierarchical clustering. It generates an average of 37.2% duplicated input features in the entire network

Lyra2REv2 is a hashing algorithm that consists of a chain of individual hashing algorithms, and it is used as a proof-of-work function in several cryptocurrencies. The most crucial and exotic hashing algorithm in the Lyra2REv2 chain is a specific instance of the general Lyra2 algorithm. This work presents the first hardware implementation of the specific instance of Lyra2 that is used in Lyra2REv2

The rise of data-intensive applications has resulted in an increasing demand for high-density and low-power on-chip embedded memories. Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible alternative to conventional static random access memory (SRAM) which offers higher density, lower leakage power, and two-ported operation. However, in order to maintain the stored data, GC-eDRAM requires periodic

This work presents a compact CMOS Image Sensor (CIS) architecture enabling embedded object recognition facilitated by a dedicated end-of-column Compressive Sensing (CS), reducing on-chip memory needs. Our sensing scheme is based on a combination of random modulations and permutations leading to an implementation with very limited hardware impacts. It is designed to meet both theoretical ( i.e. , stable

Acceleration and compression on deep Convolutional Neural Networks (CNNs) have become a critical problem to develop intelligence on resource-constrained devices. Previous channel pruning can be easily deployed and accelerated without specialized hardware and software. However, weight-level redundancy is not well explored in channel pruning, which results in a relatively low compression ratio. In this

Block floating point quantization (BFPQ) exploits signal statistics so that one common exponent is shared among a block of data. The output signal-to-quantization-noise ratio (SQNR) may drop due to the increase in quantization error resulted from the increment of the exponent, especially for the non-uniformly distributed input signals. The tunable BFPQ is then proposed. With the aid of the tuning parameter

More compact Switch-Mode Power Supplies (SMPSs) satisfying typical design specifications can be obtained by exploiting ferrite core inductors working in partial saturation. In this case, the inductance is no longer a constant parameter, since it exhibits a sharp drop as the inductor current increases. A behavioral model was recently proposed, which provides the inductance at steady state as a function

Operating systems (OS) are critical infrastructures for information system. To design a highly reliable software, it is essential to understand the architecture feature of operating systems, which is recently explored by network analysis. While most focus is on the topological properties, the network reliability is rarely studied. In this paper, based on percolation method, we analyze the function-call

In this paper, the start-up response of a digitally controlled dc-dc boost converter with a constant power load is studied. A mathematical expression of the system response during start-up is derived using a nonlinear averaged model. The time-domain response of the system during start-up when the converter is operating under current limitation mode is derived by analytically integrating the mathematical

This paper studies the impacts of stochastic load fluctuations, namely the fluctuation intensity and the load power variation speed, on power system dynamic voltage stability. Additionally, the trade-off relationship between the two parameters is revealed, which provides important insights regarding the potential of using energy storage to maintain voltage stability under high uncertainty. To this

This paper presents implementation friendly VLSI-algorithms for maximum-eigenvalue-detection (MED), energy with minimum-eigenvalue (EME), and mean-to-square extreme-eigenvalue (MSEE) based blind spectrum sensing algorithms. We propose to use efficient iterative power-method for computing maximum and minimum eigenvalues for these algorithms that complemented our hardware design. New VLSI architectures

In recent years, the popularity of electric vehicles (EVs) has been rapidly expanding, thanks to the government’s supportive policies. However, managing EV’s en-route re-charge activities under different operation scenarios is still a critical issue, when the EV’s limited driving range and long re-charge time are concerned. In this paper, an EV flow distribution problem is formulated for the guidance

This paper presents a novel design methodology to turn the timing violation caused by aging into computation approximation error without the reliability guardband or increasing the supply voltage. It can be realized by accurately monitoring the critical path delay at run-time. We evaluate the proposal at two levels: RTL component level and system level. The experimental results at the RTL component

Recent state-of-the-art deep convolutional neural networks (CNNs) have shown remarkable success in current intelligent systems for various tasks, such as image/speech recognition and classification. A number of recent efforts have attempted to design custom inference engines based on processing-in-memory (PIM) architecture, where the memory array is used for weighted sum computation, thereby avoiding

This paper presents a fully-integrated integer- $N$ frequency synthesizer that uses switched-gain control (SGC) within the phased-locked loop (PLL). Unlike other methods to improve PLL performance, the SGC method exploits the potential advantages of positive feedback within the main loop. The proposed SGC-PLL uses a supervisor with four switching regions in the phase plane to minimize the effects of

A novel injection-locked phase locked loop (IL-PLL) with low spur and low phase noise is presented in this paper, in which self-feedback injection locked ring oscillator (SFIL-RO) and pseudo-random injection locked technique (PRILT) are presented. SFIL-RO, of which the oscillation signal is feedback to the input of the pulse generator to generate injection pulse, is proposed to achieve inherently aligned

Residue number systems (RNS) are characterized by fast modular arithmetic and low power dissipation. Numerous RNS applications take advantage of moduli set ${\tau }=\{{2}^{{{n}}}{-1,}{2}^{{{n}}},\,\,2^{{{n}}}+1\}$ , with nearly ${2}^{3n}$ dynamic range and fast parallel-prefix adders. However, the ${2}^{{{n}}}+1$ channel is ${4}{\Delta }{{G}}$ slower ( ${\Delta }{{G}} =$ simple 2-input gate delay)

In this work, voice activity detection (VAD) systems with system-level energy-quality (EQ) scaling are investigated. Compared to prior single-knob EQ scaling, multiple EQ knobs are selectively inserted into the entire signal chain from end to end. EQ knobs are dynamically co-optimized to minimize energy for a given quality target. The analysis shows that system-level EQ optimization provides several

If the memristor, used in each cell of a memristive variant of the standard space-invariant Cellular Nonlinear Network (CNN), undergoes analogue memductance changes, the processing element operates as a second-order system. The Dynamic Route Map (DRM) technique, applicable to investigate first-order systems only, is no longer relevant. In this manuscript, a recently introduced methodology, generalizing

This paper investigates the bipartite tracking problem of networked robotic systems (NRSs) subject to input disturbances, discrete communications and signed directed graphs. Two new classes of hierarchical hybrid control algorithms (HHCAs), which involve both continuous and discontinuous signals in a uniform framework, are designed to solve the aforementioned problem in the model-independent control

This paper investigates the suitability of full duplex simultaneous bidirectional (FD-SBD) signaling as a method to theoretically double the aggregate data transfer per pin for ultra-short-reach links. Advantages as well as challenges associated with differential FD-SBD links are described, and comparisons are made with single-ended and multilevel signaling schemes. FD-SBD links require a hybrid to

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In this paper, we propose a lattice-based encryption scheme for Identity-Based Encryption (IBE) which is secure against Chosen-Ciphertext Attacks (CCA), and it is deduced from a previous Chosen-Plaintext Attack (CPA) secure IBE scheme by applying Fujisaki-Okamoto transform. Also, we present the design of a lattice-based cryptoprocessor that performs the encryption or decryption of the proposed CCA

Carbon nanotube field effect transistor (CN-MOSFET) is attractive for the realization of future monolithic three-dimensional (M3D) memory circuits with ultra-high integration density, capacity, efficiency, and speed. However, the yield of each vertically-stacked active layer can be significantly degraded by the presence of metallic carbon nanotubes (m-CNs) caused by process imperfections. The potential

Bandpass power amplifiers (PAs) are typically implemented by a cascade of second-order topologies. To achieve a wide and flat passband response, the number of resonators must be increased, which leads to large size, high loss and low efficiency, especially at high frequencies. In this paper, a wideband Class-F −1 PA based on a microstrip multimode bandpass impedance transformer (BPIT) is proposed.

In this paper we present the Standard Cell Delay-based Dual-rail Pre-charge Logic (SC-DDPL), a novel logic style which is able to counteract Power Analysis Attacks (PAAs) also in the presence of capacitive mismatch at the output of dual-rail gates. The SC-DDPL is based on a standard-cell design flow and it is suitable to be implemented on ASICs or FPGAs without any routing constraint on differential

This paper presents a wakeup timer in 40-nm CMOS for Internet-of-Things (IoT) applications based on a bang-bang Digital-intensive Frequency-Locked Loop (DFLL). A self-biased $\Sigma \Delta $ Digitally Controlled Oscillator (DCO) is locked to an RC time constant via a feedback loop consisting of a single-bit chopped comparator and a digital loop filter, thus maximizing the use of digital circuits while

Coordinate rotation digital computer (CORDIC) is widely used in digital signal processing (DSP) to calculate functions. One of the elegant ways to accelerate CORDIC is employment of the redundant binary signed-digit (BSD) number systems, so-called BSD-CORDIC. This paper aims to achieve efficient BSD-CORDIC structures for generic/specific initial angles. First, three generic BSD-CORDIC algorithms are

With the aggressive scaling of transistor dimensions, intrinsic device gains are dropping but the need for high-gain amplifiers still exists, resulting in a great interest in multi-stage amplifiers. Most existing amplifier topologies rely on Miller capacitors which achieve stability at the expense of reduced speed. In this paper, a new state feedback compensation strategy with gain enhancement using