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This special section is a collection of selected papers presented at the IEEE International Symposium on Circuits and Systems (ISCAS) 2019 that was held in Sapporo, Japan, on May 26–29, 2019. As the flagship of the IEEE Circuits and Systems Society (CASS), ISCAS attracts researchers across all the main themes associated with the circuits and systems domain. ISCAS conferences are attended by more than

This paper presents an implantable fluorescence system with a composite emission filter and fiber-coupled laser excitation. The composite structure of the short-pass interference filter and absorption filters exhibited a band-pass spectrum between 510 and 570 nm, which is close to green fluorescent protein (GFP) emission. A high-quality excitation light was achieved by utilizing a blue laser through

In a more and more digital world, the protection of sensitive data is an essential challenge. Current cryptographic methods rely on one-way functions based on computationally challenging problems. However, there are several candidates for runtime efficient computing that might require new methods for data security. Among them are Universal Memcomputing Machines (UMM) for which a memristive circuit

This paper presents experimental results from a system that comprises a fully autonomous energy harvester with a solar cell of 1 mm 2 as energy transducer and a Power Management Unit (PMU) on the same silicon substrate, and an output voltage regulator. Both chips are implemented in standard $0.18~\mu \text{m}$ CMOS technology with total layout areas of 1.575 mm 2 and 0.0126 mm 2 , respectively. The

This work proposes a new theory to reduce the phase noise of K-band Voltage-Controlled Oscillators (VCOs) in Complementary Metal Oxide Semiconductor (CMOS) process by introducing one or more transmission poles around the parallel resonance of an LC-tank circuit. Introduction of transmission poles beside the parallel resonance of the LC-tank circuit sharpens the skirt characteristics of the Scattering

This paper describes the design of a touch screen panel (TSP) readout IC having an in-band noise immunity. The proposed IC employs a cascaded spread spectrum TSP driving scheme combining chirp spread spectrum (CSS) and pseudo-random (PR) orthogonal sequences. The CSS shows the 12-dB spread gain prior to an application of PR sequences, resulting in total -24-dB in-band noise immunity. The proposed IC

This paper proposes a low power 10-bit 2b/cycle time and voltage based-successive approximation register (SAR) analog-to-digital converter (ADC). At low supply voltage, there will be a significant difference in comparator decision time for different input voltages. By taking advantage of the fact, this ADC converts the reference voltage to the corresponding comparator decision time, achieving 2b/cycle

A continuous-time (CT) second-order $\Delta \Sigma $ current-to-digital converter (CDC) is presented in this paper. The proposed CDC uses two current-controlled ring oscillators as phase-domain integrators to achieve second-order quantization noise shaping. The proposed CDC uses a current-reuse architecture in which the feedback digital-to-analog converter (DAC) is used to bias the first integrator

This work presents a low-power all-digital approach to multiphase delay locked loop (DLL) design by the use of a scalable phase-to-digital converter (PDC) based on asynchronous sampling. The PDC is used as a linear phase detector (PD) with the ability to measure any phase difference leading to a shorter delay line with less power consumption. Two different approaches for the delay cell implementation

This article describes the cross-correlation function as an alternative method to adapt loop gain in digital CDRs. Cross-correlation function inherent properties and their link with the cross-power spectral density help consolidating the adaptive loop gain technique, XCALG, for clock and data recovery systems that implement bang-bang phase detector. Considering the modulation of the loop gain due to

A low power face recognition (FR) convolutional neural network (CNN) processor is proposed with high power efficiency to achieve always-on FR in mobile devices. Three key features enable a power-efficient FR CNN. First, tile-based clustering (THC) is proposed for reducing the computation overhead of hierarchical clustering. It generates an average of 37.2% duplicated input features in the entire network

Lyra2REv2 is a hashing algorithm that consists of a chain of individual hashing algorithms, and it is used as a proof-of-work function in several cryptocurrencies. The most crucial and exotic hashing algorithm in the Lyra2REv2 chain is a specific instance of the general Lyra2 algorithm. This work presents the first hardware implementation of the specific instance of Lyra2 that is used in Lyra2REv2

The rise of data-intensive applications has resulted in an increasing demand for high-density and low-power on-chip embedded memories. Gain-cell embedded DRAM (GC-eDRAM) is a logic-compatible alternative to conventional static random access memory (SRAM) which offers higher density, lower leakage power, and two-ported operation. However, in order to maintain the stored data, GC-eDRAM requires periodic

This work presents a compact CMOS Image Sensor (CIS) architecture enabling embedded object recognition facilitated by a dedicated end-of-column Compressive Sensing (CS), reducing on-chip memory needs. Our sensing scheme is based on a combination of random modulations and permutations leading to an implementation with very limited hardware impacts. It is designed to meet both theoretical ( i.e. , stable

Acceleration and compression on deep Convolutional Neural Networks (CNNs) have become a critical problem to develop intelligence on resource-constrained devices. Previous channel pruning can be easily deployed and accelerated without specialized hardware and software. However, weight-level redundancy is not well explored in channel pruning, which results in a relatively low compression ratio. In this

Block floating point quantization (BFPQ) exploits signal statistics so that one common exponent is shared among a block of data. The output signal-to-quantization-noise ratio (SQNR) may drop due to the increase in quantization error resulted from the increment of the exponent, especially for the non-uniformly distributed input signals. The tunable BFPQ is then proposed. With the aid of the tuning parameter

More compact Switch-Mode Power Supplies (SMPSs) satisfying typical design specifications can be obtained by exploiting ferrite core inductors working in partial saturation. In this case, the inductance is no longer a constant parameter, since it exhibits a sharp drop as the inductor current increases. A behavioral model was recently proposed, which provides the inductance at steady state as a function

Operating systems (OS) are critical infrastructures for information system. To design a highly reliable software, it is essential to understand the architecture feature of operating systems, which is recently explored by network analysis. While most focus is on the topological properties, the network reliability is rarely studied. In this paper, based on percolation method, we analyze the function-call

In this paper, the start-up response of a digitally controlled dc-dc boost converter with a constant power load is studied. A mathematical expression of the system response during start-up is derived using a nonlinear averaged model. The time-domain response of the system during start-up when the converter is operating under current limitation mode is derived by analytically integrating the mathematical

This paper studies the impacts of stochastic load fluctuations, namely the fluctuation intensity and the load power variation speed, on power system dynamic voltage stability. Additionally, the trade-off relationship between the two parameters is revealed, which provides important insights regarding the potential of using energy storage to maintain voltage stability under high uncertainty. To this

This paper presents implementation friendly VLSI-algorithms for maximum-eigenvalue-detection (MED), energy with minimum-eigenvalue (EME), and mean-to-square extreme-eigenvalue (MSEE) based blind spectrum sensing algorithms. We propose to use efficient iterative power-method for computing maximum and minimum eigenvalues for these algorithms that complemented our hardware design. New VLSI architectures

In recent years, the popularity of electric vehicles (EVs) has been rapidly expanding, thanks to the government’s supportive policies. However, managing EV’s en-route re-charge activities under different operation scenarios is still a critical issue, when the EV’s limited driving range and long re-charge time are concerned. In this paper, an EV flow distribution problem is formulated for the guidance

This paper presents a novel design methodology to turn the timing violation caused by aging into computation approximation error without the reliability guardband or increasing the supply voltage. It can be realized by accurately monitoring the critical path delay at run-time. We evaluate the proposal at two levels: RTL component level and system level. The experimental results at the RTL component

Recent state-of-the-art deep convolutional neural networks (CNNs) have shown remarkable success in current intelligent systems for various tasks, such as image/speech recognition and classification. A number of recent efforts have attempted to design custom inference engines based on processing-in-memory (PIM) architecture, where the memory array is used for weighted sum computation, thereby avoiding

This paper presents a fully-integrated integer- $N$ frequency synthesizer that uses switched-gain control (SGC) within the phased-locked loop (PLL). Unlike other methods to improve PLL performance, the SGC method exploits the potential advantages of positive feedback within the main loop. The proposed SGC-PLL uses a supervisor with four switching regions in the phase plane to minimize the effects of

A novel injection-locked phase locked loop (IL-PLL) with low spur and low phase noise is presented in this paper, in which self-feedback injection locked ring oscillator (SFIL-RO) and pseudo-random injection locked technique (PRILT) are presented. SFIL-RO, of which the oscillation signal is feedback to the input of the pulse generator to generate injection pulse, is proposed to achieve inherently aligned

Residue number systems (RNS) are characterized by fast modular arithmetic and low power dissipation. Numerous RNS applications take advantage of moduli set ${\tau }=\{{2}^{{{n}}}{-1,}{2}^{{{n}}},\,\,2^{{{n}}}+1\}$ , with nearly ${2}^{3n}$ dynamic range and fast parallel-prefix adders. However, the ${2}^{{{n}}}+1$ channel is ${4}{\Delta }{{G}}$ slower ( ${\Delta }{{G}} =$ simple 2-input gate delay)

In this work, voice activity detection (VAD) systems with system-level energy-quality (EQ) scaling are investigated. Compared to prior single-knob EQ scaling, multiple EQ knobs are selectively inserted into the entire signal chain from end to end. EQ knobs are dynamically co-optimized to minimize energy for a given quality target. The analysis shows that system-level EQ optimization provides several

If the memristor, used in each cell of a memristive variant of the standard space-invariant Cellular Nonlinear Network (CNN), undergoes analogue memductance changes, the processing element operates as a second-order system. The Dynamic Route Map (DRM) technique, applicable to investigate first-order systems only, is no longer relevant. In this manuscript, a recently introduced methodology, generalizing

This paper investigates the bipartite tracking problem of networked robotic systems (NRSs) subject to input disturbances, discrete communications and signed directed graphs. Two new classes of hierarchical hybrid control algorithms (HHCAs), which involve both continuous and discontinuous signals in a uniform framework, are designed to solve the aforementioned problem in the model-independent control

This paper investigates the suitability of full duplex simultaneous bidirectional (FD-SBD) signaling as a method to theoretically double the aggregate data transfer per pin for ultra-short-reach links. Advantages as well as challenges associated with differential FD-SBD links are described, and comparisons are made with single-ended and multilevel signaling schemes. FD-SBD links require a hybrid to

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The Multi-stAge noise SHaping Digital Delta-Sigma Modulator (MASH DDSM), which is commonly used as a divider controller in a fractional- $N$ frequency synthesizer, can produce a time-varying periodic pattern of tones in the output spectrum of the synthesizer; these are known as wandering spurs. In this work, a detailed analysis of the cause of wandering spur patterns in a MASH 1-1-1 DDSM-based fractional-

This paper analyzes the absolute jitter performance of digital phase-locked loops and compares the case when either a multi-bit time-to-digital converter with mid-rise characteristic or a bang-bang phase detector is adopted. The linear equivalent model of the PLL and expressions for random-noise and limit-cycle jitter are first derived for the case of a 2-bit time-to-digital converter with a mid-rise

This paper presents a linear-mode light detection and ranging (LiDAR) analog front-end architecture with multiplex analog-to-digital converter/time-to-digital converter (ADC/TDC). An added voltage-to-time converter (VTC) and a reused TDC are simultaneously used to implement the ADC and TDC function, thus replacing discrete ADC and TDC, saving hardware cost and reducing power consumption. A three-stage

Class-D amplifiers switch high voltages and currents at high frequencies and hence produce electromagnetic interference (EMI). This work presents a technique to reduce the high frequency ripple, which is still present after the output filter. A Class-A ripple reduction amplifier is put in parallel to the output of the Class-D amplifier, each having their own feedback loop with digital filters. High

In this article, the impact of the combination of the column-level gain and the correlated multiple sampling (CMS) on the noise of CMOS image sensor (CIS) readout chains is first analyzed. The theory is then validated experimentally with CIS readout chains embedding two different pixels, a variable gain column-level amplifier (CLA) and a passive switched-capacitor (SC) CMS circuit. The noise measurements

A novel quantitative design method is proposed herein for a 120-GHz 8-stage broadband amplifier using the stagger tuning technique. The pole frequencies of the unit amplifiers are determined by the parasitic capacitors and the size of the matching inductors, and resonance peaks are formed at the pole frequency. We proposed the stagger tuning technique at two different frequencies, where an inductance

This article describes the designing process of a low-cost class-D audio amplifier with digitized global feedback after the output filter, using a signal microcontroller. Various approaches to the feedback-based distortions elimination of class-D amplifiers are discussed. Hardware architecture of the author’s designed class-D amplifier with digital audio input interface, output voltage feedback path

A high-efficiency inverse Class-F (Class-F −1 ) power amplifier (PA) with a low voltage pHEMT is presented in this paper. The design process is based on a novel harmonic control network (HCN), consisting of a bias circuit (BC) and a low pass filter (LPF). The goal is reducing the impact of fundamental frequency reflection on DC supply, elimination of harmonics, improvement of power added efficiency

A high efficiency multi-mode class-E outphasing RF power amplifier (PA) with a passive combining circuit is presented. The multi-mode PA combines multiple class-E amplifier branches and can work in different configurations. The PA improves efficiency at lower power levels by switching ‘on’ and ‘off’ individual branches in a static or dynamic manner and using Efficiency Enhancement Circuit (EEC). The

This paper presents the design and experimental verification of two drivers designed to be compliant with the high radiation dose levels present in the inner layers of the CERN’s Large Hadron Collider (LHC) experimental chambers. The drivers, designed to face up to 800 Mrad (SiO 2 ) Total Ionizing Dose, are able to sustain up to 5 Gbps bit-rate links when integrated in a 65 nm CMOS technology. They

This paper presents the Zero-Crossing-Time-Difference Model (ZCTDM) for a Voltage-Controlled-Oscillator based Operational Transconductance Amplifier (VCO-OTA). The small-signal, linear, discrete-time model provides output current impulses at equidistant time intervals, with their magnitude proportional to the time difference between the zero-crossings of the two VCOs in the VCO-OTA. Compared to the

The ${n}$ -term Karatsuba algorithm (KA) is an extension of 2-term KA, which can obtain even fewer multiplications than the original one. The existing ${n}$ -term Karatsuba hybrid $\textit {GF}(2^{m})$ multipliers rely on factorization of ${m}$ or ${m}-1$ , so that put a confinement to these schemes. In this contribution, we use a new decomposition ${m}={n}\ell +{r}$ , such that $0\leq {r}< {n}$ and

Lattice based cryptography plays an important role in the construction of post-quantum cryptography, including key exchange, public key encryption as well as digital signature schemes. Dating back to 2016, a new key exchange scheme called NewHope was proposed by Alkim, Ducas, Pöppelmann, and Schwabe that based security on the quantum hardness of Ring Learning with Errors (RLWE) problem, and was later

First, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUCT) latch, featuring quadruple cross-coupled dual-interlocked-storage-cells (DICEs) with a C-element. Due to the existence of sufficient feedback loops, the latch can achieve complete DNU toleration. Second, this paper proposes an improved DNUCT latch (referred to as the TNUCT latch) by inserting a redundant level of C-elements

Binary arithmetic coding is a key part of recent video compression standards. Its throughput is limited by the inherent dependencies existing in the algorithm. As a consequence, a higher bin parallelism leads to lower clock frequencies. This paper presents an architecture able to exceed limits existing in previous hardware implementations. The architecture exploits less probable symbols as starting

In this paper, we consider the problem of estimating multiple parameter vectors over a sensor network in a multitasking framework and under temporally-correlated input conditions. For this, an efficient clustered multitask diffusion affine projection algorithm (APA) is proposed that enjoys both intra-cluster and inter-cluster cooperation via diffusion. It is, however, shown that while collaboration

To overcome the energy and bandwidth limitations of traditional IoT systems, “edge computing” or information extraction at the sensor node has become popular. However, now it is important to create very low energy information extraction or pattern recognition systems. In this paper, we present an approximate computing method to reduce the computation energy of a specific type of IoT system used for

In many natural and man-made networks, nodes communicate with each other through different types of interconnections giving rise to so-called multiplex networks. In this paper, we study the interplay between synchronous steady state solutions and the topology of multiplex networks of Chua’s circuits. In particular, we consider all circuits to be simultaneously interconnected through a network of resistors

Well understanding the access behavior of hot data is significant for NAND flash memory due to its crucial impact on the efficiency of garbage collection (GC) and wear leveling (WL), which respectively dominate the performance and life span of SSD. Generally, both GC and WL rely greatly on the recognition accuracy of hot data identification (HDI). However, in this paper, the first time we propose a

This work investigates the observer-based asynchronous fault detection problem for a class of nonlinear Markov jumping systems. The conic-type nonlinearities hold such a restrictive condition that locates in a known hypersphere with an undefined centre. In order to guarantee the observer modes run synchronously with the system modes, we introduce a hidden Markov model to deal with this difficulty.

In many memristor models the internal variable is related to the width of a conductive layer and is therefore limited by the physical dimensions of the device. The necessity of keeping the internal variable within allowable limits may introduce discontinuities in right hand sides of differential equations describing dynamics of circuits with memristors. Such discontinuities are difficult to handle

This article presents an approximate signed digit representation (ASD) which quantizes the weights of convolutional neural networks (CNNs) in order to make multiplier-less CNNs without performing any retraining process. Unlike the existing methods that necessitate retraining for weight quantization, the proposed method directly converts full-precision weights of CNN models into low-precision ones,

Broad Learning System (BLS) are widely used in many fields because of its strong feature extraction ability and high computational efficiency. However, the BLS is mainly used in supervised learning, which greatly limits the applicability of the BLS. And the obtained data is less labeled data, but is a large number of unlabeled data. Therefore, the BLS is extended based on the semi-supervised learning