This review paper presents an overview of readout architectures and analog-to-digital converters (ADCs) for 3D-stacked CMOS image sensors (CIS) with their advantages and challenges. Depending on the application requirements, a suitable 3D-stacked readout architecture will be proposed. While most ADCs to date have been reported in planar CIS, this paper ports these designs to a 3D-stacked CIS and compares

This Special Issue is a selection of the best articles presented at the 18th IEEE International NEWCAS Conference (NEWCAS) 2020 that was held in Montreal, Canada, on June 16–19, 2020. As an Interregional flagship conference of the IEEE Circuits and Systems Society (CASS), this conference covers a wide spectrum of topics, research, and practice in the fields of circuits and systems, and offers an international

Power consumption is an important limitation in designing analog-to-digital converters (ADCs) used in low-power sensing applications. This paper estimates analytically the power bound of a two-step multi-stage noise-shaping successive-approximation-register incremental ADC (two-step MASH NS-SAR IADC) proposed in our previous work. Our model considers the impacts of thermal noise, mismatch, and CMOS

In this paper, dual-mode oval dielectric resonator (DR) is proposed as common resonator to realize all four kinds of balanced and unbalanced duplexers. The conventional topology is replaced with the novel one of sharing input and output dual-mode resonators at the same time for miniaturization. By adjusting the aspect ratio and height of the oval DR, the two modes are separated properly to form two

Incremental delta-sigma data converters are useful in applications where one ADC is needed to digitize multiple channels. They can be realized using single- or multi-bit feedback. In both cases, the use of FIR feedback is beneficial in terms of improving the modulator’s linearity, reducing the quantizer’s complexity, and mitigating the effects of clock jitter (in a continuous-time realization). In

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time $\Delta \Sigma $ modulator (CT $\Delta \Sigma \text{M}$ ) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and $1/f$ noise. However, the chopping artifacts in the modulator loop degrade the in-band

In this paper a novel triple hole block layer (HBL) structure of the OLED is proposed that depicts an enhanced luminescence of 25285 cd/m 2 with an improvement of 47% over multilayered OLED architecture. It also owes 74% improvement in luminous power efficiency. An in-depth numerical analysis based on Poisson and drift diffusion equation is undertaken and validated against the internal device analysis

This paper proposes a Differential-Input Body Bias Sense Amplifier (DIBBSA) with an auto-offset mitigation feature suitable for low-voltage SRAMs where the differential bitline signals are applied to the sources as well as to the body of the critical sensing transistors. We simulated and fabricated the proposed DIBBSA architecture with various operational modes in 65-nm CMOS technology to analyze body

Depthwise separable convolution (DSC) has become one of the essential structures for lightweight convolutional neural networks. Nevertheless, its hardware architecture has not received much attention. Several previous hardware designs incur either high off-chip memory traffic or large on-chip memory usage, and hence have deficiency in terms of hardware efficiency as well as performance. This paper

This paper proposes a low-complexity method and architecture to compute the logarithm of complex numbers based on coordinate rotation digital computer (CORDIC). Our method takes advantage of the vector mode of circular CORDIC and hyperbolic CORDIC, which only needs shift-add operations in its hardware implementation. Our architecture has lower design complexity and higher performance compared with

This paper presents a charge-domain in-memory computing (IMC) macro for precision-scalable deep neural network accelerators. The proposed Dual-SRAM cell structure with coupling capacitors enables charge-domain multiply and accumulate (MAC) operation with variable-precision signed weights. Unlike prior charge-domain IMC macros that only support binary neural networks or digitally compute weighted sums

With aggressive scaling of transistor size and supply voltage, the critical charge of the sensitive nodes is reducing rapidly. As a result, when these deep submicron devices are used in memory cells in the space environment, single-event upsets (SEUs), also known as soft-errors, pose a great threat to the reliability of the cells. To mitigate the effects of SEUs, we propose a soft-error-immune rea

Approximate computing is an efficient approach for reducing computational costs. This method involves a trade-off between computational accuracy and the circuit’s power consumption, delay, and area. However, the accuracy requirements may differ for different applications. In some situations, precise results are required. Therefore, this paper proposes an accuracy-configurable radix-4 adder (ACRA),

Data transfer across DRAM channels accounts for nearly a quarter of the total energy consumption of DDR4 DRAMs. Modern applications with high bandwidth requirements further increase channel energy consumption. However, channel energy consumption is dependent on data being transferred. Pseudo Open Drain (POD) asymmetric termination, used in current DDR4 systems, consumes energy only when 1’s are being

The estimation of the Direction of Arrival (DoA) is one of the most critical parameters for target recognition, identification and classification. MUltiple SIgnal Classification (MUSIC) is a powerful technique for DoA estimation. The algorithm requires complex mathematical operations like the computation of the covariance matrix for the input signals, eigenvalue decomposition and signal peak search

A general-purpose analog computing method is proposed to compute the continuous-time solutions of nonlinear partial differential equations (PDEs). The discrete-time difference operator in the standard finite difference time domain (FDTD) method is replaced by continuous-time delay operators that can be realized using analog all-pass filters. The resulting spatially discrete time-continuous (SDTC) update

In-Memory Computing (IMC), which takes advantage of analog multiplication-accumulation (MAC) insides memory, is promising to alleviate the Von-Neumann bottleneck and improve the energy efficiency of deep neural networks (DNNs). Since the time-domain (TD) computing is also an energy-efficient analog computing paradigm, we present an 8kb mixed-signal IMC macro, TD-SRAM, by combining IMC with TD computing

Ring oscillators, with capacitive load intended for frequency tuning, can fail to sustain stable oscillations. Failure depends on the size of the load capacitors and their equivalent series resistance. This paper first describes the failing mechanism from an intuitive perspective. It then develops an analytical model and provides the equations for the minimum load capacitance and the range of equivalent

Nowadays, research, modeling, simulation and realization of brain-like systems to reproduce brain behaviors have become urgent requirements. In this paper, neural bursting and synchronization are imitated by modeling two neural network models based on the Hopfield neural network (HNN). The first neural network model consists of four neurons, which correspond to realizing neural bursting firings. Theoretical

In this paper, a method for offline training of inverter-based memristive neural networks ( IM -NNs), called ERIM, is presented. In this method, the output voltage of the inverter is modeled very accurately by considering the loading effect of the memristive crossbar. To properly choose the size of each inverter, its output load and the required slope of its voltage transfer characteristic (VTC) for

This paper addresses the problem of simultaneous fault detection and control (SFDC) for Markov jump systems (MJSs) over sensor networks. In order to save the bandwidth of the network, round-Robin protocol is adopted for the communication between the sensors and fault detection filter. First, to fully utilize the data of sensor networks, a new distributed system is developed especially for SFDC, and

Predefined mymargin finite-time output containment control problem for nonlinear multi-agent systems with multiple dynamical leaders under directed topology is investigated, where the outputs of followers can converge to the predefined convex hull formed by the multiple leaders within a finite time, and the leaders can have unknown control inputs. Firstly, for the directed topological structure among

In this paper, a two-stage reconfiguration strategy is proposed for a group of agents to find their specially designated formation, which can be seen as a transition from the current states to the predefined formations. The specially designated formation occurs during the inter-task idle time in order to minimize the reconfiguration time. The basic specially designated formation is designed for dotted

This paper is concerned with the almost sure exponential synchronization of a multilayer network which is set up on a non-strongly connected digraph that can be classified into several layers by Tarjan’s algorithm. Note that, in the multilayer network, white-noise-based time-varying coupling and drift term coupling are proposed to simulate two kinds of coexisting distinguishable interactions between

This paper proposes two kinds of algorithms to achieve privacy-preserving consensus of multi-agent systems over undirected graphs via node decomposition mechanism and homomorphic cryptography technique. Based on the number of neighboring nodes ( $|\mathscr {N}_{i}|$ ), every agent is decomposed into $|\mathscr {N}_{i}|$ subagents, which are connected as a chain graph. Note that every subagent connects

In this paper, hybrid dynamical systems theory is applied to the analysis and control of switched converters with Pulse-Width Modulated (PWM) inputs. The system is described by a state-space model with continuous flows and discrete jumps, without averaged equations. The modulation effects are captured in full without using time-dependent signals, by enlarging the state vector to include the PWM waveform

Sparse code multiple access (SCMA) is a promising technology for the development of wireless communication, which supports a large number of overloading users and enjoys high spectral efficiency. However, conventional SCMA decoders suffer very high complexity in implementations. Changing the updating scheme is a superior approach to reduce complexity, which guarantees the updated information immediately

The multi-band and spectrally flexible transmission requires a wideband transmitter system to cover a wider frequency band of interest. A wideband power amplifier (PA) is required to achieve the desired signal strength for covering long-distance communication. Due to PA’s nonlinear characteristics, spectral growth and harmonics occur, which may cause interference with the other band of interest. This

This paper presents an iterative decimation approach to significantly alleviate the computational burden of centralized controllers applying real-time recursive system identification algorithms in multi-rail power converters. The proposed approach uses an adaptive update rate as opposed to the fixed update rate used in conventional adaptive filters. Also, the step size/forgetting factors vary at different

Presents the table of contents for this issue of the publication.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

To efficiently deploy machine learning applications to the edge, compute-in-memory (CIM) based hardware accelerator is a promising solution with improved throughput and energy efficiency. Instant-on inference is further enabled by emerging non-volatile memory technologies such as resistive random access memory (RRAM). This paper reviews the recent progresses of the RRAM based CIM accelerator design

This paper presents a low-power single-channel 8-bit loop-unrolled (LU) successive approximation register (SAR) analog-to-digital-converter (ADC) with a novel common-mode adaptive background comparator offset calibration scheme. LU-SAR ADCs use multiple comparators to reduce the SAR loop delay. Offset mismatch between the comparators severely degrades the effective resolution. This paper addresses

This work introduces an accurate linearized model and phase noise spectral analysis of digital bang-bang PLLs, that includes both the reference and the digitally-controlled oscillator (DCO) noise contributions. A time-domain analysis of bang-bang PLLs is leveraged to derive closed-form expressions for the integrated jitter, leading to a precise estimation of the binary phase detector (BPD) equivalent

This paper presents a highly sensitive phase-variation sensor for dielectric constant measurements based on a capacitively-loaded periodic slow-wave transmission line. Such line is implemented in microstrip technology, and the loading capacitors are formed by closely spaced rectangular patches. The sensing area of the device is delimited by the region occupied by the capacitive patches, where the material

The paper presents a generalization of the Groszkowski’s result in differential oscillators, providing novel equations to describe the oscillation frequency dependence on the harmonic content. The effect of the common-mode oscillation is rigorously included. Moreover, an additional term, arising from the dependence of the transistor current on the drain voltage, which is dominant any time ohmic operation

An asynchronous event-driven approach to clocking and timing control is explored in the context of pipelined ADCs. It is shown how a conventional global clock tree can be replaced by localized control units coordinated through inter-stage communication protocols. The approach is found to yield many compelling advantages in terms of power efficiency, speed, robustness, and reconfigurability. It is shown

In this work, we focus on the three most relevant pseudo-digital ring oscillator circuits for VCO A/D conversion. First, we show that they can be accurately modeled by an equivalent 2-terminal diode-like element. Next, we study the main analog performance figures: the effective oscillation frequency (which affects the quantization noise of a VCO ADC), the input referred noise and the power efficiency

Deep learning has achieved excellent results in many fields due to powerful feature extraction and learning ability. In this study, an improved method for analog circuit fault diagnosis based on a deep residual network is presented. The proposed method utilizes a ResNet to extract the performance characteristics of an analog circuit and determine the fault type of a component to realize the fault diagnosis

Deep learning (DL) has gained unprecedented success in many real-world applications. However, DL poses difficulties for efficient hardware implementation due to the needs of a complex gradient-based learning algorithm and the required high memory bandwidth for synaptic weight storage, especially in today’s data-intensive environment. Computing-in-memory (CIM) strategies have emerged as an alternative

This paper presents an IC implementation of on-chip learning neural network accelerator using highly linear CMOS-compatible floating gate charge trap devices. A simple learning algorithm utilizing winner-take-all and competitive learning is proposed to design fast and power-efficient hardware. This algorithm was analyzed with behavioral model of emerging non-volatile memory via MATLAB. The linearity

This paper presents a new time-based pipelined analog-to-digital converter (ADC) with multiplying-DAC (MDAC) stages capable of robust $2 \times $ residue amplification by subtracting two pulse widths. First, the input voltage is converted into two timing pulses containing the information of the time difference between their rising edges. Each MDAC stage performs 1.5-bit quantization and generates two

This work describes a hybrid incremental ADC (IADC) with two-capacitor (2-C) successive-approximation registers (SAR) extended counting in two-step operation to achieve high resolution data conversion. The circuits in the first step is acting as a first-order incremental analog-to-digital converter (IADC). Finite impulse response (FIR) DAC is incorporated in the loop filter to reduce the transient

Resistive random-access memory (ReRAM) memristors are promising candidates for various compute in memory and flow-based computing approaches. As an alternative to traditional von Neumann computation, flow-based computing avoids serial movement of data between memory and processor. In this paper, we demonstrate arrays of 1 transistor 1 ReRAM (1T1R) to detect edges between 8 bit pixels using flow-based

Pairs trading is a solidly profitable strategy in the algorithmic trading area, and an important step of this strategy is selecting pairs of stocks. Compared with other existing pairs selection approaches, the Engle-Granger cointegration is more stable and reliable. Nowadays, as trading is becoming faster and faster in stock markets all over the world, it is necessary to accelerate the pairs selection

In an 8B/10B mode giga-bit-per-second serial data transactions, the de-serialized data is sent to a comma detection and word alignment (CDWA) module to identify the word boundaries, which is a prerequisite in the high-speed transceivers such as PCIe, USB and JESD204B/C. In order to ensure that the comma code (/K/-code) can be correctly detected. Ten 10-bit comma detector cells are adopted in a typical

Designing hardware accelerators for convolutional neural networks (CNNs) has recently attracted tremendous attention. Plenty of existing accelerators are built for dense CNNs or structured sparse CNNs. By contrast, unstructured sparse CNNs can achieve higher compression ratio with equivalent accuracy. However, their corresponding hardware implementations generally suffer from load imbalance and conflict

In this paper, we present a novel approximate computing scheme suitable for realizing the energy-efficient multiply-accumulate (MAC) processing. In contrast to the prior works that suffer from the error accumulation limiting the approximate range, we utilize different approximate multipliers in an interleaved way to compensate errors in the opposite direction during accumulate operations. For the balanced

Conventional hardened cells are not robust enough to single event upset (SEU) in 28nm technology due to the scaling of the transistors. High soft error rate is caused by particle striking at cells and logic circuit in SRAM. This work proposes an SEU robust dual access 12T (DA-12T) SRAM with a radiation hardened crossbar-based peripheral circuit (CBPC). The proposed cell with 209% area penalty is more

Nowadays, with the increasing shortage of traditional medical resources, the existing portable monitoring healthcare device is no longer satisfactory. Thus, wearable healthcare device with diagnostic capability is becoming much more desirable. However, the design of wearable healthcare device faces the challenge of limited hardware resource and high diagnostic accuracy. In this paper, an efficient

This paper proposes a novel scheme for energy-efficient transmitter design using optimized multi-level DSM (OML-DSM) along with time-interleaved level splitting technique. This scheme significantly improves the overall transmitter efficiency by providing high coding efficiency (CE) at the DSM stage and high drain efficiency (DE) at the amplification stage. The position of quantization level and quantization

In this paper, a novel multi-stream spatial digital predistortion (DPD) technique is proposed to model and linearize the fully-connected (FC) hybrid beamforming (HBF) transmitters. The proposed scheme solves the DPD implementation issue in the FC HBF array by estimating and linearizing the beam signals instead of the individual PAs. In FC HBF systems, significant intermodulation (IMD) between different

Chaos has been successfully applied in many fields to improve the performance of engineering systems, such as communication, vibration compact, and mixing. Generating chaos from originally non-chaotic systems is a relevant topic because of potential applications. In this work, the impulse control is shown to generate chaos from non-chaotic system. Using non-chaotic Chen system as an example, we prove

In this paper we address the problem of controlling chaos by using a selective filter inserted in a negative feedback loop. This has been achieved in driven double-well Duffing oscillator in a parameter region exhibiting both a boundary crisis and generalized bistability. The optimization of the filter response allows us to improve the reduction of the control signal when the periodic solution competing

Spread spectrum clocking (SSC) conventionally uses frequency modulation (FM) to suppress digital switching noise in the frequency domain. While clock-FM effectively reduces spectral noise peaks, it maintains the synchronous operation per cycle with total noise unchanged. In this paper, we introduce plesiochronous design as a general applicable de-synchronization solution for the spectral switching

With the continuous scaling-down of transistors, the soft error issue of the combinational circuit becomes more serious. Triple Modular Redundancy (TMR) and Gate-Sizing (GS) are commonly used hardening methods for combinational circuits. However, the traditional TMR method is often applied at the module level, causing a large area overhead. Therefore, to explore the feasibility of refined and more

The problem of fuzzy-based adaptive event-triggered tracking control is investigated for a class of non-strict-feedback nonlinear systems within fixed-time interval in this paper. Fuzzy logic system (FLS) is employed to approximate the packaged unknown nonlinearities. Event-triggered mechanism is employed to schedule the data transmission dependent upon errors exceeding certain threshold. And combining

This paper concerns the predefined-time bipartite consensus control for uncertain nonlinear multiagent systems under a signed directed topology. All agents have high-order uncertain nonlinear dynamic characteristics satisfying a time-varying Lipschitz growth condition, and their partial state information is not available for measurement. In this case, we put forward a novel output-feedback-based predefined-time

This work focuses on variable limits of conditional anti-windup PI-controller described in the IEEE Std. 421.5-2016 applied in the current limiters of VSC-based applications. To overcome deadlock and chattering during numerical simulation of the Std. conditional anti-windup with variable limits, it proposes a method for software implementation based on Filippov theory. The robustness of the proposed

With the increasing integration of various renewable energy resources into electric power systems, the stochastic power flow calculation, which falls into the uncertainty propagation (UP) problems, has attracted renewed interest recently. The adaptive sparse pseudospectral approximation method (A-SPAM) is highly efficient to solve UP problems. However, there still exist two major drawbacks: 1) its