Presents the table of contents for this issue of the publication.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

The thirty-two papers in this special section were presented at the European Solid- State Device Research Conference and European Solid-State Circuits Conference (ESSDERC-ESSCIRC) in 2020.

A novel method for extracting threshold voltage and substrate effect parameters of MOSFETs with constant current bias at all levels of inversion is presented. This generalized constant-current (GCC) method exploits the charge-based model of MOSFETs to extract threshold voltage and other substrate-effect-related parameters. The method is applicable over a wide range of current throughout weak and moderate

This work presents the performance and low-frequency noise (LFN) of 22-nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The experimental measurements and the analysis are performed as a function of temperature for the first time, focusing on cryogenic applications, down to 4.2 K. The back bias impact on device performance is evaluated. The results reveal that the threshold voltage tuning

This article presents a new methodology for the extraction of low-frequency noise (LFN) or random telegraph noise (RTN) parameters, such as the gate oxide interface trap density, ${N}_{\text {t}}$ , and the mobility fluctuations factor, $\Omega $ , without the influence of the source/drain series resistance, ${R}_{\text {sd}}$ . The method utilizes the ${Y}$ -function—which is immune to any first-order

To pave the way for system-on-chip MEMS confinement up to 50 GHz, the mechanical properties of a CMOS back-end-of-line (BEOL) are studied by analytic and finite element approaches. In particular, the two main directions of vertical and horizontal wave propagation are investigated. With respect to the symmetry of the BEOL, the movement through the nonperiodic horizontal layers is described by the Rayleigh-Lamb

Independent back bias in the ultrathin body and Box (UTBB) fully depleted silicon-on-insulator (FDSOI) serves as the critical knob for exploiting the performance and power tradeoffs and process/aging compensation. The effectiveness of back bias is one of the major metrics in the stages of circuit design and runtime feedback. In this article, new closed-form expressions accounting for the interface

This article focuses on one of the floating body effects in silicon-on-insulator (SOI) substrates, the out-of-equilibrium body potential. Unlike the already existing studies which explore either SOI fully fabricated devices or SOI wafers measured with pressure probes, here the out-of-equilibrium body potential is explored in SOI substrates with deposited metal contacts. Chromium and gold/titanium contacts

In this work, an evaluation of the performance of discrete elements intended for an ${L}$ -band high-temperature GaN-based LC -oscillator is carried out between room temperature and 300 °C. GaN high-electron mobility transistors (HEMTs) on sapphire substrate, metal–insulator–metal (MIM) capacitors, thin-film inductors, and resistors on sapphire and quartz substrates are fabricated and characterized

To enable CMOS-compatible GaN HEMTs for the next generation of communication systems (5G and beyond), a low gate resistance is of great importance since it directly affects the RF power gain and ${f}_{\text {MAX}}$ of the transistor. In this article, the impact of various gate-metal stacks on the gate resistance and RF performance of the devices is studied. The optimized Ti-free gate-metal process

An analysis of hot-electron (HE) effects on the dynamic resistance ( ${dR}\,_{\mathrm{\scriptstyle ON}}$ ) of AlGaN/GaN high-electron-mobility transistors (HEMTs) when subject to semi-ON stress is reported and compared with OFF-state stress. This is carried out using measurements and TCAD 2-D hydrodynamic simulations. Two structures with different distances between the highly carbon-doped buffer region

We investigate the reliability of state-of-the-art SiGe heterojunction bipolar transistors (HBTs) in 55-nm technology under mixed-mode stress. We perform electrical characterization and implement a TCAD model calibrated on the measurement data to describe the increased base current degradation at different collector-base voltages. We introduce a simple and self-consistent simulation methodology that

Logic-in-memory (LiM) circuits based on resistive random access memory (RRAM) devices and the material implication logic are promising candidates for the development of low-power computing devices that could fulfill the growing demand of distributed computing systems. However, these circuits are affected by many reliability challenges that arise from device nonidealities (e.g., variability) and the

We propose, for the first time, an indium gallium zinc oxide (IGZO)-based 2T1C compute cell (IGZO-cell) for analog in-memory computing. To assess the impact of an IGZO-cell-based array including the periphery on power and accuracy, a PyTorch framework was developed to analytically modeled analog components. The results are reported for a ResNet20 network on the Canadian Institute For Advanced Research-10

The requirement of multilevel cell (MLC) resistive random access memory (RRAM) for computing is different than that for MLC storage. It generally requires a linearly spaced conductance median and an ultratight conductance distribution, as the column current are summed up for analog computation. In this article, 3-bit per cell RRAM that is suitable for accurate inference of a deep neural network (DNN)

This article explores the feasibility of high-temperature annealing for top-tier devices in a sequential 3-D (Seq3D) technology. Thermally stable bottom-tier device and interconnect design guidelines are provided. CMOS–SRAM partitioning is proposed to achieve performance gain from Seq3-D. The implications of thermally stable Seq3-D on system-level performance are evaluated. Seq3-D wafer and die cost

The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while

In this article, we have studied the drain current and transconductance of nMOS fully depleted silicon-on-insulator (FDSOI) transistors operating at low temperature (typically < 20 K) when back gate is forward biased. Humps appear in the current, leading to oscillations of the transconductance with gate voltage, owing to mobility discontinuity due to intersubband scattering, in relation with the 2-D

We present a novel ultrathin avalanche photodiode (APD) with a silicon (Si) body thickness of 640 nm and optimized doping profiles to significantly improve the detection efficiency in ultraviolet (UV) spectral range from near UV (NUV) to UV-C (here studied down to 275 nm). The square photodiode is fabricated on silicon-on-insulator (SOI) substrate with an active area of $420~ \mu \text{m}^{2}$ ( $37\

A new differential method for accurate extraction of electrical parameters of high-electron mobility transistor (HEMT) devices for gallium nitride (GaN) technology is proposed. This method, presented here for the first time, is used to study the mobility degradation with gate length, allowing an analysis of the contribution of the gate edge region to the total metal–insulator semiconductor (MIS)-HEMT

This article provides guidelines to design porous silicon (PS) layers regarding optimization of small-signal properties in passive structures for radio frequency (RF): insertion loss and crosstalk. Results are based on high-frequency measurements on 200-mm wafers and electromagnetic simulations up to 40 GHz. Using substrate resistivity below ${1}~\Omega $ cm allows the best tradeoff with minimized

In this brief, extraction methods are proposed for determining the essential parameters of double gate junction field-effect transistors (FETs). First, a novel method for determining free carrier effective mobility, similar to a recently proposed method for MOSFETs, is developed. The same method is then extended to cover also the case when series resistance is present, while series resistance itself

In this study, the local variation of the effective channel reduction parameter ( ${\Delta }{L}={L}_{\text {m}}-{L}_{\text {eff}}$ ) of a MOSFET is extracted by means of the traditional shift-and-ratio (SAR) method. ${\Delta }{L}$ is then correlated with the threshold voltage difference ( ${\Delta }{V}_{\text {TH}}$ ) between the device under test (DUT) and the reference device. It is demonstrated

In this study, a consistent analytical charge-based model for the bias-dependent variability of the drain current of organic thin-film transistors is presented. The proposed model combines both charge-carrier-number-fluctuation effects and correlated-mobility-fluctuation effects to predict the drain-current variation and is verified using experimental data acquired from a statistical population of

A charge-based macromodel for small-signal ac and transient analyses of organic thin-film transistors (TFTs) is presented. Due to the comparatively small charge-carrier mobility in organic TFTs, the dynamic behavior of the gate-field-induced carrier channel is greatly affected by the frequency of the applied gate–source and drain–source voltages. The model presented here is, therefore, based on the

Previous work has shown that optomechanical resonators are particularly well suited to the design of ultrasensitive mass sensors. They present an extremely low noise level, very high optical quality factor ( ${Q}>{10}^{5}$ ), excellent integration density and can resonate both in a gaseous and liquid environment. In order to reduce the long measurement time due to their small particle-capture area

The use of new materials with advanced properties has become mandatory to meet the needs for higher electronics performance at reduced power. Topological insulators (TIs) possess highly conductive topologically protected edge states which are insensitive to scattering and thus suitable for energy-efficient high-speed devices. Here, we evaluate the subband structure in a narrow nanoribbon of 1 $\text

A technology computer-aided design (TCAD) simulation framework of gas desorption induced by self-heating in carbon nanotube (CNT) field effect transistor (FET) gas sensors is presented. Its key feature is the use of temperature profiles extracted from electrothermal simulations to determine the change of the effective gas-induced doping concentration during the gas desorption phase. The approach allows

In this work, we have investigated the influence of ${V}_{\text {t}}$ extraction procedure on overall ${V}_{\text {t}}$ variability of sub-10 nm ${W}_{\text {fin}}$ FinFETs. Using six different ${V}_{\text {t}}$ extraction techniques, we have experimentally demonstrated that the ${V}_{\text {t}}$ variability is independent of ${V}_{\text {t}}$ extraction procedure (unlike reported earlier). Furthermore

This article demonstrates low supply voltage ( ${V}_{{\text {DD}}}{)}$ and high-frequency polarization switching in an organic ferroelectric capacitor (OFEC). The Landau–Khalatnikov (LK) equation is used to model the organic ferroelectric (OFE) in the Sentaurus technology computer-aided design (TCAD) environment considering multidomain (MD) dynamics and interaction factor ( ${K}_{{\text {OFE}}}{)}$

Analytic doping profiles and contact resistivities are adjusted to reproduce measured transfer characteristics of state-of-the-art n-type and p-type FinFETs by Monte Carlo device simulation. The results are used to compare the performance of nanosheets (NSs) and FinFETs at advanced-node device dimensions. It is found that the ON-current normalized by the effective gate width reduces for a higher number

The performance of 15-nm-gate-length MOSFETs based on silicene nanoribbons (SiNRs) is analyzed with respect to width scaling, series resistance, and ballisticity of electron transport. Numerical simulations were based on quantum transport with atomic resolution of nanoribbon Hamiltonians and their bandstructure. Assuming negligible tunneling, we found that SiNR MOSFETs in which the nanoribbons are

The impact of different process options on the low-frequency noise (LFN) performance and reliability of Ge nFinFETs is investigated. The results show that the LFN is mainly determined by carrier number fluctuations, and the density of traps in the high- $\kappa $ dielectric can be reduced by an extended dry clean. In some small-size devices, the Lorentzian-type noise comes from GR centers in the oxide

Fluctuating parametric shifts that arise from the stochastic capture/emission by oxide traps in small gate-area MOSFETs have triggered considerable interest due to their impact on timing-sensitive circuits. To date, studies have only reported the effect of gate voltage stress on oxide traps, while the effect of drain voltage stress is equally important but is seldom studied. This work examines the

This article explores the scope of drain-extended FinFET (DeFinFET) as a high-voltage (HV) device contender for Fin-based SoC applications. For the first time, guidelines for efficient and reliable HV integration in sub-14 nm FinFET nodes are given. Up to what extent DeFinFET stands as a promising choice is carefully investigated through device-circuit interactions and reliability analysis of range

Substrate-bias-affected unique electrical characteristics of junctionless transistors (JLTs) were investigated in detail. Bulk channel thickness of JLTs ( ${t}_{\mathrm {si\_{}eff}}$ ) was effectively modulated by back-gate bias ( ${V}_{\text {gb}}$ ). The variation in threshold voltage ( ${V}_{\text {th}}$ ) $\vphantom {^{\int }}$ and mobility degradation were observed in the reduced ${t}_{\mathrm

A stochastic reaction–diffusion drift model is used to simulate the time kinetics of interface and bulk oxide traps responsible for bias temperature instability (BTI), stress-induced leakage current (SILC), and time-dependent dielectric breakdown (TDDB) in MOSFETs. Trap generation and passivation are calculated using dissociation and repassivation of trap precursors and simultaneous diffusion and/or

The time kinetics of hot carrier degradation (HCD) is modeled using a reaction diffusion drift (RDD) framework. It is incorporated into Sentaurus Device TCAD and validated using conduction mode HCD data in n- and p-channel MOSFETs and FinFETs. RDD-enabled TCAD calculates carrier-energy-initiated generation of interface traps ( $\Delta {N}_{\text {IT}}$ ) and the impact of the resulting localized charges

An analytical 2-D model of double-gate metal–ferroelectric–insulator–semiconductor-negative-capacitance FET (MFIS-NCFET), using Green’s function approach, in the subthreshold region, is presented in this article. The explicit solution of coupled 2-D Landau–Devonshire and Poisson equations is analytically derived. Subsequently, an analytical and explicit model of subthreshold slope is developed from

The impact of a single displacement defect on the performance of tunneling field-effect transistors (TFETs) is studied. The OFF-state leakage current and subthreshold swing of the TFET are found to degrade by the single point defect. The degradation depends on the trap energy level; the impact due to a deep trap is greater than that due to a shallow trap. The degradation becomes more profound as the

Terahertz (THz) silicon-based electronics is undergoing rapid developments. In order to keep this momentum high, an accurate and optimized on-wafer characterization procedure needs to be developed. While evaluating passive elements, the measured s-parameter data can be verified by a direct use of EM simulation tools. However, this verification requires to precisely introduce part of the measurement

This article presents an accurate, reliability-aware statistical Berkeley short-channel IGFET Model 4 (BSIM4) compact model parameter generation methodology using the generalized lambda distribution (GLD) method. Using this methodology, compact model parameter sets can be generated “on the fly” beyond the limitation of the number of compact models extracted from the TCAD simulation. The generated unlimited

A normally OFF hydrogen-terminated diamond (H-terminated diamond) field-effect transistor (FET) has been successfully achieved with Ti/TiO x gate materials. A 5-nm Ti film was deposited on H-terminated diamond by electron beam evaporation technique and then it was thermally oxidized in air at 120 °C for 10 h to form Ti/TiO x , which was confirmed by X-ray photoelectron spectroscopy. The threshold voltage

We present the results of low-noise silicon junction field-effect transistors (JFET) with a split-channel concept. The device can be manufactured as a module in a standard CMOS process. The channel is split under the top gate of the JFET into a source-side main channel and a drain-side-extended drain channel. Devices with design gate length between 1.0 and 3.0 $\mu \text{m}$ and effective channel length

Drain-extended MOSFET (DEMOS) with halo implant induced laterally asymmetric channel doping shows anomalous characteristics across bias and temperature that cannot be captured by existing models. The transconductance ( ${g}_{m}$ ) maxima in the linear region is found to be not only a function of the peak mobility but also the halo doping density. In the saturation region, the ${g}_{m}$ characteristics

This article presents a comparative low-frequency noise (LFN) characterization of gate-all-around nanosheet n-channel Si metal–oxide–semiconductor field effect transistors, processed with three different metal gates (MGs): an aluminum-based reference process and two alternative effective work function (EWF) stacks. In all cases, the gate dielectric is composed of HfO 2 over an SiO 2 interfacial layer

In this article, the ${C}$ – ${V}$ curve shift, trap densities responsiveness, and dynamic ${R}_{ON}$ of AlGaN/GaN/GaN:C (SH:C) and AlGaN/GaN/graded-AlGaN:Si/GaN:C (DH:Si/C) heterostructure Schottky barrier diodes (SBDs) have been systematically analyzed. Due to additional 3-D electrons in graded-AlGaN:Si layer, the composite 2-D–3-D channel of DH:Si/C has a higher carrier concentration. Reducing the

We introduce a deep-recessed gate architecture in $\beta $ -Ga 2 O 3 delta-doped field-effect transistors (FETs) for improvement in dispersion and breakdown properties. The device design incorporates an unintentionally doped (UID) $\beta $ -Ga 2 O 3 layer as the passivation dielectric. To fabricate the device, the deep-recess geometry was developed using BCl 3 plasma-based etching at ~5 W reactive

We have theoretically shown thermophotovoltaic (TPV) energy conversion with Ga 0.84 In 0.16 As 0.14 Sb 0.86 /InAs 0.91 Sb 0.09 tandem cell, for which both subcells have the same lattice matched to GaSb substrate and can be experimentally fabricated in a high quality. Under the illumination of blackbody-like thermal spectra, the doping profiles of this device should be controlled as ${N}_{d{(}{a}{)}}

In this article, a metal/carbon-doped GaN (GaN:C)/Si-doped GaN (GaN:Si) structure was used to investigate the defect characteristics and carrier transport mechanisms in GaN:C layers with different carbon doping concentration. Capacitance-voltage, current–voltage, and deep-level transient spectroscopy measurements were performed at different temperatures. At forward bias, a pinning effect was found

Critical design parameters for AlGaN/GaN Schottky barrier diodes (SBDs) are analyzed in this work using TCAD computations and detailed experiments. A comprehensive TCAD-based computational modeling approach is developed for GaN-based SBD. Breakdown mechanisms in SBD for unintentionally doped (UID) buffer, Fe-doped buffer and C-doped buffer are studied. For the first time, we have reported impact of

This work presents the electrostatic analysis of a novel Ga 2 O 3 vertical Schottky diode with three different guard ring (GR) configurations to reduce the peak electric field at the metal edges. Highly doped p-type GaN, p-type nonpolar AlGaN, and polarization-doped graded p-AlGaN are simulated and analyzed as the GR material, which forms a heterojunction with the Ga 2 O 3 drift layer. GR with nonpolar

This article presents a study on the short-circuit (SC) instability of p-doped gate gallium nitride (p-GaN) high-electron-mobility transistors (HEMTs). Under SC condition, self-sustained oscillation occurs when a package stray inductance is introduced in a common source. The SC oscillation features some unique characteristics. With higher dc-bus voltage, the SC oscillation tends to be more unstable

p-Diamond field-effect transistors (FETs) featuring large effective mass, long momentum relaxation time, and high carrier mobility are a superb candidate for plasmonic terahertz (THz) applications. Previous studies have shown that p-diamond plasmonic THz FETs (TeraFETs) could operate in plasmonic resonant mode at a low-frequency window of 200 to ~600 GHz, thus showing promising potential for beyond

In this article, we analyze the characteristics of a recently conceived steep switching device 2-D Strain FET (2D-SFET) and present its circuit implications in the context of 6T-SRAM. We discuss the dependence of 2D-SFET characteristics on key design parameters, showing up to $2.7\times $ larger ON-current and 35% decrease in subthreshold swing when compared to 2D-FET. We analyze the performance of

Resistive random access memories (RRAMs) have attracted tremendous attention due to their miniaturized size, low power consumption, high response speed, and simple fabrication requirements, which are regarded as a promising candidate for future nonvolatile memories. However, the traditional binary storage RRAMs fail to meet the high-density requirement in the area of big data. One of the ways to overcome

This work experimentally investigates current conduction in 3-D NAND under up to 7 GPa of externally applied compressive mechanical stress. The impact of channel crystallinity and geometry is studied by comparing four types of Si channels: polycrystalline full channel, single-crystal full channel, polycrystalline macaroni channel, and single-crystal macaroni channel. In the studied channel types, the

Increasing computation demand of machine learning (ML) applications (recommender system, image classification, speech recognition, and so on) calls for the development of specialized hardware for ML and neuromorphic computing. New memories, such as resistive random access memory (RRAM), can be used to store weights of neural networks and to accelerate matrix multiplication, the dominant operation in

This study comprehensively investigates the impact of the time interval ( ${t}_{\text {wait}}$ ) between program/erase (P/E) cycles on the oxide quality of NAND Flash memory devices. It is observed that, at room temperature, P/E cycles with a shorter ${t}_{\text {wait}}$ yield a better oxide quality than those with a longer ${t}_{\text {wait}}$ . The oxide charge ( ${Q}_{T}$ ) evolution by distributed