In this article, we investigated the destructive behavior of the latest power diode when operating a hard-switching process. From the numerical simulation analysis, the destruction behavior originates in the enhanced impact ionization at the p-n junction on the anode side and current filament in the active region. A relaxing electric field on the anode side and a moderated electric field on the cathode

Quantum dots (QDs) have broad application prospects in displays such as full-color light-emitting diodes (LEDs) and micro-LEDs. However, an ultrahigh concentration of QDs is required to eliminate the pumping light for achieving high color purity, leading to significant reduction in the photoluminescence (PL) intensity of the QDs and the generation of much more heat. In this article, the PL intensity

The impact of electrical stress on the defect generation behaviors in thin GeO 2 /n-Ge gate stacks has been investigated through the measurement of the time-dependent dielectric breakdown (TDDB) and the stress-induced leakage current (SILC) characteristics. A multiple-spot breakdown (BD) event is confirmed, as well as a larger SILC generation probability compared with that in SiO 2 /Si structures.

The cold source field-effect transistor (CSFET), enabled by novel source engineering, is a promising alternative to achieve sub-60 mV/dec steep-slope switching. For the first time, we develop an industry-standard TCAD approach for the CSFET with an effective cold carrier density of states (DOS) model which captures the underlying physics of DOS engineering, cold carrier injection, and thermalization

In this article, the impact of self-heating effect (SHE) on nanosheet gate-all-around (GAA) transistor with a vertical combo spacer and different underlap/overlap channels is studied by the 3-D TCAD simulation. To achieve high authoritative evidences, the ${I}_{\text {d}}$ – ${V}_{\text {g}}$ characteristic with SHE is calibrated with the experimental data. First, the change of electrical characteristic

Due to the increasing importance and complexity of source/drain parasitic resistance (R sd ) in nanoscale CMOS technology and circuit design, a predictive 3-D structure-aware R sd compact model is developed and comprehensively validated in respect of 7-nm bulk FinFET TCAD platform. Our TCAD model was calibrated against GlobalFoundries/Samsung 7-nm FinFET technology experimental data and further validated

A CdTe/PbTe heterojunction (HJ) yields two-dimensional electron gas (2DEG) with a high electron density and mobility. Ultrahigh-speed and room-temperature operating mid-infrared photodetectors are developed with the 2DEG. The photoresponse of the detectors originates from the intrinsic response of PbTe by virtue of the conduction-band and valence-band alignment of the HJ. The extremely short rise and

Rectifier circuits featuring low threshold voltages and high cutoff frequencies based on p-channel organic thin-film transistors (TFTs) have been designed, fabricated and characterized. The TFTs and circuits were fabricated by shadow-mask lithography on flexible plastic substrates using the vacuum-deposited small-molecule organic semiconductor dinaphtho[2,3-b: $2^\prime $ , $3^\prime $ -f]thieno[3

We have observed and analyzed the ${1}/{f}^{{1}+\alpha }$ noise in transient leakage current through a metal–insulator–metal stacked high- ${k}$ capacitor of TiN–ZrO 2 –TiO 2 –TiN. The ZrO 2 and TiO 2 films, formed by atomic layer deposition, are polycrystalline and show geometrical variety at interfaces (i.e., grain boundaries). Two types of transient leakage current are observed: 1) the monotonically

This article presents the design, experimental results, and modeling of an inversion-mode CMOS varactor integrated in the STMicroelectronics 55-nm BiCMOS technology. The device was characterized from 1 to 325 GHz, demonstrating high-quality factor at millimeter-waves. For instance, a quality factor of 7 at around 190 GHz for a tuning ratio ( ${C}_{\text {max}}/{C}_{\text {min}}$ ) greater than 4 was

This article reports the fabrication of a dual-ion beam sputtering (DIBS)-grown MgZnO/CdZnO (MCO)-based gateless heterostructure field-effect transistor (HFET). In addition, this article presents that by introducing a 30-nm yttria spacer layer, the crystallinity of the CdZnO buffer layer can be enhanced and the interface roughness at the heterojunction of the MCO heterostructure can be reduced. Furthermore

This article reports on the experimental and analytical determination of the optimum carbon concentration in GaN to achieve enhanced breakdown in AlGaN/GaN high-electron mobility transistors (HEMTs). The lateral breakdown voltage increases when carbon doping is increased from $3\times 10^{{18}}$ to 10 19 cm −3 beyond which it decreases, whereas there is no substantial enhancement in the vertical breakdown

An irreversible model of the thermophotonic cell (TPC) with a heated forward-based light-emitting diode (LED) as an emitter and a photovoltaic cell (PVC) is established. The performances of the TPC are optimized and compared with those of the thermophotovoltaic cell (TPVC) based on finite-time thermodynamics. The results obtained show that there exist the optimally operating ranges of the voltages

In this article, a trench-field-plate (TFP) high-voltage power MOSFET is proposed. Instead of using a conventional n − drift region, the TFP power MOSFET features benzocyclobutene dielectric in the sidewall of deep trenches in the drift region and a sloped field plate (FP) inside each of the trenches. The TFP structure employed in the drift region modulates the electric field in the OFF-state, resulting

In this article, the effects of redundant electrode width on stability of inverted staggered via-contact structured amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs) under hot-carrier stress (HCS) were investigated. It is found that devices with a larger redundant electrode width have a severer degradation behavior after HCS. Capacitance–voltage measurements were conducted to

Vertical diamond Schottky diodes with blocking voltages ${V}_{\text {BD}} > {2.4}$ kV and ON-resistances ${R}_{\textsf {ON}} < {400}~\text{m}\Omega $ cm 2 were fabricated on homoepitaxially grown diamond layers with different surface morphologies. The morphology (smooth as-grown, hillock-rich, polished) influences the Schottky barrier, the carrier transport properties, and ultimately the device performance

The dV / dt in superjunction metal–oxide–semiconductor field-effect transistors (MOSFETs) during the turn-off transient has been shown to be higher than during the turn-on, which can be attributed to a shorter Miller plateau. In this article, we will show that these asymmetrical turn-on and turn-off characteristics are indirectly detected by the hysteresis of the dynamic gate-to-drain capacitance,

Capability of high-speed and low-cost manufacturing makes the printing techniques a very promising approach for large-area flexible electronics mass manufacturing. Due to fast and intensive technology development, the lack of knowledge about the reliability and lifetime of printed electronics is obvious, requiring further investigation. Especially, the effect of torsional bending on lifetime is a mostly

Although gate-oxide degradation occurs in both silicon (Si) and silicon carbide (SiC) MOSFETs, it requires a special attention in SiC MOSFETs. This is because the gate oxide in SiC MOSFETs is comparatively thinner than the gate oxide in Si MOSFETs, and thus, a higher electric field that appears across it could push the gate oxide to its reliability limit. While several electrical parameters have been

True random number generators (TRNGs) have received extensive research owing to their wide applications in information processing, transmission, and encryption. Recently, TRNGs have also been employed in emerging stochastic/probabilistic computing paradigms. TRNGs can be designed based on, for example, oscillator sampling, noise amplifying, and quantum physical effect with the aid of peripheral postprocessing

A device design technique for boosting output resistance ( ${R}_{\text {out}}$ ) characteristics of long-channel halo-doped nMOSFETs for replacement gate (RMG) high- ${k}$ /metal gate (HK/MG) devices is proposed based on numerical simulations. We show that the self-aligned halo-compensated channel implant (HCCI) that is carried out after dummy poly gate removal provides compensation for the conventional

Wereport on the fabrication and measurement of hydrogen-terminated diamond field-effect transistors (FETs) incorporating V 2 O 5 as a surface acceptor material to induce transfer doping. Comparing a range of gate lengths down to 50 nm, we observe inversely scaling peak output current and transconductance. Devices exhibited a peak drain current of ~700 mA/mm and a peak transconductance of ~150 mS/mm

Metal-oxide thin-film transistors (TFTs) promise to enable lightweight and low-power applications, such as ultrathin active matrix displays and low-cost RF identification tags. However, most reported high-performance metal-oxide TFTs contain high-cost indium and gallium elements, leading to constraints in cost-sensitive application. Herein, we present enhancement-/depletion-mode (E-/D-mode) TiO 2 TFTs

For the first time, the mobility enhancement mechanism due to the SiO 2 passivation layer (PVL) in amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) is studied using technology-computer-aided design (TCAD) simulation. Our results indicate that the introduction of oxygen vacancies in shallow donor states around the PVL/a-IGZO interface, which donate more free electrons in the induced accumulation

A physical-based analytical kink current model for polycrystalline -silicon (poly-Si) thin-film transistors (TFTs) has been proposed. Two important mechanisms for the kink current, namely carrier impact ionization and the parasitic bipolar junction transistor effect, are physically included in the model without introducing any artificial parameters. The proposed kink current model is fully compatible

In this article, a ring remote phosphor (RRP) structure comprising an inverted-cone-lens encapsulant and a surrounding phosphor layer was developed and used for laser-driven white lighting. The inverted-cone-lens encapsulant in the structure redirects light from a blue laser diode (LD) to the surrounding phosphor layer, thus preventing intense light from hitting the phosphor layer on a small surface

To figure out the effects of aluminum-doped ZnO (AZO) and Ag layers for the transparent electrode vertical (TEV) photoconductive semiconductor switch (PCSS) reported in our previous works, several different structures of high power, new vertical, extrinsic-triggered PCSS were designed and their performances are presented. All the PCSSs were fabricated on the vanadium compensated semi-insulating (VCSI)

This article presents new optical pixel sensors that are based on hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) for detecting secondary color optical signals to increase the number of colors of sensed light. Three types of series-connected structure with different photo TFTs enable the sensors to receive secondary color optical input signals that combine any two primary colors

An anomalous breakdown voltage (BV) walk-in phenomenon of the trench-gate p-type vertical double-diffused metal–oxide–semiconductor (VDMOS) after single avalanche stress has been experimentally investigated. It is found that the BV of the VDMOS is decreased after the single avalanche stress, while other electrical parameters remain unchanged. T-CAD simulations and emission microscope (EMMI) analysis

This article proposes a MATLAB-based optimization methodology of the drift region specific ON-resistance ( ${R}_{on,sp}$ ) both for the high-permittivity ( $\text{H}{k}$ ) MOSFETs and superjunction (SJ) MOSFETs with design parameters expressed by breakdown voltage (BV) and aspect ratio (AR). The optimized method has three distinctive features. First, based on the built-in functions in MATLAB, the proposed

Tilted ion implantation (TII) used in conjunction with preexisting masking features on the surface of a wafer is a relatively low-cost method for sublithographic patterning. Previous demonstrations of this method utilized a thin thermally grown layer of silicon oxide (SiO 2 ) as the implanted layer, with amorphous-silicon masking features, to form patterns with feature sizes as small as 9 nm. In this

A new and simple kind of all-carbon junction nanodevice, which is free of metal electrodes, is constructed by carbon chains seamlessly connected to two graphyne nanoribbons (GYNRs) electrodes. The electron transport properties of the constructed nanodevices are systematically investigated using self-consistent charge density-functional tight-binding combined with nonequilibrium Green’s function (NEGF)

Several miniaturized viscometers, or microviscometers, have been developed exploiting numerous rapid prototyping techniques. Among them, paper microstrips, famously known as microfluidic paper-based analytical devices ( $\mu $ PADs), have become popular due to their cost-efficacy, simple fabrication, fast response, and easily disposable. Many fabrication methods are existing to develop paper microstrips

2-D semiconductors show great promise to serve as channel materials in next-generation field-effect transistors (FETs). The permittivity of many 2-D semiconductors is anisotropic, though many recent simulation works studying 2-D FETs have treated these materials as though they have isotropic permittivities. Because there have been no works that investigate the role of each element of a semiconductor’s

A new class of metal–insulator tunneling transistor (MITT) devices is proposed and investigated. The planar dual-gate structure allows for complete gate field penetration of the transistor channel to modulate tunneling current across the channel. For a 5-nm channel length, with contact geometries that reflect the reality of fabricating at such a scale, we show that a 10% decrease in the effective electron

In this brief, we modeled the charge loss in the program verify level 1 (PV1) during the short-term retention operation. As a result, we confirmed that the charge loss in the lateral direction [lateral migration (LM)] was affected by the residual hole at the edge of the target word line (WL). Unlike the other PV levels, LM could be modeled separately in the PV1 by LM caused by electrons (LME) and LM

In this brief, several issues attributed to the channel-release process in vertically stacked-gate-all-around MOSFETs (GAAFETs) having various nanosheet (NS) widths were rigorously investigated. Because of the finite selectivity of SiGe (sacrificial layer) etchant to Si (channel layer), Si channel is likely to be thinned during the channel-release step which is one of the key processes in stacked-GAA

Deep-level traps in AlGaN/GaN- and AlInN/GaN-based HEMTs with different buffer doping technologies are identified by drain current transient spectroscopy (DCTS) and low-frequency (LF) output admittance ( ${Y}_{{22}}$ ) dispersion techniques. TCAD simulations are also carried out to determine the spatial location and type of traps. The DCTS and LF ${Y}_{{22}}$ measurements on Al 0.25 Ga 0.75 N/GaN HEMT

A series of electric field profile simulations in gallium nitride (GaN) p-i-n vertical diodes with negative bevel termination is carried out to optimize the bevel design. The bevel angles are varied from 90° to 0.1° with reasonably small increments to study the impact of the bevel angle on the electric field profile. The doping densities are also varied to study a more generalized trend; a new parameter

The human brain comprises about a hundred billion neurons connected through quadrillion synapses. Spiking neural networks (SNNs) take inspiration from the brain to model complex cognitive and learning tasks. Neuromorphic engineering implements SNNs in hardware, aspiring to mimic the brain at scale (i.e., 100 billion neurons) with biological area and energy efficiency. The design of ultra-energy-efficient

In this article, we propose an efficient and robust spike-driven convolutional neural network (SCNN) based on the NOR flash computing array (NFCA), which is mapped by the pretrained convolutional neural network with the same structure. The spike-driven system eliminates the additional analog-to-digital/digital-to-analog (AD/DA) conversion in the NFCA-based CNN. To study the performance of the hardware

Poststress dc characteristics of AlGaN/GaN HEMTs can be used to study the effect of high-power stress on the noise figure (NF) and gain of low-noise amplifiers (LNAs) subjected to large input overdrives. This enables a shift from circuit- to transistor-level measurements to investigate the impact of variations in HEMT design parameters on the robustness (including both recovery time and survivability)

A novel microdetector array (MDA) for monitoring electron beam (eBeam) and extreme ultraviolet (EUV) lithography processes in 5 nm and beyond FinFET technology is first-time presented. This on-wafer detector array consists of high-density sensing cells which are fully compatible with standard FinFET CMOS processes. Fin coupling structures and energy-sensing pads are first applied in an ultrasmall detector

Titanium-based contacts are envisioned for the integration of III–V device contacts on a 300-mm platform, such as photodetectors, semiconductor optical amplifiers (SOAs), and III–V silicon hybrid lasers. For the first time, the impact of the thermal budgets of process integration, back-end of line (BEOL), and long-term thermal stress on the electrical characteristics of the Ti/p-In 0.53 Ga 0.47 As

A conductivity type transformable junctionless transistor (T-JLT) is proposed. Two complementary doped, i.e., n- and p-type, polysilicon films thinner than 5 nm are arranged orthogonally with a dielectric in between, where each film plays a role as a source, a channel, a drain, and a gate, respectively. The role of the film is interchangeable by contact allocation. By swapping the contact assignment

In this article, an analytical model on the influence of the acceptor-type trap on the 2-dimensional electron gas (2DEG) density is proposed for GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs). Based on the charge-control method, a numerical analysis of the 2DEG in both the subthreshold and above-threshold regions is carried out with the deep-level and band-tail acceptor-type

In this article, we have developed an amorphous CuNiSnO (a-CNTO), which is a p-type amorphous oxide semiconductor (AOS). The a-CNTO thin films were deposited by the pulsed laser deposition method, having high amorphous quality with a rather smooth surface. The a-CNTO films grown at 100 °C exhibited the smoothest surface (root-mean-square roughness of 0.25 nm), highest visible transparency (~85%), and

In this article, we report the fabrication of Zr-rich high- ${k}$ ferroelectric hafnium zirconium oxide (HZO) capacitor with TiN as the top and bottom electrodes demonstrating an equivalent oxide thickness (EOT) of 5.7 Å and remanent polarization ( ${P}_{r}$ ) of $\sim 16~\mu \text{C}$ /cm 2 . High- ${k}$ value and low EOT was achieved by utilizing multiphase region of HZO as well as high pressure

A new room temperature (25 °C) ammonia gas sensor based on a metal-oxide-semiconductor (MOS) diode is reported. The device structure is synthesized by a sputtered tantalum pentoxide (Ta 2 O 5 ) dielectric, evaporated platinum nanoparticles (Pt NPs), and a Pt thin film on a GaN/AlGaN heterostructure. Pt NPs can effectively increase the specific surface area and related catalytic reactivity of Pt metal

The porous tungsten matrixes of barium tungsten cathodes are prepared by spark plasma sintering (SPS). By adjusting the raw powder particle diameter and the porosity, the matrixes with different average distances between the pores are obtained. The microstructure and the emission performance of the barium tungsten cathode are analyzed using scanning electron microscopy (SEM), electron emission measurement

We investigate the GaAs 0.51 Sb 0.49 /In 0.53 Ga 0.47 As negative-capacitance vertical-tunnel FET (NCVT-FET) to maximize its vertical tunneling over the corner tunneling. Negative capacitance enhances vertical tunneling more significantly than corner tunneling due to the amplified vertical electric field. By TCAD optimization of the device, small ${I}_{{\mathrm {OFF}}}$ (10 pA/ $\mu \text{m}$ ) and

The performances of FinFET, gate-all-around (GAA) nanowire/nanosheet, and U-shaped FETs (UFETs) are studied targeting the 3-nm node (N3) and beyond CMOS dimensions. To accommodate a contacted gate pitch (CGP) of 32 nm and below, the gate length is scaled down to 14 nm and beyond. While going from 5-nm node (N5) to 3-nm node (N3) dimensions, the GAA-lateral nanosheet (LNS) shows 8% reduction in the

Various self-powered devices employ energy-harvesting technology to capture and store an ambient energy. The photovoltaic (PV) cell is one of the most preferred approaches due to its potential for on-chip integration. Although serial connection of multiple PV cells is commonly required to obtain a sufficiently high voltage for circuit operation, a voltage boosting with serially stacked PV cells is

To focus on developing white light-emitting diodes (WLEDs) for lightings with high color rendering index (CRI), low correlated color temperature (CCT), and the displays with wide color gamut, inorganic perovskite quantum dots (QDs) such as CsPbX 3 (X = C1, Br, I) were the promising candidate owing to the excellent optoelectronic properties such as high quantum efficiency, narrow emission wavelengths

This article aims at proposing a compact analytical model for the low-frequency noise (LFN) of junctionless nanowire transistors (JNTs), operating at different bias conditions and temperatures. The model is validated through tridimensional numerical simulations, accounting for different trap configurations, as well as devices with different channel lengths, nanowire widths, and doping concentrations

The finite-difference time-domain (FDTD) algorithm and the particle-in-cell (PIC) method-based simulation are classic approaches to design and optimize the helix traveling wave tubes (TWTs). In this article, a multiple-graphics processing unit (GPU)-based 3-D-FDTD-PIC parallel program is developed to complete the full-wave simulation of a Ka -band helix TWT in the time domain. The specific parallel

The silicon bipolar impact ionization MOSFET offers potential for the realization of leaky integrated fire (LIF) silicon neuron due to the presence of parasitic bipolar junction transistor (BJT) in the floating body. In this article, we have proposed an L-shaped gate bipolar impact ionization MOS (L-BIMOS) with reduced breakdown voltage ( ${V}_{B} = {1.68}$ V) and demonstrated the functioning of LIF

The Landau field-effect transistors have been previously investigated to lower the power dissipation of integrated circuits by reducing the subthreshold swing (SS) below the Boltzmann limit of 60 mV/dec. The basic idea is to replace the classical gate insulator with dielectrics that exhibit a negative capacitance (NC) associated with the double-well energy landscape, for example, ferroelectrics (FE)

Presents the table of contents for this issue of the publication.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.