Presents the table of contents for this issue of the publication.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

We present and discuss explicit closed-form expressions for the saturation drain current of short-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) with gate oxide and interface-trapped charges, and including carrier velocity saturation, according to the generalized Enz–Krummenacher–Vittoz (EKV) MOSFET compact model. The normalized saturation drain current is derived as an explicit

FinFET architecture has witnessed great success at commercial 22-nm node and beyond due to its natural immunity of short-channel effects (SCEs) since the past decade. As the critical size scales down further, the parasitic capacitance becomes a crucial bottleneck to gain the device performance. In this article, analytical parasitic capacitance models (including eight components) are established based

We derive a complete set of expressions for the MOSFET gate and drain power spectral densities due to elastic and inelastic trapping/detrapping of channel carriers into the gate dielectric. Our calculations explain trapping/detrapping noise (TDN) in various FET operating regions and highlight trap’s position-dependent terms, often neglected in the literature, which are instead important for devices

This article presents a distributed analysis of 2-D plate capacitors with resistive top and bottom plates, which results in two coupled partial differential equations in two variables. The exact solutions for the input impedance of a rectangular capacitor are derived for several contacting scenarios. Using frequency power series analysis, we prove the resistance decoupling theorem: the effective (low

In this article, we report on the high dc and RF performance of AlGaN/GaN high electron mobility transistors that employ Ti/Au/Al/Ni/Au metallization stack with shallow trench etching ohmic contact (STEOC). An excellent ohmic contact performance including low contact resistance ( ${R}_{C}$ ) of $0.28~\Omega \cdot $ mm and smooth surface morphology have been achieved simultaneously. Atomic force microscope

We present a novel test structure for the study of sidewall ohmic contacts to III–V fins for FinFETs. We apply it to the characterization of the impact of digital etch (DE), used to trim the fin width, and thermal annealing on the contact resistivity of Mo/ $\text{n}^{+}$ -InGaAs fin sidewall contacts. To obtain sidewall contacts, we leave in place the etch mask that is used to define the fins in a

Dynamic ${R}_{\mathrm{\scriptscriptstyle {ON}}}$ dispersion due to buffer traps is a well-known issue of GaN power high electron mobility transistors (HEMTs), critically impacting their performance and stability. Several works show that the dynamic ${R}_{\mathrm{\scriptscriptstyle {ON}}}$ reaches a maximum for some OFF-state drain–source voltage ( ${V}_{\text{DS},{\mathrm{\scriptscriptstyle OFF}}}$

We present the physics and performance space of the tri-gate GaN junction high electron mobility transistor (Tri-JHEMT), a new tri-gate GaN device proposed recently. In Tri-JHEMTs, p-n junctions wrap around two-dimensional-electron-gas (2DEG) fins in the gate region. Our fabricated Tri-JHEMT demonstrates, for the first time, the kilovolt blocking capability at 150 °C in all tri-gate GaN high electron

In this work, we report a critical semi- ON-state drain stress voltage above which the gate current increases significantly and degrades permanently in AlGaN/GaN high electron mobility transistors (HEMTs). The observed critical voltage was found to be channel field-dependent by analyzing devices with different field plate lengths and passivation thicknesses, along with different gate–drain distances

Memristor is a promising device as a fundamental building block for future unconventional system architectures such as neuromorphic computing, reconfigurable logic, and multibit memories. Therefore, to facilitate circuit design using memristors, accurate and efficient models spanning a wide range of programming voltages and temperatures are required. In the first part of this series, we propose a behavioral

In the second part of this series, we propose a physics-based model for describing the temperature dependence of TiO x -based memristors, both switching and static. We show that the current–voltage ( ${I}$ – ${V}$ ) characteristics of memristor in the nonswitching regime, indicating a Schottky emission mechanism, can be described by minor modifications to the Schottky current equation. This leads to

One of the most attractive types of novel nonvolatile memory concepts is resistive random access memory (ReRAM) based on a reversible (“soft”) dielectric breakdown effect. The interest is caused by combining simple architecture with promising performance: excellent scalability, nanosecond speed, long data retention, and low power consumption. However, the commercialization of this type of memory is

In this article, for the first time, self-rectifying memristors are exploited for logic-in-memory computation. We report a Pt/TaO x /Ta memristor with salient self-rectifying bipolar features (10 4 ON-/ OFF-ratio, 10 5 rectification ratio, 10 5 nonlinearity, and ~1 pA leakage current), which could support a large passive crossbar array up to 160 Mb with the premise of 10% read margin. Moreover, we

A tristate-nanoelectromechanical-switch-based ternary content-addressable memory (NEMTCAM) is proposed for the first time. In the proposed unit NEMTCAM cell, a single nanoelectromechanical (NEM) memory switch replaces two static random access memory cells. Due to the monolithic 3-D (M3D) integration and nonvolatile property of NEM memory switches, the proposed NEMTCAM achieves an 86.3% smaller area

The integration of complete Boolean logic gate and memory in a single device is imperative to develop future computing systems beyond von Neumann architecture. Specifically, the giant magnetoimpedance (GMI) effect has drawn much attention for the high sensitive magnetic sensor applications; however, its possible application in logic-in-memory devices has been rarely explored. This work studies the

A 6T-SRAM bitcell with the footprint of only two transistors is demonstrated by stacking four n-type vertical gate-all-around transistors (VFET) on two pFinFETs. The local interconnects are all within the footprint of the two bottom pFinFETs. The bitcell area is $0.014~\mu \text{m}^{{2}}$ considering the experimentally achievable metal pitch of 52 nm and bottom pFinFETs of 5 nm node. It can be further

The implementation of current deep learning training algorithms is power-hungry, due to data transfer between memory and logic units. Oxide-based resistive random access memories (RRAMs) are outstanding candidates to implement in-memory computing, which is less power-intensive. Their weak RESET regime is particularly attractive for learning, as it allows tuning the resistance of the devices with remarkable

In this work, we present a four-transistor-two-resistor (4T2R) ternary content addressable memory (TCAM) bit cell based on the resistive memory (RRAM), comprising the conventional two-transistor-two-resistor (2T2R) cell with two additional comparison transistors. It can effectively amplify the match-line signal ratio (ML-ratio), lower the leakage current of the match cell ( ${I}_{{\mathrm {MATCH}}}$

New technologies are continuously investigated to overcome the physical limitations of the downscaling process of microelectronic industry in order to perpetuate the miniaturization of devices as well as to enhance their capabilities. Memories are important components of almost any modern system. Applications, such as portable devices for which magnetic storage is not viable, prompt the search for

Binary neural networks (BNNs) are promising for resource-constrained Internet of Things (IoT) devices owing to the lightweight memory and computation requirements. Moreover, BNNs based on computing-in-memory (CIM) architectures have attracted much attention in both algorithm and hardware designs. Recently, a variety of CIM-based BNN hardware designs has been proposed, particularly based on emerging

We measure the electrical performance and stability of indium tin zinc oxide (ITZO) thin-film transistors (TFTs), respectively, covered with a passivation layer (PVL) of aluminum oxide (Al 2 O 3 ) or scandium oxide (Sc 2 O 3 ) prepared by pulsed laser deposition (PLD). The devices with the Sc 2 O 3 PVL exhibit both satisfactory electrical performance and stability with a field effect mobility of 16

A novel compact realization of the XNOR/ XOR function is demonstrated with multimodal transistors (MMTs). The multimodal thin-film transistors (MMT’s) structure allows efficient use of layout area in an implementation optimized for unipolar thin-film transistor (TFT) technologies, which may serve as a multipurpose element for conventional and emerging large-area electronics. Microcrystalline silicon

Contact-controlled devices, such as source-gated transistors (SGTs), deliberately use energy barriers at the source, and naturally, the positive temperature dependence (PTD) of drain current can be utilized for temperature sensing. We exploit the difference in drain current activation energy, which arises with contact doping in polysilicon n-type contact-controlled transistors, to demonstrate output

This study presents a CMOS image sensor (CIS) with a two-step single-slope (TS-SS) analog-to-digital convertor (ADC), wherein the differential topology characteristics of a ramp generator are used. The proposed TS-SS ADC effectively resolves 1 most significant bit (MSB) with a half-ramping of a full analog-to-digital (A/D) reference at coarse conversion and the remaining least significant bits (LSBs)

An in-tool, on-wafer detectors’ array for monitoring deep ultraviolet (DUV) light is proposed and demonstrated in this work. The proposed electronic layer detectors array (ELDA) features FinFET CMOS compatibility and compact pixel structure. Its minimum pixel pitch can reach 0.7 $\mu \text{m}$ , enabling the realization of high spatial resolution array. Most importantly, the sensing results from DUV

In this work, we report on the fabrication and characterization of a miniature GaN chip with a size of $1.1\times 1.1\times0.21$ mm 3 for surface roughness measurement. Unlike conventional optical metrology that requires external components for the optical coupling between light source and detector, a monolithic GaN-on-sapphire chip fabricated through wafer-scale processes provides light emission and

In order to improve the photovoltaic performance of dye-sensitized solar cell (DSSC), graphitic carbon nitride (g-C 3 N 4 )/titanium dioxide (TiO 2 ) nanofibers (NFs) are added into the photoanode of DSSC as an additional layer. g-C 3 N 4 is prepared by high-temperature calcination. Through sol–gel method and electrospinning technology, we prepare g-C 3 N 4 /TiO 2 NFs. The material properties of g-C

We have theoretically investigated the effect of front electrode on the structure and performances of Ga x In $_{1-{x}}$ As y Sb $_{1-{y}}$ thermophotovoltaic (TPV) cells. By sampling a comb-like electrode, it is clearly demonstrated here that the optimum grid separation ${d}_{G}$ depending on the cell bandgap yields a quadratic function for a given spectrum illumination, while the desired coefficients

Perovskite-based devices are a promising candidate for the next generation of photovoltaic devices. Depending on the selective contacts layers and their interfaces with the absorber, the performance and photoelectric parameters of the perovskite solar cells (PSCs) can be changed. So, it is possible, to achieve highly efficient and stable PSCs by engineering the selective contacts layers and their interface

In this work, an analysis of the impact of drain field plate (FP) length on the semi- ON degradation of AlGaN/GaN high-electron-mobility transistors (HEMTs) is performed. A wafer-level characterization, by means of pulsed stress tests, reveals a faster and more severe decrease of the drain current in the linear region for the samples with longer drain FP. 2-D technology computer-aided design (TCAD)

This work demonstrates a trench isolated lateral double-implanted MOSFET (LDMOS) on Si-face in 4H-silicon carbide (SiC). A device $\vphantom {_{\int _{}}}$ where ${L}_{\textit {ch}} = 0.8\,\,\mu \text{m}$ and ${L}_{d} = 12\,\,\mu \text{m}$ shows an ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 22.9 $\text{m}\Omega $ cm 2 at a ${V}_{\text {GS}}$ of 20 V and a breakdown voltage (BV) of 1100 V

Threshold voltage ( ${V}_{\text {TH}}$ ) hysteresis affects the reliability of silicon carbide (SiC) MOSFETs. To evaluate the ${V}_{\text {TH}}$ hysteresis effect on switching characteristics, this article first investigates the ${V}_{\text {TH}}$ hysteresis in the static characteristics of three SiC MOSFETs with different gate structures. The results illustrate the density of the interface states

A novel high-performance 1700-V 4H-Silicon carbide (SiC) junction field-effect transistor (JFET) with reverse recovery capability and low switching loss is proposed in this article. As for the proposed 4H-SiC JFET, the gate region of the conventional 4H-SiC JFET is split into two segments, one of which is replaced by the source. A Schottky barrier diode (SBD) is integrated in the sidewall of the channel

Planar-gate 2.3 kV 4H-SiC power MOSFETs were successfully fabricated in a commercial foundry with the gate oxide thickness reduced from 55 to 27 nm for the first time. Results of numerical simulations demonstrate acceptable gate oxide electric field despite the increased blocking voltage. For a gate bias of 15 V, the measured specific ON-resistance ( ${R}_{\mathrm {ON},\text {sp}}$ ) and high-frequency

This article presents the 2-D numerical simulation results of the heavy-ion-induced leakage current degradation and single-event burnout (SEB) in the rated 1.2-kV silicon-carbide (SiC) super-junction (SJ) vertical diffusion metal-oxide-semiconductor (VDMOS). The employed simulation physics models were validated by the heavy-ion irradiation experiments of the commercially rated 1.2-kV SiC common VDMOS

In this article, the normally- OFF etching-free p-GaN stripe array gate AlGaN/GaN high-electron-mobility-transistors (PSAG-HEMTs) are designed and experimentally demonstrated through hydrogen plasma treatment. The unique threshold voltage ( ${V}_{TH}$ ) modulation technique based on the PSAG structure is proposed and simulated. Using this method, the ${V}_{TH}$ can be continuously shifted from −0.14

A new vertical double-diffused metal oxide semiconductor field effect transistor (MOSFET) is presented based on the high- ${k}$ (Hk) MOSFET concept in this article with the step high- ${k}$ insulator, named as step Hk vertical double-diffused metal oxide semiconductor (VDMOS), to improve the electric field modulation effect. For step Hk VDMOS, the depletion is increased by the electric field modulation

The design space of Ga 2 O 3 -based devices is severely constrained due to its low thermal conductivity and absence of viable p-type dopants. In this work, we discuss the limits of operation of a novel Ga 2 O 3 –Al 2 O 3 –diamond-based super-junction device concept, which can alleviate the constraints associated with Ga 2 O 3 -based devices. The improvements achieved using the proposed device concept

This article proposes an RC -IGBT structure with N-Si/n-Ge heterojunction (NNH-IGBT) to suppress snapback effect. Because the proposed N-Si/n-Ge heterojunction acts as a gradually reverse bias diode to suppress the electron flow into the N-short region, so the snapback effect can be suppressed. For the same ${\mathrm{\scriptstyle {ON}}}$ -state voltage drop ( ${V}_{\text {CE}}$ ), the turn-off loss

In this article, the hydrogen-terminated diamond metal-oxide-semiconductor field effect transistors (MOSFETs) which can operate at high frequency of 10 GHz are demonstrated. The devices were fabricated with a 50 nm Al 2 O 3 gate insulator and a 350 nm Si 3 N 4 passivation layer, which is compatible with the process of monolithic microwave-integrated circuits (MMICs). The device with gate length of

A silicon-on-insulator (SOI) lateral diffused metal-oxide semiconductor (LDMOS) with potential modulation plates (PMPs) and deep-oxide trenches (DOTs) is proposed and studied through TCAD simulations, which aims to enhance the electron mobility and improve the ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ). The proposed SOI LDMOS consists of a conduction cell and an auxiliary cell. The surface

With a goal of delay and power reduction in global buses, an air-gap technology for upper-layer interconnect is introduced. The fabrication process is discussed, utilizing ${h}$ -BN as an air-gap capping layer to enable large voids. The suitability of an air-gap technology for integration into the upper-layer back-end-of-line (BEOL) interconnect is evaluated in terms of the void ratio to the adjacent-line

MIS-type Al/Al 2 O 3 /p-Si structures were fabricated to identify its admittance analysis through capacitance/conductance versus logarithmic frequency ( ${C} / {G}$ – ${V}$ – ${f}$ ) data in the 1 kHz–5 MHz and ±3 V ranges at room temperature. Admittance measurements determine the surface states ( ${N}_{\text{ss}}$ ) and these states occurred at M/S interlayer arise as a result of high capacitance

The mobility degradation with channel length is examined from the viewpoint of electrostatic effects that alter not only the threshold voltage but also the transport properties. Even operated at low drain voltage, short MOSFETs are subject to a strong lateral electric field present over a significant portion of the channel. The lateral field, responsible for threshold voltage roll-off, causes a local

In this article, for the first time, we propose a silicene-based spin filter having a TFET configuration. The device portrays a voltage-dependent spin polarization and achieves a “spin polarization” as high as 98% at a minimal “operating voltage” (0.35 V). The operation of the device is based on the “spin-polarized edge states” in a silicene nanoribbon. The “spin polarization” of the output current

We propose a parallel negative-capacitance field-effect transistor (P-NCFET) structure, in which a ferroelectric operating in its negative-capacitance region is placed in parallel with the gate and source terminals of a MOSFET. The P-NCFET is stabilized by combining careful matching of the ferroelectric with the gate capacitance along with simple feedback realized using current mirrors. The novel stabilization

Ferroelectric field-effect transistors (Fe-FETs) with ferroelectric hafnium oxide (FE HfO 2 ) as the gate insulator are being extensively explored as a promising device candidate for non-volatile memory application. FE HfO 2 exhibits long retention over ten years, high endurance over 10 12 cycles, high speed with subnanosecond polarization switching, and high remnant polarization of 10– $30~\mu \text{C}$

In this article, tight binding model and nonequilibrium Green’s function technique have been used to investigate the electronic properties of armchair black phosphorene nanoribbons in ballistic transport regime as well as in the presence of line-edge roughness. The results indicate that although the ballistic electrical conductance is almost independent of ribbon width for the narrow ribbons and has

Conventionally, silver (Ag) electrodes for organic thin-film transistors (OTFTs) are prepared by evaporated method at high temperature. In this work, we report a new methodology to fabricate the Ag source/drain electrodes of flexible OTFTs arrays by chemically plated technique on polyimide substrate at room temperature. The indacenodithiophene-co-benzothiadiazole (IDT-BT) OTFTs with chemically plated

A miniature ionization vacuum sensor (IVS) based on an on-chip SiO x -based tunneling electron source is reported. The vacuum sensor fabricated by microfabrication technologies exhibits a compact multilayered structure with overall dimensions of $13\times 9\times2.7$ mm 3 , where the electron source chip, Si layer of the electron collector, Si layer of the ion collector, and glass spacers between them

This article presents a novel stepped suspended gate field-effect transistor (SSGFET) array-based ${z}$ -axis accelerometer with an enhanced detection range. The stepped gate electrode structure of SGFET aids in extending the stable driving range beyond 33.33% of the initial air gap. The stable driving range is extended to 50% of the initial air gap with ~90% increase in the pull-in voltage. Mechanical

This study proposed a nonenzymatic sensor for lactic acid detection based on copper doped zinc oxide (CZO) modified by graphitic carbon nitride (g-C 3 N 4 ) and iron–platinum nanoparticles (FePt NPs). The silver paste electrodes of the sensor were prepared using screen printing technology, and the CZO sensing film was deposited using radio frequency (R.F.) sputtering system. The g-C 3 N 4 nanosheet

In this work, we, for the first time, propose a quartz crystal microbalance (QCM) humidity sensor that is prepared by a one-step method based on pencil drawing. The scanning electron microscopy (SEM), atomic force microscope (AFM), and Raman spectra confirm some graphite flakes, and a layer of sensing film is formed, demonstrating the successful preparation of the QCM sensor. A series of experiments

In this article, we report a wafer-level packaged Pirani vacuum gauge using the proprietary InvenSense CMOS MEMS technology. The micro Pirani vacuum gauge features three serpentine-shaped molybdenum thermistors on the suspended silicon-on-insulator (SOI) bridges, while the wiring gap of each serpentine-shaped silicon microbridge is 1.6 ${ {\mu }}\text{m}$ . For the vacuum range of $5\times 10^{-{4}}$

AlGaN/GaN Schottky barrier diode (SBD) temperature sensor with low turn-on voltage was fabricated by employing the recessed anode structure. This AlGaN/GaN SBD demonstrates good rectification in a broad temperature scope from 298 to 473 K. Compared with common planar diode, the recessed anode SBD shows a relatively lower turn-on voltage and better Schottky contact characteristics. The temperature-dependent

This report demonstrates the fabrication and performance of a novel, transient, stable breath sensor based on black phosphorus quantum dots (BPQDs) and polyvinyl alcohol (PVA) composite. BPQDs were utilized as the conduction medium, while the PVA provides a flexible substrate that disintegrates in water. The device presents an innovative solution to black phosphorous (BP) degradation in which the copper

2H MoS 2 nanoflakes were exfoliated and surface-modified by amine (-NH 2 ) groups in a simple three-step water-based approach. The NH 2 -modified MoS 2 sheets were used as humidity sensitive layer for estimating various levels of relative humidity (RH) (10%–90%). The devices demonstrated a maximum response of 720% for 90% RH with ${t}_{{\text {response}}} =1.2$ s and ${t}_{{\text {recovery}}} =3.1$

Based on the phenomenon that the incident terahertz (THz) radiation can increase the discharge current and luminescent intensity of a glow discharge detector (GDD), the electrical and optical modes were used to detect the THz wave. The influence of GDD’s discharge current, orientation, size, phosphor coating, and polarization sensitivity were investigated in detail. The results show that the electron