当前期刊: ACM Transactions on Reconfigurable Technology and Systems Go to current issue    加入关注   
显示样式:        排序: IF: - GO 导出
我的关注
我的收藏
您暂时未登录!
登录
  • Processing Grid-format Real-world Graphs on DRAM-based FPGA Accelerators with Application-specific Caching Mechanisms
    ACM Trans. Reconfig. Technol. Syst. (IF 1.125) Pub Date : 2020-06-03
    Zhiyuan Shao; Chenhao Liu; Ruoshi Li; Xiaofei Liao; Hai Jin

    Graph processing is one of the important research topics in the big-data era. To build a general framework for graph processing by using a DRAM-based FPGA board with deep memory hierarchy, one of the reasonable methods is to partition a given big graph into multiple small subgraphs, represent the graph with a two-dimensional grid, and then process the subgraphs one after another to divide and conquer

    更新日期:2020-06-30
  • FPGA Logic Block Architectures for Efficient Deep Learning Inference
    ACM Trans. Reconfig. Technol. Syst. (IF 1.125) Pub Date : 2020-06-03
    Mohamed Eldafrawy; Andrew Boutros; Sadegh Yazdanshenas; Vaughn Betz

    Reducing the precision of deep neural network (DNN) inference accelerators can yield large efficiency gains with little or no accuracy degradation compared to half or single precision floating-point by enabling more multiplication operations per unit area. A wide range of precisions fall on the pareto-optimal curve of hardware efficiency vs. accuracy with no single precision dominating, making the

    更新日期:2020-06-30
  • Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling
    ACM Trans. Reconfig. Technol. Syst. (IF 1.125) Pub Date : 2020-06-23
    Jiandong Mu; Wei Zhang; Hao Liang; Sharad Sinha

    Recent success in applying convolutional neural networks (CNNs) to object detection and classification has sparked great interest in accelerating CNNs using hardware-like field-programmable gate arrays (FPGAs). However, finding an efficient FPGA design for a given CNN model and FPGA board is not trivial since a strong background in hardware design and detailed knowledge of the target board are required

    更新日期:2020-06-30
  • VTR 8
    ACM Trans. Reconfig. Technol. Syst. (IF 1.125) Pub Date : 2020-05-31
    Kevin E. Murray; Oleg Petelin; Sheng Zhong; Jia Min Wang; Mohamed Eldafrawy; Jean-Philippe Legault; Eugene Sha; Aaron G. Graham; Jean Wu; Matthew J. P. Walker; Hanqing Zeng; Panagiotis Patros; Jason Luu; Kenneth B. Kent; Vaughn Betz

    Developing Field-programmable Gate Array (FPGA) architectures is challenging due to the competing requirements of various application domains and changing manufacturing process technology. This is compounded by the difficulty of fairly evaluating FPGA architectural choices, which requires sophisticated high-quality Computer Aided Design (CAD) tools to target each potential architecture. This article

    更新日期:2020-05-31
  • Model-based Design of Hardware SC Polar Decoders for FPGAs
    ACM Trans. Reconfig. Technol. Syst. (IF 1.125) Pub Date : 2020-05-30
    Yann Delomier; Bertrand Le Gal; Jerémie Crenne; Christophe Jego

    Polar codes are a new error correction code family that should be benchmarked and evaluated in comparison to LDPC and turbo-codes. Indeed, recent advances in the 5G digital communication standard recommended the use of polar codes in EMBB control channels. However, in many cases, the implementation of efficient FEC hardware decoders is challenging. Specialised knowledge is required to enable and facilitate

    更新日期:2020-05-30
  • Reconfigurable Framework for Environmentally Adaptive Resilience in Hybrid Space Systems
    ACM Trans. Reconfig. Technol. Syst. (IF 1.125) Pub Date : 2020-05-05
    Sebastian Sabogal; Alan Dale George; Christopher Mark Wilson

    Due to ongoing innovations in both sensor technology and spacecraft autonomy, on-board space processing continues to be outpaced by the escalating computational demands required for next-generation missions. Commercial-off-the-shelf, hybrid system-on-chips (SoCs), combining fixed-logic CPUs with reconfigurable-logic FPGAs, present numerous architectural advantages that address on-board computing challenges

    更新日期:2020-05-05
  • Substream-Centric Maximum Matchings on FPGA
    ACM Trans. Reconfig. Technol. Syst. (IF 1.125) Pub Date : 2020-04-24
    Maciej Besta; Marc Fischer; Tal Ben-Nun; Dimitri Stanojevic; Johannes De Fine Licht; Torsten Hoefler

    Developing high-performance and energy-efficient algorithms for maximum matchings is becoming increasingly important in social network analysis, computational sciences, scheduling, and others. In this work, we propose the first maximum matching algorithm designed for FPGAs; it is energy-efficient and has provable guarantees on accuracy, performance, and storage utilization. To achieve this, we forego

    更新日期:2020-04-24
  • HopliteBuf
    ACM Trans. Reconfig. Technol. Syst. (IF 1.125) Pub Date : 2020-02-13
    Tushar Garg; Saud Wasly; Rodolfo Pellizzoni; Nachiket Kapre

    HopliteBuf is a deflection-free, low-cost, and high-speed FPGA overlay Network-on-chip (NoC) with stall-free buffers. It is an FPGA-friendly 2D unidirectional torus topology built on top of HopliteRT overlay NoC. The stall-free buffers in HopliteBuf are supported by static analysis tools based on network calculus that help determine worst-case FIFO occupancy bounds for a prescribed workload. We implement

    更新日期:2020-02-13
  • Kernel Normalised Least Mean Squares with Delayed Model Adaptation
    ACM Trans. Reconfig. Technol. Syst. (IF 1.125) Pub Date : 2020-02-13
    Nicholas J. Fraser; Philip H. W. Leong

    Kernel adaptive filters (KAFs) are non-linear filters which can adapt temporally and have the additional benefit of being computationally efficient through use of the “kernel trick”. In a number of real-world applications, such as channel equalisation, the non-linear mapping provides significant improvements over conventional linear techniques such as the least mean squares (LMS) and recursive least

    更新日期:2020-02-13
  • Molecular Dynamics Simulations on High-Performance Reconfigurable Computing Systems.
    ACM Trans. Reconfig. Technol. Syst. (IF 1.125) Pub Date : 2010-11-01
    Matt Chiu,Martin C Herbordt

    The acceleration of molecular dynamics (MD) simulations using high-performance reconfigurable computing (HPRC) has been much studied. Given the intense competition from multicore and GPUs, there is now a question whether MD on HPRC can be competitive. We concentrate here on the MD kernel computation: determining the short-range force between particle pairs. In one part of the study, we systematically

    更新日期:2019-11-01
  • Mercury BLASTP: Accelerating Protein Sequence Alignment.
    ACM Trans. Reconfig. Technol. Syst. (IF 1.125) Pub Date : 2009-06-06
    Arpith Jacob,Joseph Lancaster,Jeremy Buhler,Brandon Harris,Roger D Chamberlain

    Large-scale protein sequence comparison is an important but compute-intensive task in molecular biology. BLASTP is the most popular tool for comparative analysis of protein sequences. In recent years, an exponential increase in the size of protein sequence databases has required either exponentially more running time or a cluster of machines to keep pace. To address this problem, we have designed and

    更新日期:2019-11-01
Contents have been reproduced by permission of the publishers.
导出
全部期刊列表>>
材料学研究精选
Springer Nature Live 产业与创新线上学术论坛
胸腔和胸部成像专题
自然科研论文编辑服务
ACS ES&T Engineering
ACS ES&T Water
屿渡论文,编辑服务
杨超勇
周一歌
华东师范大学
南京工业大学
清华大学
中科大
唐勇
跟Nature、Science文章学绘图
隐藏1h前已浏览文章
中洪博元
课题组网站
新版X-MOL期刊搜索和高级搜索功能介绍
ACS材料视界
x-mol收录
福州大学
南京大学
王杰
左智伟
湖南大学
清华大学
吴杰
赵延川
中山大学化学工程与技术学院
试剂库存
天合科研
down
wechat
bug