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Profiling with trust: system monitoring from trusted execution environments Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2024-02-16 Christian Eichler, Jonas Röckl, Benedikt Jung, Ralph Schlenk, Tilo Müller, Timo Hönig
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Novel adaptive quantization methodology for 8-bit floating-point DNN training Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2024-02-16 Mohammad Hassani Sadi, Chirag Sudarshan, Norbert Wehn
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Transparent integration of autonomous vehicles simulation tools with a data-centric middleware Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2024-01-06 José Luis Conradi Hoffmann, Leonardo Passig Horstmann, Antônio Augusto Fröhlich
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On the impact of hardware-related events on the execution of real-time programs Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2023-12-31
Abstract Estimating safe upper bounds on execution times of programs is required in the design of predictable real-time systems. When multi-core, instruction pipeline, branch prediction, or cache memory are in place, due to the considerable complexity traditional static timing analysis faces, measurement-based timing analysis (MBTA) is a more tractable option. MBTA estimates upper bounds on execution
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Multiprovision: a Design Space Exploration tool for multi-tenant resource provisioning in CPU–GPU environments Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2023-12-21 Michael G. Jordan, Julio Costella Vicenzi, Tiago Knorst, Guilherme Korol, Antonio Carlos Schneider Beck, Mateus Beck Rutzig
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Monitoring the performance of multicore embedded systems without disrupting its timing requirements Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2023-12-16 Leonardo Passig Horstmann, José Luis Conradi Hoffmann, Antônio Augusto Fröhlich
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On vulnerabilities in EVT-based timing analysis: an experimental investigation on a multi-core architecture Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2023-10-17 Jamile Vasconcelos, George Lima, Marwan Wehaiba El Khazen, Adriana Gogonel, Liliana Cucu-Grosjean
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Hardware-accelerated service-oriented communication for AUTOSAR platforms Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2023-06-13 Abdelrahman Elbahnihy, M. Watheq El-Kharashi, Mona Safar
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Efficient placement and migration policies for an STT-RAM based hybrid L1 cache for intermittently powered systems Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2023-05-05 SatyaJaswanth Badri, Mukesh Saini, Neeraj Goel
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Accelerated and optimized covariance descriptor for pedestrian detection in self-driving cars Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2023-04-28 Nesrine Abid, Ahmed. C. Ammari, Ahmed Al Maashri, Mohamed Abid, Medhat Awadalla
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A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2023-04-26 Rama Muni Reddy Yanamala, Muralidhar Pullakandam
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Predictable timing behavior of gracefully degrading automotive systems Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2023-04-11 Philipp Weiss, Sebastian Steinhorst
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Low-cost modular devices for on-road vehicle detection and characterisation Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2023-04-07 Jose-Luis Poza-Lujan, Pedro Uribe-Chavert, Juan-Luis Posadas-Yagüe
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Scheduling and energy savings for small scale embedded FreeRTOS-based real-time systems Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2023-03-15 Gessé Oliveira, George Lima
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Using evolutionary metaheuristics to solve the mapping and routing problem in networks on chip Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2023-03-10 Hiago Mayk Gomes de Araujo Rocha, Antonio Carlos Schneider Beck, Marcio Eduardo Kreutz, Sílvia Maria Diniz Monteiro Maia, Monica Magalhães Pereira
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Supporting single and multi-core resource access protocols on object-oriented RTOSes Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2023-03-01 Lucas Matheus dos Santos, Giovani Gracioli, Tomasz Kloda, Marco Caccamo
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Design and evaluation of an energy efficient DiamondMesh topology for on-chip interconnection networks Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2023-01-02 Lakshmi Kiranmai Varanasi, B. K. N Srinivasarao
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Emulation and verification framework for MPSoC based on NoC and RISC-V Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2022-09-14 Mostafa Khamis, Sameh El-Ashry, Mohamed AbdElsalam, M. Watheq El-Kharashi, Ahmed Shalaby
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Optimization based on the minimum maximal k-partial-matching problem of finite states machines with input multiplexing Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2022-06-02 Ignacio Garcia-Vargas, Raouf Senhadji-Navarro
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Selective register-file cache: an energy saving technique for embedded processor architecture Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2022-05-29 Sumanth Gudaparthi, Rahul Shrestha
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Auto implementation of parallel hardware architecture for Aho-Corasick algorithm Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2022-01-23 M. Najam-ul-Islam, Fatima Tu Zahra, Atif Raza Jafri, Roman Shah, Masood ul Hassan, Muhammad Rashid
Pattern matching using Aho-Corasick (AC) algorithm is the most time-consuming task in an Intrusion Detection System, and therefore, the Field Programmable Gate Array (FPGA) based solutions are frequently employed. In this context, the two possibilities are memory based solutions and hardwired solution. The limitation of memory based solutions is the inefficient utilization of slices while the hardwired
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An energy efficient multi-target binary translator for instruction and data level parallelism exploitation Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2022-01-14 Tiago Knorst, Julio Vicenzi, Michael G. Jordan, Jonathan H. de Almeida, Guilherme Korol, Antonio C. S. Beck, Mateus B. Rutzig
Embedded devices are omnipresent in our daily routine, from smartphones to home appliances, that run data and control-oriented applications. To maximize the energy-performance tradeoff, data and instruction-level parallelism are exploited by using superscalar and specific accelerators. However, as such devices have severe time-to-market, binary compatibility should be maintained to avoid recurrent
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New paradigm of FPGA-based computational intelligence from surveying the implementation of DNN accelerators Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2022-01-12 Yang You, Yinghui Chang, Weikang Wu, Bingrui Guo, Hongyin Luo, Xiaojie Liu, Bijing Liu, Kairong Zhao, Shan He, Lin Li, Donghui Guo
With the rapid development of Artificial Intelligence, Internet of Things, 5G, and other technologies, a number of emerging intelligent applications represented by image recognition, voice recognition, autonomous driving, and intelligent manufacturing have appeared. These applications require efficient and intelligent processing systems for massive data calculations, so it is urgent to apply better
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A hardware/software partitioning method based on graph convolution network Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2021-10-30 Xin Zheng, Shouzhi Liang, Xiaoming Xiong
Hardware/software (HW/SW) partitioning is the crucial step in HW/SW co-design, which can significantly reduce the time-to-market and improves the performance of an embedded system. Due to that the majority of previous works have large exploration time and generate often low-quality solutions for large scale systems, we propose a fast HW/SW partitioning approach based on graph convolution network (GCN)
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Candidate architectures for emerging IoV: a survey and comparative study Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2021-08-12 Hichri, Yamina, Dahi, Soumaya, Fathallah, Habib
Intelligent Transportation System (ITS) is observing significant evolution in terms of technology and investment worldwide. This has given birth to the new concept of Internet of vehicles (IoV) as one of the leading applications of the Internet of Things. IoV aims to offer a better sharing of information and communication between vehicles, enabling higher cooperation for common interests. IoV is increasingly
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Simplified introduction of power intent into a register-transfer level model Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2021-08-15 Matej Groma, Dominik Macko
In highly-integrated electronic circuits designs, power reduction must be properly addressed. The standardized ways of power-intent specification are unbearable in modern complex designs, since they extensively prolong the time-to-market of products. In this article, we propose a simplified method of designing energy-efficient systems at the register-transfer level, which is fully compatible with the
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Adaptive run-time scheduling of dependent services for service-oriented IoT systems Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2021-07-07 Jangryul Kim, Kangkyu Park, Hoeseok Yang, Soonhoi Ha
IoT systems can be regarded as distributed systems that are composed of heterogeneous smart devices with different performances and functionalities. Many IoT applications with various resources and real-time requirements will run concurrently in an IoT system. In addition, non-functional properties such as power consumption and device lifetime are considered important. Since the IoT services can be
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SRCP: sharing and reuse-aware replacement policy for the partitioned cache in multicore systems Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2021-06-12 Soma Niloy Ghosh, Lava Bhargava, Vineet Sahula
Although multi-core processors enhance the performance yet the challenge of estimating Worst-Case Execution Time (WCET) of a task remains in such systems due to interference in shared resources like Last Level Caches (LLC). Cache partitioning has been used to reduce the interference problem by isolating the shared cache among each thread to ease the WCET estimation. However, it prevents information
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An embedded FPGA-SoC framework and its usage in moving object tracking application Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2021-06-11 Jai Gopal Pandey
Moving object tracking is a computation-intensive operation that requires accelerating hardware solution. In this work, a high-performance design for mean shift based moving object tracking algorithm and its FPGA implementation is done. Here, associated circuits are utilized as intellectual-property cores to implement an embedded system-on-a-chip (SoC) framework for real-time moving object tracking
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Special issue with selected papers from 2019 Brazilian Symposium on Computer Engineering (SBESC 2019) Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2021-05-29 Ivan Muller,Marcelo Götz
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CAD synthesis tools for floating-gate SoC FPAAs Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2021-03-22 Sihwan Kim, Sahil Shah, Richard Wunderlich, Jennifer Hasler
We present a tool framework to compile and program mixed-signal circuits and systems on Floating-Gate (FG) based mixed-signal System-on-Chips (SoC) consisting of a digital processor and Field Programmable Analog Array (FPAA) fabric. We have modified the configuration of Verilog-to-Routing (VTR) to cover analog circuits and developed a tool called vpr2swcs to create the list of FG switches, that is
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Simulation is essential for embedded control systems with task jitter Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2021-03-22 Long Tran, P J Radcliffe, Liuping Wang
Sampling or task jitter affects the performance of digital control systems but realistic simulation of this effect has not been possible to date. Our previous work has developed a novel method to simulate sampling jitter in MATLAB/Simulink simulation software where the jitter is generated randomly. What has been missing is a way to capture sampling jitter from a target platform and then feed this timing
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Revisiting the battery level indicator of mobile devices Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2021-02-18 Seunghyeok Jeon, Daeyong Kim, Junick Ahn, Rhan Ha, Hojung Cha
Mobile device users tend to extend the device’s usage time by checking the battery level frequently via the battery level indicator (BLI) and adjusting their device usage patterns. This behavior is based on the assumption that the BLI is accurate. In this paper, we define four requirements that a user would expect for the BLI and define BLI anomalies that violate these requirements. We found various
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No-instruction-set-computer design experience of flexible and efficient architectures for digital communication applications: two case studies on MIMO turbo detection and universal turbo demapping Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2021-01-27 Mostafa Rizk, Amer Baghdadi, Michel Jezequel, Yasser Mohanna, Youssef Atat
The emerging flexibility need in designing application-specific processors dedicated for modules of digital receiver imposes a new design metric, which is added to the requirements of efficiency and productivity. In order to cope with the emerging flexibility requirement combined with the best performance efficiency, many application-specific processor design approaches have been proposed and investigated
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A model of architecture for estimating GPU processing performance and power Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2021-01-16 Saman Payvar, Maxime Pelcat, Timo D. Hämäläinen
Efficient usage of heterogeneous computing architectures requires distribution of the workload on available processing elements. Traditionally, the mapping is based on information acquired from application profiling and utilized in architecture exploration. To reduce the amount of manual work required, statistical application modeling and architecture modeling can be combined with exploration heuristics
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Dynamic concurrency throttling on NUMA systems and data migration impacts Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2020-11-04 Janaina Schwarzrock, Michael Guilherme Jordan, Guilherme Korol, Charles C. de Oliveira, Arthur F. Lorenzon, Mateus Beck Rutzig, Antonio Carlos S. Beck
Many parallel applications do not scale as the number of threads increases, which means that using the maximum number of threads will not always deliver the best outcome in performance or energy consumption. Therefore, many works have already proposed strategies for tuning the number of threads to optimize for performance or energy. Since parallel applications may have more than one parallel region
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Synthetic image generation for training deep learning-based automated license plate recognition systems on the Brazilian Mercosur standard Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2020-10-07 Gilles Silvano, Vinícius Ribeiro, Vitor Greati, Aguinaldo Bezerra, Ivanovitch Silva, Patricia Takako Endo, Theo Lynn
License plates are the primary source of vehicle identification data used in a wide range of applications including law enforcement, electronic tolling, and access control amongst others. License plate detection (LPD) is a critical process in automatic license plate recognition (ALPR) that reduces complexity by delimiting the search space for subsequent ALPR stages. It is complicated by unfavourable
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An analysis of the Gateway Integrity Checking Protocol from the perspective of Intrusion Detection Systems Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2020-09-07 Mateus Martínez de Lucena, Roberto Milton Scheffel, Antônio Augusto Fröhlich
Internet of Things (IoT) gateways bridging resource-constrained devices and the internet, running conventional operating systems and communication protocols, are valuable targets for malicious attackers. Once compromised, the gateway can no longer be trusted to deliver data accurately to the applications running on the Cloud. In this work we present an analysis of the Gateway Integrity Checking Protocol
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Special issue on deep learning for on-chip learning Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2020-08-13 Wei Wei,Jinsong Wu,Chunsheng Zhu
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Hot sparing for lifetime-chip-performance and cost improvement in application specific SIMT processors Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2020-06-03 S. Hasan Mozafari, Brett H. Meyer
Redundancy is a well-known technique for replacing components with manufacturing defects, improving yield and reducing cost. Previously, most yield improvement strategies utilized redundant components only when another component had failed (i.e., cold spares). However, utilizing hot spares is becoming popular in commercial products (e.g., the NVIDIA Ti GPU series). Hot spares address manufacturing
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Deep learning controller design of embedded control system for maglev train via deep belief network algorithm Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2020-04-09 Ding-gang Gao, You-gang Sun, Shi-hui Luo, Guo-bin Lin, Lai-sheng Tong
The maglev train has been successful in practice as a new type of ground transportation. Owing to the inherent nonlinearity and open-loop instability of the electromagnetic suspension (EMS) system, an analogue or a digital controller is used to control the maglev trains’ stability. With the rapid development of embedded systems and artificial intelligence, intelligent digital control has begun to replace
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Reducing neighbor discovery time in sensor networks with directional antennas using dynamic contention resolution Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2020-03-21 Nicolás Gammarano, Javier Schandy, Leonardo Steinfeld
In this paper we present, simulate, and evaluate Dynamic Asynchronous Neighbor Discovery protocol for Directional Antennas (DANDi), a neighbor discovery protocol for Wireless Sensor Networks (WSN) with directional antennas that guarantees that every reliable communication link in a network is discovered. DANDi is asynchronous, fully directional (supports both directional transmissions and receptions)
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Deep learning parallel computing and evaluation for embedded system clustering architecture processor Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2020-03-07 Yue Zu
In the era of intelligence, the processing of a large amount of information and various intelligent applications need to rely on embedded devices. This trend has made machine learning algorithms play an increasingly important role. High-performance embedded computing is an effective means to solve the lack of computing power of embedded devices. Aiming at the problem that the calculation amount of
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Nested genetic algorithm for highly reliable and efficient embedded system design Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2020-03-06 Adeel Israr, Mohammad Kaleem, Sajid Nazir, Hamid Turab Mirza, Sorin Alexander Huss
Modern embedded systems must have high reliability and performance. They should be able to tolerate both hard as well as soft errors occurring in the resources constituting the system. Reliability must be part of the system design and the system must consist of non expensive off-the-shelf resources. A system-level design process of reliable system demands efficient reliability evaluation of the explored
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Experimental evaluation and comparison of latency-optimized opticaland conventional multi-FPGA systems Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2020-02-06 Asmeen Kashif, Mohammad A. S. Khalid
Rising data rates and input/output density in integrated circuits are challenging the traditional off-chip copper interconnect solutions, demanding a compatible high-speed serial interface capable of maintaining multi-gigabits data rates. Designers typically choose copper interconnect for chip-to-chip connections in a Multi-FPGA System (MFS). However, copper based interconnects are incapable of scaling
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Special issue with selected papers from 2018 Brazilian Symposium on Computer Engineering (SBESC 2018) Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2020-01-08 Marcelo Götz,Francisco Vasques
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An energy-efficient time-triggered scheduling algorithm for mixed-criticality systems Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2019-12-05 Lalatendu Behera, Purandar Bhaduri
Real-time safety-critical systems are getting more complicated due to the introduction of mixed-criticality systems. The increasing use of mixed-criticality systems has motivated the real-time systems research community to investigate various non-functional aspects of these systems. Energy consumption minimization is one such aspect which is just beginning to be explored. In this paper, we propose
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Code generation for distributed embedded systems with VDM-RT Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2019-11-19 Miran Hasanagić, Tommaso Fabbri, Peter Gorm Larsen, Victor Bandur, Peter Tran-Jørgensen, Julien Ouy
Developing embedded systems that are distributed is a challenging endeavour, since they need to ensure system-wide properties as well as existence of a large number of possible candidate system architectures. Various model based techniques advocate raising the abstraction level in order to support a holistic view of such a distributed embedded system. Furthermore, automatically generating implementation
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An embedded automatic license plate recognition system using deep learning Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2019-11-13 Diogo M. F. Izidio, Antonyus P. A. Ferreira, Heitor R. Medeiros, Edna N. da S. Barros
A system to automatically recognize vehicle license plates is a growing need to improve safety and traffic control, specifically in major urban centers. However, the license plate recognition task is generally computationally intensive, where the entire input image frame is scanned, the found plates are segmented, and character recognition is then performed for each segmented character. This paper
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Data clustering for efficient approximate computing Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2019-11-09 Michael G. Jordan, Marcelo Brandalero, Guilherme M. Malfatti, Geraldo F. Oliveira, Arthur F. Lorenzon, Bruno C. da Silva, Luigi Carro, Mateus B. Rutzig, Antonio Carlos S. Beck
Given the saturation of single-threaded performance improvements in General-Purpose Processor, novel architectural techniques are required to meet emerging demands. In this paper, we propose a generic acceleration framework for approximate algorithms that replaces function execution by table look-up accesses in dedicated memories. A strategy based on the K-Means Clustering algorithm is used to learn
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A model-driven framework for design and verification of embedded systems through SystemVerilog Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2019-11-08 Muhammad Waseem Anwar, Muhammad Rashid, Farooque Azam, Muhammad Kashif, Wasi Haider Butt
The demands of system complexity and design productivity for embedded systems can be managed by simplifying and reusing the design. Furthermore, these systems should be verified as early as possible in the development process to reduce the cost and effort. The rationale of the proposed framework in this article is to simplify the design and verification process of embedded systems in the context of
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On embedding a hardware description language in Isabelle/HOL Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2019-11-05 Wilayat Khan, David Sanan, Zhe Hou, Liu Yang
In order to define executable hardware description language while at the same time be fit for formal proofs of properties, a hardware description language VeriFormal, embedded in Isabelle/HOL, was created. VeriFormal, together with a translator and Isabelle/HOL proof facility, provides a platform for designing, simulating and reasoning about hardware designs. Building such an environment is challenging
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Implementation of high precision/low latency FP divider using Urdhva–Tiryakbhyam multiplier for SoC applications Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2019-11-05 C. R. S. Hanuman, J. Kamala, A. R. Aruna
The increasing demand of Industrial and Scientific data intensive applications are higher precision arithmetic with reduced computation time. In this paper, we designed a high-precision, fully pipelined 32-bit floating-point (FP) divider using Newton–Raphson (NR) algorithm realized with Urdhva–Tiryakbhyam (UT) multiplier for System on Chip applications. The divider design is based on Newton–Raphson
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A simultaneous multithreading processor architecture with predictable timing behavior Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2019-09-10 Hadley Magno Siqueira, Marcio Eduardo Kreutz
Real-time embedded systems need software and hardware to be time-predictable to guarantee the correct behavior of the system. Precision Timed Machines are architectures designed for timing predictability and repeatability. They help to improve design time and the efficiency of real-time embedded systems by allowing to separately verify the timing properties of modules. This paper presents a Simultaneous
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Memphis: a framework for heterogeneous many-core SoCs generation and validation Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2019-08-20 Marcelo Ruaro, Luciano L. Caimi, Vinicius Fochi, Fernando G. Moraes
This work presents Memphis, which comprises a flexible EDA framework and a many-core model for heterogeneous SoCs. The framework, together with the many-core model supports the integration of processors, network interfaces, routers, and peripherals. A set of tools enable a decoupled generation and compilation of the hardware, operating systems, and applications. The hardware model is cycle-accurate
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Optimization of multitask parallel mobile edge computing strategy based on deep learning architecture Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2019-07-12 Zongkai Liu, Xiaoqiang Yang, Jinxing Shen
As a mainstream computing and storage strategy for mobile communications, Internet of Things and large data applications, mobile edge computing strategy mainly benefits from the deployment and allocation of small base stations. Mobile edge computing mainly helps users to complete complex, intensive and sensitive computing tasks. However, the algorithm has many problems in practical application, such
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Control-schedule co-design for fast stabilization in real time systems facing repeated reconfigurations Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2019-06-14 Jaishree Mayank, Arijit Mondal, Arnab Sarkar
Efficient scheduling of tasks in cyber-physical systems or internet-of-things is a challenging prospect primarily due to their demands to meet critical performance goals in the face of stringent resource constraints. In addition, to enhance ease of implementation and more efficient usage of resources, these schedulers are many-a-times restricted to be non-preemptive, where jobs once started must be
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A survey on partitioning models, solution algorithms and algorithm parallelization for hardware/software co-design Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2019-04-30 Neng Hou, Xiaohu Yan, Fazhi He
In electronic design automation, hardware/software co-design significantly reduces the time-to-market and improves the performance of embedded systems. With the increasing scale of applications and complexity of hardware architecture of embedded systems, hardware/software co-design is still a research hotspot. As hardware/software co-design is a wide topic, this paper focuses on major developments
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Special issue with selected papers from 2017 Brazilian Symposium on Computer Engineering (SBESC 2017) Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2019-04-22 José Augusto Miranda Nacif,Marcio Seiji Oyamada
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Trace-driven and processing time extensions for Noxim simulator Des. Autom. Embed. Syst. (IF 1.4) Pub Date : 2019-01-05 Ivan Luiz Pedroso Pires, Marco Antonio Zanata Alves, Luiz Carlos Pessoa Albini
Simulation is one of the main tools used to analyze and test new proposals in the Network-on-Chip field. Several simulators can be found in the literature, among them the Noxim simulator stands out. It is being used by many researchers due to the wireless support and open-source availability. An important issue at the simulation phase is the choice of workload, as it may affect testing the system and