We present a tool framework to compile and program mixed-signal circuits and systems on Floating-Gate (FG) based mixed-signal System-on-Chips (SoC) consisting of a digital processor and Field Programmable Analog Array (FPAA) fabric. We have modified the configuration of Verilog-to-Routing (VTR) to cover analog circuits and developed a tool called vpr2swcs to create the list of FG switches, that is

Sampling or task jitter affects the performance of digital control systems but realistic simulation of this effect has not been possible to date. Our previous work has developed a novel method to simulate sampling jitter in MATLAB/Simulink simulation software where the jitter is generated randomly. What has been missing is a way to capture sampling jitter from a target platform and then feed this timing

Mobile device users tend to extend the device’s usage time by checking the battery level frequently via the battery level indicator (BLI) and adjusting their device usage patterns. This behavior is based on the assumption that the BLI is accurate. In this paper, we define four requirements that a user would expect for the BLI and define BLI anomalies that violate these requirements. We found various

The emerging flexibility need in designing application-specific processors dedicated for modules of digital receiver imposes a new design metric, which is added to the requirements of efficiency and productivity. In order to cope with the emerging flexibility requirement combined with the best performance efficiency, many application-specific processor design approaches have been proposed and investigated

Efficient usage of heterogeneous computing architectures requires distribution of the workload on available processing elements. Traditionally, the mapping is based on information acquired from application profiling and utilized in architecture exploration. To reduce the amount of manual work required, statistical application modeling and architecture modeling can be combined with exploration heuristics

Many parallel applications do not scale as the number of threads increases, which means that using the maximum number of threads will not always deliver the best outcome in performance or energy consumption. Therefore, many works have already proposed strategies for tuning the number of threads to optimize for performance or energy. Since parallel applications may have more than one parallel region

License plates are the primary source of vehicle identification data used in a wide range of applications including law enforcement, electronic tolling, and access control amongst others. License plate detection (LPD) is a critical process in automatic license plate recognition (ALPR) that reduces complexity by delimiting the search space for subsequent ALPR stages. It is complicated by unfavourable

Internet of Things (IoT) gateways bridging resource-constrained devices and the internet, running conventional operating systems and communication protocols, are valuable targets for malicious attackers. Once compromised, the gateway can no longer be trusted to deliver data accurately to the applications running on the Cloud. In this work we present an analysis of the Gateway Integrity Checking Protocol

Redundancy is a well-known technique for replacing components with manufacturing defects, improving yield and reducing cost. Previously, most yield improvement strategies utilized redundant components only when another component had failed (i.e., cold spares). However, utilizing hot spares is becoming popular in commercial products (e.g., the NVIDIA Ti GPU series). Hot spares address manufacturing

The maglev train has been successful in practice as a new type of ground transportation. Owing to the inherent nonlinearity and open-loop instability of the electromagnetic suspension (EMS) system, an analogue or a digital controller is used to control the maglev trains’ stability. With the rapid development of embedded systems and artificial intelligence, intelligent digital control has begun to replace

In this paper we present, simulate, and evaluate Dynamic Asynchronous Neighbor Discovery protocol for Directional Antennas (DANDi), a neighbor discovery protocol for Wireless Sensor Networks (WSN) with directional antennas that guarantees that every reliable communication link in a network is discovered. DANDi is asynchronous, fully directional (supports both directional transmissions and receptions)

In the era of intelligence, the processing of a large amount of information and various intelligent applications need to rely on embedded devices. This trend has made machine learning algorithms play an increasingly important role. High-performance embedded computing is an effective means to solve the lack of computing power of embedded devices. Aiming at the problem that the calculation amount of

Modern embedded systems must have high reliability and performance. They should be able to tolerate both hard as well as soft errors occurring in the resources constituting the system. Reliability must be part of the system design and the system must consist of non expensive off-the-shelf resources. A system-level design process of reliable system demands efficient reliability evaluation of the explored

Rising data rates and input/output density in integrated circuits are challenging the traditional off-chip copper interconnect solutions, demanding a compatible high-speed serial interface capable of maintaining multi-gigabits data rates. Designers typically choose copper interconnect for chip-to-chip connections in a Multi-FPGA System (MFS). However, copper based interconnects are incapable of scaling

Real-time safety-critical systems are getting more complicated due to the introduction of mixed-criticality systems. The increasing use of mixed-criticality systems has motivated the real-time systems research community to investigate various non-functional aspects of these systems. Energy consumption minimization is one such aspect which is just beginning to be explored. In this paper, we propose

Developing embedded systems that are distributed is a challenging endeavour, since they need to ensure system-wide properties as well as existence of a large number of possible candidate system architectures. Various model based techniques advocate raising the abstraction level in order to support a holistic view of such a distributed embedded system. Furthermore, automatically generating implementation

A system to automatically recognize vehicle license plates is a growing need to improve safety and traffic control, specifically in major urban centers. However, the license plate recognition task is generally computationally intensive, where the entire input image frame is scanned, the found plates are segmented, and character recognition is then performed for each segmented character. This paper

Given the saturation of single-threaded performance improvements in General-Purpose Processor, novel architectural techniques are required to meet emerging demands. In this paper, we propose a generic acceleration framework for approximate algorithms that replaces function execution by table look-up accesses in dedicated memories. A strategy based on the K-Means Clustering algorithm is used to learn

The demands of system complexity and design productivity for embedded systems can be managed by simplifying and reusing the design. Furthermore, these systems should be verified as early as possible in the development process to reduce the cost and effort. The rationale of the proposed framework in this article is to simplify the design and verification process of embedded systems in the context of

In order to define executable hardware description language while at the same time be fit for formal proofs of properties, a hardware description language VeriFormal, embedded in Isabelle/HOL, was created. VeriFormal, together with a translator and Isabelle/HOL proof facility, provides a platform for designing, simulating and reasoning about hardware designs. Building such an environment is challenging

The increasing demand of Industrial and Scientific data intensive applications are higher precision arithmetic with reduced computation time. In this paper, we designed a high-precision, fully pipelined 32-bit floating-point (FP) divider using Newton–Raphson (NR) algorithm realized with Urdhva–Tiryakbhyam (UT) multiplier for System on Chip applications. The divider design is based on Newton–Raphson

Real-time embedded systems need software and hardware to be time-predictable to guarantee the correct behavior of the system. Precision Timed Machines are architectures designed for timing predictability and repeatability. They help to improve design time and the efficiency of real-time embedded systems by allowing to separately verify the timing properties of modules. This paper presents a Simultaneous

This work presents Memphis, which comprises a flexible EDA framework and a many-core model for heterogeneous SoCs. The framework, together with the many-core model supports the integration of processors, network interfaces, routers, and peripherals. A set of tools enable a decoupled generation and compilation of the hardware, operating systems, and applications. The hardware model is cycle-accurate

As a mainstream computing and storage strategy for mobile communications, Internet of Things and large data applications, mobile edge computing strategy mainly benefits from the deployment and allocation of small base stations. Mobile edge computing mainly helps users to complete complex, intensive and sensitive computing tasks. However, the algorithm has many problems in practical application, such

Efficient scheduling of tasks in cyber-physical systems or internet-of-things is a challenging prospect primarily due to their demands to meet critical performance goals in the face of stringent resource constraints. In addition, to enhance ease of implementation and more efficient usage of resources, these schedulers are many-a-times restricted to be non-preemptive, where jobs once started must be

In electronic design automation, hardware/software co-design significantly reduces the time-to-market and improves the performance of embedded systems. With the increasing scale of applications and complexity of hardware architecture of embedded systems, hardware/software co-design is still a research hotspot. As hardware/software co-design is a wide topic, this paper focuses on major developments

Simulation is one of the main tools used to analyze and test new proposals in the Network-on-Chip field. Several simulators can be found in the literature, among them the Noxim simulator stands out. It is being used by many researchers due to the wireless support and open-source availability. An important issue at the simulation phase is the choice of workload, as it may affect testing the system and

Many ground-level and space systems require reliability testing before their deployment, since they are increasingly susceptible to transient and permanent faults. Such process must be accurate, controllable, generic, cheap, and fast. Even though fault injection at gate-level is often the most appropriate solution when one seeks for accuracy and controllability, it is very time-consuming. Considering

Industrial environments are typically characterised by high levels of interference. Therefore, standards for industrial wireless sensor networks (WirelessHART, ISA 100.11a, and IEEE 802.15.4e) have defined a time division and multichannel-based mode of operation, in which pairs of time slots and channels are assigned to links representing communication between nodes. In IEEE 802.15.4e this mode of

Droplet-based microfluidic biochips (or DMFBs) are rapidly becoming a revolutionizing lab-on-a-chip technology. Numerous application specific protocols bridging the cross-disciplinary fields necessitate DMFBs as their prime need. The main goal at the fluid level is to minimize bioassay schedule length. Also, for a safe assay outcome, contamination among droplet routes must be avoided. Size restriction

The emergence of many-core processors raises novel demands to system design. Power-limitations and abundant parallelism require for efficient and scalable run-time management. The integration of dedicated hardware to enhance the performance of the run-time management system is gaining an increasing importance. But the design of a run-time manager for many-core generally suffers from exhaustive evaluation

Efficient mapping of tasks onto heterogeneous multi-core systems is very challenging especially in the context of real-time applications. Assigning tasks to cores is an NP-hard problem and solving it requires the use of meta-heuristics. Relevantly, genetic algorithms have already proven to be one of the most powerful and widely used stochastic tools to solve this problem. Conventional genetic algorithms

Mixed-criticality systems are promoted in industry due to their potential to reduce size, weight, power, and cost. Nonetheless, deploying mixed-criticality applications on commercial multi-core platforms remains a highly challenging problem. To name a few reasons: (i) Industrial mixed-criticality applications are usually complex reactive applications, which cannot be specified by traditional, e.g.

Most vehicles are now produced with infotainment features. However, as reported in various security conferences, security vulnerabilities associated with an infotainment system can cause serious security issues, e.g., an attacker can control in-vehicle systems through the infotainment system. To address such security issues, in this paper, we propose a session key establishment protocol using Elliptic

Based on measurement of export technological complexity and input servitization level in the manufacturing industry of China from 2006 to 2015, the effects of onshore and offshore input servitization on export technological complexity of manufacturing industry were discussed based on the panel data model by combining industrial heterogeneity. Results demonstrated that offshore input servitization has

In this paper we propose a novel deep spatial transformer convolutional neural network (Spatial Net) framework for the detection of salient and abnormal areas in images. The proposed method is general and has three main parts: (1) context information in the image is captured by using convolutional neural networks (CNN) to automatically learn high-level features; (2) to better adapt the CNN model to

Prototyping using multi-FPGA systems offers significant advantages over simulation and emulation based pre-silicon verification techniques. Multi-FPGA prototyping follows a complex design flow where the quality of associated tools and the architecture of interconnect topology play a very important role in the performance of final prototyped design. A well designed interconnect topology may remain underutilized

The wireless network should provide high throughput and positive status and this paper suggest a system that supports real-time communications with excellence of service necessities for application based on wireless communications. In addition a hybrid network that interconnects both mobile networks and wireless networks. By inheriting the features of Solid Rocket Booster technology for mobile and

In the world of embedded architectures, energy consumption and the reliable performance are the two important parameters where the limelight of the research is required. When embedded architectures are used as the Internet of Things, these two parameters plays the very important role in the better performance. Several algorithms have been designed for the energy consumption in the embedded architectures

The healthcare domain is basically “data rich”, yet tragically not every one of the information are dug which is required for finding concealed examples and successful basic leadership used to find learning in database and for restorative research, especially in heart malady forecast. This article has examined forecast frameworks for heart disease utilizing more number of info attributes. In this article

For any organization, the selection of suppliers is a very important step to increase productivity and profitability. Any organization or company seeks to use the best methodology and the appropriate technology to achieve its strategies and objectives. The present study employs the neutrosophic set for decision making and evaluation method (DEMATEL) to analyze and determine the factors influencing

Modern mobile heterogeneous platforms have GPUs integrated with multicore processors to enable execution of high-end graphics-intensive games. However, these gaming applications consume significant power due to heavy utilization of CPU–GPU resources, which drains battery resources that are critical for mobile devices. While dynamic voltage and frequency scaling (DVFS) techniques have been exploited

Image segmentation in MR images gives valuable information and plays a vital part in identifying the different kinds of tumor. Various learning techniques have been utilized for tumor detection by comparing extracted feature points of the image under study and reference image. However, it is a challenging task to build a reliable data for brain tumor detection by training due to large variations of

Computer aided detection assists radiologists by providing second opinion in the mammography detection, and reduce misdiagnosis. An expert system with novel subclass based learning multiple neural network classifier (SBLMNN) has been proposed to solve the mammogram mass classification problem. This work explores the significance of the modular learning in artificial neural networks, inspired from the

Hydrops Fetalis is an abnormal condition in the fetus by an accretion of unusual fluid or edema in two or more fetal cavities for instance ascites, pericardial and pleural effusion. Accumulation of atypical fluid above 2 mm needs extra attention of radiologists. Ultrasound imaging technique helps to diagnose the fluid accumulation within the pericardial tissues. The trained medicinal practitioners

The objective of this research is the assessment of circuit design compression strategy carrying a greater number of similar output chains. The proposed method decreases the testing time while keeping lesser area overhead. The decompression technique depends upon constant LFSR diffusion which is utilized as a part of such a route, to the point that it empowers LFSR lockout getting away inside the least

Internet of Things (IoT) is a reality right now and IoT applications has being applied for many different scenarios. Every IoT scenario has stringent requirements and each new developed application must be tested before being embedded on real devices. There are two main approaches for testing IoT applications, real testbeds and network simulators. Real testbeds are the most accurate test environments

The objective of the paper is to represent the real-time framework in multiprocessor environment task scheduling process by examining the novel algorithm advanced PSO. The advanced PSO algorithm has the metaphor as the basis to facilitate social interaction, which makes a search on space by making adjustments to the trajectories of individual vectors, referred to “particles” as they are considered

This paper addresses the problem of mapping tasks onto an FPGA-based many-core platform where the cores typically have a limited amount of memory and thus should be frequently overlaid with a small program block that implements a task. In this regard, we propose a framework that takes integer linear programming (ILP) to find an optimal mapping of an application onto such a many-core platform at the

Nowadays, internet of things (IoT) became a leading beginning process of technology in advances of information and communication. The technology of it provides the system welfare and convenes in the water quality of the present monitoring. In order to watch the level of water quality various techniques were implemented in the areas of water in various localities like monitoring of drinking water quality

This paper presents a new methodology to incorporate testability to Technology driven high-level synthesis, which is a customized high level synthesis approach based on the target technology. This new methodology called testable technology driven high-level synthesis, generates testable hardware from the corresponding HDL input. Testability incorporation at this higher abstraction, using this integrated

Advanced Encryption Standard was published as Federal Information Processing Standard by National Institute of Standards and Technology in 2001. AES is a symmetric non fiestel block cipher cryptographic algorithm that encrypts and decrypts the data block of 128 bits using different key sizes (128, 192, 256). Based on the block sizes, the number of rounds of encryption and decryption operations and

VLSI circuits are perceived to dissipate extra power during testing when compared with that of the normal function. Drastic heat may reduce circuit consistency, shoot up package cost, and even cause permanent damage to the circuit under test. Thus minimization of test power has gained increased significance. This paper explores the avenues in power minimization during test application in CMOS VLSI

Designing critical embedded systems, like UAVs is not a trivial task because it brings the challenge of dealing with the uncertainty that is inherent to this type of systems, e.g., winds, GPS uncertainty, etc. Simulation and verification tools that provide a level of confidence can help design such systems and increase the safety of specified cyber-physical systems before deployment. This paper presents

A novel input transition aware dynamic voltage scaling based low power 8 bit Multiplier–Accumulator (MAC) architecture for Digital Signal Processing (DSP) has been presented in this paper. MAC is one of the main modules used in the various DSP applications like filtering, convolution and so on. The proposed input data transition aware dynamic voltage scaling is very effective method to minimize the

The increase of interdependent components in avionic and automotive software rises new challenges for real-time system integration. For instance, most scheduling and mapping techniques proposed in the literature rely on the availability of the system’s DAG representation. However, at the initial stage of system design, a dataflow graph (DFG) is generally used to represent the dependence between software

Look-up tables (LUT) form the basic logic elements in a large class of modern day field programmable gate arrays (FPGA). With FPGAs increasingly being used in low and medium volume productions, many vendors have improved the capacity and versatility of these devices. The enormous logic capacity inherent in state-of-art FPGAs has made it essential to develop automated computer aided design (CAD) support

Model Based System Engineering (MBSE) is a renowned approach in the context of embedded systems development. It is frequently used to deal with the structural and behavioral aspects of system design. However, the verification of system design is generally performed in isolation. It is particularly true in the context of assertion based verification. Consequently, there is a huge gap between system

With the increase in the complexity of safety-critical embedded applications, the reliability analysis of such systems have also become increasingly difficult. For such complex system specifications, if the reliability provisions are declared upfront in the design flow then the overall system level reliability can be easily inferred given that the system components satisfy their individual reliability

Dynamic Circuit Specialization (DCS) is used to optimize parts of an application and switch between the specialized parts utilizing Partial Reconfiguration at the run-time. The time needed to reconfigure the FPGA is a limiting factor for DCS. The reconfiguration controller, such as Xilinx Hardware Internal Configuration Access Port (HWICAP), enables an embedded processor to read or write the configuration