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A High-Performance Accelerator for Real-Time Super-Resolution on Edge FPGAs ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-03-16 Hongduo Liu, Yijian Qian, Youqiang Liang, Bin Zhang, Zhaohan Liu, Tao He, Wenqian Zhao, Jiangbo Lu, Bei Yu
In the digital era, the prevalence of low-quality images contrasts with the widespread use of high-definition displays, primarily due to low-resolution cameras and compression technologies. Image super-resolution (SR) techniques, particularly those leveraging deep learning, aim to enhance these images for high-definition presentation. However, real-time execution of deep neural network (DNN)-based
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Detecting Adversarial Examples Utilizing Pixel Value Diversity ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-03-14 Jinxin Dong, Pingqiang Zhou
In this article, we introduce two novel methods to detect adversarial examples utilizing pixel value diversity. First, we propose the concept of pixel value diversity (which reflects the spread of pixel values in an image) and two independent metrics (UPVR and RPVR) to assess the pixel value diversity separately. Then we propose two methods to detect adversarial examples based on the threshold method
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An Efficient FPGA Architecture with Turn-Restricted Switch Boxes ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-03-14 Fatemeh Serajeh Hassani, Mohammad Sadrosadati, Nezam Rohbani, Sebastian Pointner, Robert Wille, Hamid Sarbazi-Azad
Abstract. Field-Programmable Gate Arrays (FPGAs) employ a large number of SRAM cells to provide a flexible routing architecture which have a significant impact on the FPGA’s area and power consumption. This flexible routing allows for a rather easy realization of the desired functionality, but our evaluations show that the full routing flexibility is not required in many occasions. In this work, we
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EPHA: An Energy-efficient Parallel Hybrid Architecture for ANNs and SNNs ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-03-14 Yunping Zhao, Sheng Ma, Hengzhu Liu, Libo Huang
Artificial neural networks (ANNs) and spiking neural networks (SNNs) are two general approaches to achieve artificial intelligence (AI). The former have been widely used in academia and industry fields; the latter, SNNs, are more similar to biological neural networks and can realize ultra-low power consumption, thus have received widespread research attention. However, due to their fundamental differences
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D3PBO: Dynamic Domain Decomposition-based Parallel Bayesian Optimization for Large-scale Analog Circuit Sizing ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-03-14 Aidong Zhao, Tianchen Gu, Zhaori Bi, Fan Yang, Changhao Yan, Xuan Zeng, Zixiao Lin, Wenchuang Hu, Dian Zhou
Bayesian optimization (BO) is an efficient global optimization method for expensive black-box functions, but the expansion for high-dimensional problems and large sample budgets still remains a severe challenge. In order to extend BO for large-scale analog circuit synthesis, a novel computationally efficient parallel BO method, D3PBO, is proposed for high-dimensional problems in this work. We introduce
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Reduced On-chip Storage of Seeds for Built-in Test Generation ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-03-14 Irith Pomeranz
Logic built-in self-test (LBIST) approaches use an on-chip logic block for test generation and thus enable in-field testing. Recent reports of silent data corruption underline the importance of in-field testing. In a class of storage-based LBIST approaches, compressed tests are stored on-chip and decompressed by an on-chip decompression logic. The on-chip storage requirements may become a bottleneck
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Comparative Analysis of Dynamic Power Consumption of Parallel Prefix Adder ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-03-11 Ireneusz Brzozowski
The Newcomb-Benford law is the law, also known as Benford's law, of anomalous numbers stating that in many real-life numerical datasets, including physical and statistical ones, numbers have small initial digit. Numbers irregularity observed in nature leads to the question, is the arithmetical-logical unit, responsible for performing calculations in computers optimal? Are there other architectures
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Security Evaluation of State Space Obfuscation of Hardware IP through a Red Team – Blue Team Practice ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-03-05 Md Moshiur Rahman, Jim Geist, Daniel Xing, Yuntao Liu, Ankur Srivastava, Travis Meade, Yier Jin, Swarup Bhunia
Due to the inclination towards a fab-less model of integrated circuit (IC) manufacturing, several untrusted entities get white-box access to the proprietary intellectual property (IP) blocks from diverse vendors. To this end, the untrusted entities pose security-breach threats in the form of piracy, cloning, and reverse engineering, sometimes threatening national security. Hardware obfuscation is a
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2D Search Space for Extracting Broadside Tests from Functional Test Sequences ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-03-02 Irith Pomeranz
Testing for delay faults after chip manufacturing is critical to correct chip operation. Tests for delay faults are applied using scan chains that provide access to internal memory elements. As a result, a circuit may operate under non-functional operation conditions during test application. This may lead to overtesting. The extraction of broadside tests from functional test sequences ensures that
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Root-Cause Analysis with Semi-Supervised Co-Training for Integrated Systems ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-03-01 Renjian Pan, Xin Li, Krishnendu Chakrabarty
Root-cause analysis for integrated systems has become increasingly challenging due to their growing complexity. To tackle these challenges, machine learning (ML) has been applied to enhance root-cause analysis. Nonetheless, ML-based root-cause analysis usually requires abundant training data with root causes labeled by human experts, which are difficult or even impossible to obtain. To overcome this
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FortiFix: A Fault Attack Aware Compiler Framework for Crypto Implementations ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-03-01 Keerthi K, Chester Rebeiro
Fault attacks are one of the most powerful forms of cryptanalytic attack on embedded systems, that can corrupt cipher’s operations leading to a breach of confidentiality and integrity. A single precisely injected fault during the execution of a cipher can be exploited to retrieve the secret key in a few milliseconds. Naïve countermeasures introduced into implementation can lead to huge overheads, making
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H3D-Transformer: A Heterogeneous 3D (H3D) Computing Platform for Transformer Model Acceleration on Edge Devices ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-02-28 Yandong Luo, Shimeng Yu
Prior hardware accelerator designs primarily focused on single-chip solutions for 10MB-class computer vision models. The GB-class transformer models for natural language processing (NLP) impose challenges on existing accelerator design due to the massive number of parameters and the diverse matrix multiplication (MatMul) workloads involved. This work proposes a heterogeneous 3D-based accelerator design
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Mixed Integer Programming based Placement Refinement by RSMT Model with Movable Pins ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-02-15 Ke Tang, Lang Feng, Zhongfeng Wang
Placement is a critical step in the physical design for digital application specific integrated circuits (ASICs), as it can directly affect the design qualities such as wirelength and timing. For many domain specific designs, the demands for high performance parallel computing result in repetitive hardware instances, such as the processing elements in the neural network accelerators. As these instances
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Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-02-15 Deepanjali S., Noor Mahammad SK
Controllers are mission-critical components of any electronic design. By sending control signals, they decide which and when other data path elements must operate. Faults, especially Single Event Upset (SEU) occurrence in these components, can lead to functional/mission failure of the system when deployed in harsh environments. Hence, competence to self-heal from SEU is highly required in the control
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GAN-Place: Advancing Open Source Placers to Commercial-quality Using Generative Adversarial Networks and Transfer Learning ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-02-14 Yi-Chen Lu, Haoxing Ren, Hao-Hsiang Hsiao, Sung Kyu Lim
Recently, GPU-accelerated placers such as DREAMPlace and Xplace have demonstrated their superiority over traditional CPU-reliant placers by achieving orders of magnitude speed up in placement runtime. However, due to their limited focus in placement objectives (e.g., wirelength and density), the placement quality achieved by DREAMPlace or Xplace is not comparable to that of commercial tools. In this
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TROP: TRust-aware OPportunistic Routing in NoC with Hardware Trojans ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-02-15 Syam Sankar, Ruchika Gupta, John Jose, Sukumar Nandi
Multiple software and hardware intellectual property (IP) components are combined on a single chip to form Multi-Processor Systems-on-Chips (MPSoCs). Due to the rigid time-to-market constraints, some of the IPs are from outsourced third parties. Due to the supply-chain management of IP blocks being handled by unreliable third-party vendors, security has grown as a crucial design concern in the MPSoC
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Pareto Optimization of Analog Circuits Using Reinforcement Learning ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-02-14 Karthik Somayaji NS, Peng Li
Analog circuit optimization and design presents a unique set of challenges in the IC design process. Many applications require the designer to optimize for multiple competing objectives, which poses a crucial challenge. Motivated by these practical aspects, we propose a novel method to tackle multi-objective optimization for analog circuit design in continuous action spaces. In particular, we propose
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Optimal Model Partitioning with Low-Overhead Profiling on the PIM-based Platform for Deep Learning Inference ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-02-14 Seok Young Kim, Jaewook Lee, Yoonah Paik, Chang Hyun Kim, Won Jun Lee, Seon Wook Kim
Recently Processing-in-Memory (PIM) has become a promising solution to achieve energy-efficient computation in data-intensive applications by placing computation near or inside the memory. In most Deep Learning (DL) frameworks, a user manually partitions a model’s computational graph (CG) onto the computing devices by considering the devices’ capability and the data transfer. The Deep Neural Network
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Energy-Constrained Scheduling for Weakly Hard Real-Time Systems Using Standby-Sparing ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-02-15 Linwei Niu, Danda B. Rawat, Jonathan Musselwhite, Zonghua Gu, Qingxu Deng
For real-time embedded systems, QoS (Quality of Service), fault tolerance, and energy budget constraint are among the primary design concerns. In this research, we investigate the problem of energy constrained standby-sparing for both periodic and aperiodic tasks in a weakly hard real-time environment. The standby-sparing systems adopt a primary processor and a spare processor to provide fault tolerance
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DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-02-15 Newsha Ardalani, Saptadeep Pal, Puneet Gupta
Over the past decade, machine learning model complexity has grown at an extraordinary rate, as has the scale of the systems training such large models. However, there is an alarmingly low hardware utilization (5–20%) in large scale AI systems. The low system utilization is a cumulative effect of minor losses across different layers of the stack, exacerbated by the disconnect between engineers designing
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Enhanced Real-time Scheduling of AVB Flows in Time-Sensitive Networking ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-02-15 Libing Deng, Gang Zeng, Ryo Kurachi, Hiroaki Takada, Xiongren Xiao, Renfa Li, Guoqi Xie
Time-Sensitive Networking (TSN) realizes high bandwidth and time determinism for data transmission and thus becomes the crucial communication technology in time-critical systems. The Gate Control List (GCL) is used to control the transmission of different classes of traffic in TSN, including Time-Triggered (TT) flows, Audio-Video-Bridging (AVB) flows, and Best-Effort (BE) flows. Most studies focus
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Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-02-14 Bo-Yuan Huang, Steven Lyubomirsky, Yi Li, Mike He, Gus Henry Smith, Thierry Tambe, Akash Gaonkar, Vishal Canumalla, Andrew Cheung, Gu-Yeon Wei, Aarti Gupta, Zachary Tatlock, Sharad Malik
Ideally, accelerator development should be as easy as software development. Several recent design languages/tools are working toward this goal, but actually testing early designs on real applications end-to-end remains prohibitively difficult due to the costs of building specialized compiler and simulator support. We propose a new first-in-class, mostly automated methodology termed “3LA” to enable
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RGMU: A High-flexibility and Low-cost Reconfigurable Galois Field Multiplication Unit Design Approach for CGRCA ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-02-15 Danping Jiang, Zibin Dai, Yanjiang Liu, Zongren Zhang
Finite field multiplication is a non-linear transformation operator that appears in the majority of symmetric cryptographic algorithms. Numerous specified finite field multiplication units have been proposed as a fundamental module in the coarse-grained reconfigurable cipher logic array to support more cryptographic algorithms; however, it will introduce low flexibility and high overhead, resulting
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A Module-Level Configuration Methodology for Programmable Camouflaged Logic ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-02-14 Jianfeng Wang, Zhonghao Chen, Jiahao Zhang, Yixin Xu, Tongguang Yu, Ziheng Zheng, Enze Ye, Sumitha George, Huazhong Yang, Yongpan Liu, Kai Ni, Vijaykrishnan Narayanan, Xueqing Li
Logic camouflage is a widely adopted technique that mitigates the threat of intellectual property (IP) piracy and overproduction in the integrated circuit (IC) supply chain. Camouflaged logic achieves functional obfuscation through physical-level ambiguity and post-manufacturing programmability. However, discussions on programmability are confined to the level of logic cells/gates, limiting the broader-scale
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Security of Electrical, Optical, and Wireless On-chip Interconnects: A Survey ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-02-14 Hansika Weerasena, Prabhat Mishra
The advancement of manufacturing technologies has enabled the integration of more intellectual property (IP) cores on the same system-on-chip (SoC). Scalable and high throughput on-chip communication architecture has become a vital component in today’s SoCs. Diverse technologies such as electrical, wireless, optical, and hybrid are available for on-chip communication with different architectures supporting
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IDeSyDe: Systematic Design Space Exploration via Design Space Identification ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-02-10 Rodolfo Jordão, Matthias Becker, Ingo Sander
Design space exploration (DSE) is a key activity in embedded design processes, where a mapping between applications and platforms that meets the process design requirements must be found. Finding such mappings is very challenging due to the complexity of modern embedded platforms and applications. DSE tools aid in this challenge by potentially covering sections of the design space that could be unintuitive
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VeriGen: A Large Language Model for Verilog Code Generation ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-02-09 Shailja Thakur, Baleegh Ahmad, Hammond Pearce, Benjamin Tan, Brendan Dolan-Gavitt, Ramesh Karri, Siddharth Garg
In this study, we explore the capability of Large Language Models (LLMs) to automate hardware design by automatically completing partial Verilog code, a common language for designing and modeling digital systems. We fine-tune pre-existing LLMs on Verilog datasets compiled from GitHub and Verilog textbooks. We evaluate the functional correctness of the generated Verilog code using a specially designed
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Optimizing VLIW Instruction Scheduling via a Two-Dimensional Constrained Dynamic Programming ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-01-25 Can Deng, Zhaoyun Chen, Yang Shi, Yimin Ma, Mei Wen, Lei Luo
Typical embedded processors, such as Digital Signal Processors (DSPs), usually adopt Very Long Instruction Word (VLIW) architecture to improve computing efficiency. The performance of VLIW processors heavily relies on Instruction-Level Parallelism (ILP). Therefore, it is crucial to develop an efficient instruction scheduling algorithm to explore more ILP. While heuristic algorithms are widely used
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An Efficient Reinforcement Learning Based Framework for Exploring Logic Synthesis ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-01-15 Yu Qian, Xuegong Zhou, Hao Zhou, Lingli Wang
Logic synthesis is a crucial step in electronic design automation tools. The rapid developments of reinforcement learning (RL) have enabled the automated exploration of logic synthesis. Existing RL based methods may lead to data inefficiency, and the exploration approaches for FPGA and ASIC technology mapping in recent works lack the flexibility of the learning process. This work proposes ESE, a reinforcement
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SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-01-15 Bo Wang, Sheng Ma, Shengbai Luo, Lizhou Wu, Jianmin Zhang, Chunyuan Zhang, Tiejun Li
Deep learning has become a highly popular research field, and previously deep learning algorithms ran primarily on CPUs and GPUs. However, with the rapid development of deep learning, it was discovered that existing processors could not meet the specific large-scale computing requirements of deep learning, and custom deep learning accelerators have become popular. The majority of the primary workloads
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RSPP: Restricted Static Pseudo-Partitioning for Mitigation of Cross-Core Covert Channel Attacks ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-01-15 Jaspinder Kaur, Shirshendu Das
Cache timing channel attacks exploit the inherent properties of cache memories: hit and miss time along with the shared nature of the cache to leak secret information. The side channel and covert channel are the two well-known cache timing channel attacks. In this article, we propose Restricted Static Pseudo-Partitioning (RSPP), an effective partition-based mitigation mechanism that restricts the cache
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Dynamic Adaptation Using Deep Reinforcement Learning for Digital Microfluidic Biochips ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2024-01-15 Tung-Che Liang, Yi-Chen Chang, Zhanwei Zhong, Yaas Bigdeli, Tsung-Yi Ho, Krishnendu Chakrabarty, Richard Fair
We describe an exciting new application domain for deep reinforcement learning (RL): droplet routing on digital microfluidic biochips (DMFBs). A DMFB consists of a two-dimensional electrode array, and it manipulates droplets of liquid to automatically execute biochemical protocols for clinical chemistry. However, a major problem with DMFBs is that electrodes can degrade over time. The transportation
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BOOM-Explorer: RISC-V BOOM Microarchitecture Design Space Exploration ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-12-18 Chen Bai, Qi Sun, Jianwang Zhai, Yuzhe Ma, Bei Yu, Martin D. F. Wong
Microarchitecture parameters tuning is critical in the microprocessor design cycle. It is a non-trivial design space exploration (DSE) problem due to the large solution space, cycle-accurate simulators’ modeling inaccuracy, and high simulation runtime for performance evaluations. Previous methods require massive expert efforts to construct interpretable equations or high computing resource demands
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Mathematical Framework for Optimizing Crossbar Allocation for ReRAM-based CNN Accelerators ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-12-18 Wanqian Li, Yinhe Han, Xiaoming Chen
The resistive random-access memory (ReRAM) has widely been used to accelerate convolutional neural networks (CNNs) thanks to its analog in-memory computing capability. ReRAM crossbars not only store layers’ weights, but also perform in-situ matrix-vector multiplications which are core operations of CNNs. To boost the performance of ReRAM-based CNN accelerators, crossbars can be duplicated to explore
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Introduction to the Special Issue on Design for Testability and Reliability of Security-aware Hardware ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-12-18 Tianming Ni, Xiaoqing Wen, Hussam Amrouch, Cheng Zhuo, Peilin Song
The research on design for testability and reliability of security-aware hardware has been important in both academia and industry. With ever-growing globalization, commercial hardware design, manufacturing, transportation, and supply now involve many different countries, resulting in aggravated vulnerability from hardware design to manufacturing. Hardware with malicious purposes implanted from the
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Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-12-18 Monzurul Islam Dewan, Sheng-En David Lin, Dae Hyun Kim
Monolithic three-dimensional (M3D) integration allows ultra-thin silicon tier stacking in a single package. The high-density stacking is acquiring interest and is becoming more popular for smaller footprint areas, shorter wirelength, higher performance, and lower power consumption than the conventional planar fabrication technologies. The physical design of M3D integrated circuits requires several
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A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-12-18 Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar
Due to the unavailability of routing information in design stages prior to detailed routing (DR), the tasks of timing prediction and optimization pose major challenges. Inaccurate timing prediction wastes design effort, hurts circuit performance, and may lead to design failure. This work focuses on timing prediction after clock tree synthesis and placement legalization, which is the earliest opportunity
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NeuroCool: Dynamic Thermal Management of 3D DRAM for Deep Neural Networks through Customized Prefetching ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-12-18 Shailja Pandey, Lokesh Siddhu, Preeti Ranjan Panda
Deep neural network (DNN) implementations are typically characterized by huge datasets and concurrent computation, resulting in a demand for high memory bandwidth due to intensive data movement between processors and off-chip memory. Performing DNN inference on general-purpose cores/edge is gaining attraction to enhance user experience and reduce latency. The mismatch in the CPU and conventional DRAM
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Flip: Data-centric Edge CGRA Accelerator ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-12-18 Dan Wu, Peng Chen*, Thilini Kaushalya Bandara, Zhaoying Li, Tulika Mitra
Coarse-Grained Reconfigurable Arrays (CGRA) are promising edge accelerators due to the outstanding balance in flexibility, performance, and energy efficiency. Classic CGRAs statically map compute operations onto the processing elements (PE) and route the data dependencies among the operations through the Network-on-Chip. However, CGRAs are designed for fine-grained static instruction-level parallelism
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A High Throughput STR-based TRNG by Jitter Precise Quantization Superposing ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-11-15 Yuan Zhang, Jiliang Zhang
With the rapid development of integrated circuits and the continuous progress of computing capability, higher demands have been placed on the security and speed of data encryption in security systems. As a basic hardware security primitive, the true random number generator (TRNG) plays an important role in the encryption system, which requires higher throughput and randomness with lower hardware overhead
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An Efficient Ring Oscillator PUF Using Programmable Delay Units on FPGA ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-11-16 Yijun Cui, Jiang Li, Yunpeng Chen, Chenghua Wang, Chongyan Gu, Máire O’neill, Weiqiang Liu
The ring oscillator (RO) PUF can be implemented on different FPGA platforms with high uniqueness and reliability. To decrease the hardware cost of conventional RO PUFs, a new design using the programmable delay units is proposed, namely, PRO PUF. The programmable interconnect points (PIPs) of programmable delay units are used to enhance the configurability. The PUF cell of the proposed design has the
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ICP-RL: Identifying Critical Paths for Fault Diagnosis Using Reinforcement Learning ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-11-15 Jie Xiao, Yingying Ge, Ru Wang, Jungang Lou
Identifying the critical paths is crucial to reducing the complexity of performance analysis and reliability calculation for logic circuits. In this article, we propose a method for identifying the critical path in a combination circuit using a reinforcement learning framework to enhance its applicability and compatibility. Initially, we configured the learning environment of the model based on circuit
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Lightning: Leveraging DVFS-induced Transient Fault Injection to Attack Deep Learning Accelerator of GPUs ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-11-15 Rihui Sun, Pengfei Qiu, Yongqiang Lyu, Jian Dong, Haixia Wang, Dongsheng Wang, Gang Qu
Graphics Processing Units (GPU) are widely used as deep learning accelerators because of its high performance and low power consumption. Additionally, it remains secure against hardware-induced transient fault injection attacks, a classic type of attacks that have been developed on other computing platforms. In this work, we demonstrate that well-trained machine learning models are robust against hardware
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MOEA/D vs. NSGA-II: A Comprehensive Comparison for Multi/Many Objective Analog/RF Circuit Optimization through a Generic Benchmark ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-11-15 Enes Saǧlican, Engin Afacan
Thanks to the enhanced computational capacity of modern computers, even sophisticated analog/radio frequency (RF) circuit sizing problems can be solved via electronic design automation (EDA) tools. Recently, several analog/RF circuit optimization algorithms have been successfully applied to automatize the analog/RF circuit design process. Conventionally, metaheuristic algorithms are widely used in
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ProtFe: Low-Cost Secure Power Side-Channel Protection for General and Custom FeFET-Based Memories ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-11-15 Taixin Li, Boran Sun, Hongtao Zhong, Yixin Xu, Vijaykrishnan Narayanan, Liang Shi, Tianyi Wang, Yao Yu, Thomas Kämpfe, Kai Ni, Huazhong Yang, Xueqing Li
Ferroelectric Field Effect Transistors (FeFETs) have spurred increasing interest in both memories and computing applications, thanks to their CMOS compatibility, low-power operation, and high scalability. However, new security threats to the FeFET-based memories also arise. A major threat is the power analysis side-channel attack (P-SCA), which exploits the power traces of the memory access to obtain
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On-chip ESD Protection Design Methodologies by CAD Simulation ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-11-15 Zijin Pan, Xunyu Li, Weiquan Hao, Runyu Miao, Albert Wang
Electrostatic discharge (ESD) can cause malfunction or failure of integrated circuits (ICs). On-chip ESD protection design is a major IC design-for-reliability (DfR) challenge, particularly for complex chips made in advanced technology nodes. Traditional trial-and-error approaches become unacceptable to practical ESD protection designs for advanced ICs. Full-chip ESD protection circuit design optimization
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A Reliability-Aware Splitting Duty-Cycle Physical Unclonable Function Based on Trade-off Process, Voltage, and Temperature Variations ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-11-15 Jingchang Bian, Zhengfeng Huang, Peng Ye, Zhao Yang, Huaguo Liang
The physical unclonable function (PUF) is a hardware security primitive that can be used to prevent malicious attacks aimed at obtaining device information at the hardware level. The ring oscillator (RO) PUF has attracted considerable research attention. To improve the reliability of the RO PUF under voltage and temperature changes, the response of the duty-cycle (DC) PUF was obtained by comparing
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Test Compression for Launch-on-Capture Transition Fault Testing ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-11-15 Dong Xiang
A new low-power test compression scheme, called Dcompress, is proposed for launch-on-capture transition fault testing by using a new seed encoding scheme, a new design for testability architecture, and a new low-power test application procedure. The new seed encoding scheme generates seeds for all tests by selecting a primitive polynomial that encodes all tests of a compact test set. A software-defined
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AD2VNCS: Adversarial Defense and Device Variation-tolerance in Memristive Crossbar-based Neuromorphic Computing Systems ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-11-15 Yongtian Bi, Qi Xu, Hao Geng, Song Chen, Yi Kang
In recent years, memristive crossbar-based neuromorphic computing systems (NCS) have obtained extremely high performance in neural network acceleration. However, adversarial attacks and conductance variations of memristors bring reliability challenges to NCS design. First, adversarial attacks can fool the neural network and pose a serious threat to security critical applications. However, device variations
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Heterogeneous Integration Supply Chain Integrity Through Blockchain and CHSM ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-11-15 Paul E. Calzada, Md. Sami Ul Islam Sami, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark Tehranipoor
Over the past few decades, electronics have become commonplace in government, commercial, and social domains. These devices have developed rapidly, as seen in the prevalent use of system-on-chips rather than separate integrated circuits on a single circuit board. As the semiconductor community begins conversations over the end of Moore’s law, an approach to further increase both functionality per area
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The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-11-15 Xiaole Cui, Mingqi Yin, Hanqing Liu, Xiaoxin Cui
The resistive random access memory (RRAM) based in-memory computing (IMC) is an emerging architecture to address the challenge of the “memory wall” problem. The complementary resistive switch (CRS) cell connects two bipolar RRAM elements anti-serially to reduce the sneak current in the crossbar array. The CRS array is a generic computing platform, for the arbitrary logic functions can be implemented
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Yield Optimization for Analog Circuits over Multiple Corners via Bayesian Neural Networks: Enhancing Circuit Reliability under Environmental Variation ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-11-15 Nanlin Guo, Fulin Peng, Jiahe Shi, Fan Yang, Jun Tao, Xuan Zeng
The reliability of circuits is significantly affected by process variations in manufacturing and environmental variation during operation. Current yield optimization algorithms take process variations into consideration to improve circuit reliability. However, the influence of environmental variations (e.g., voltage and temperature variations) is often ignored in current methods because of the high
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A Compact TRNG Design for FPGA Based on the Metastability of RO-driven Shift Registers ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-11-15 Qingsong Peng, Jingchang Bian, Zhengfeng Huang, Senling Wang, Aibin Yan
True random number generators (TRNGs), as an important component of security systems, have received a lot of attention for their related research. The previous researches have provided a large number of TRNG solutions, however, they still failed to reach an excellent tradeoff in various performance metrics. This article presents a shift-registers metastability-based TRNG, which is implemented by compact
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NPU-Accelerated Imitation Learning for Thermal Optimization of QoS-Constrained Heterogeneous Multi-Cores ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-11-15 Martin Rapp, Heba Khdr, Nikita Krohmer, Jörg Henkel
Thermal optimization of a heterogeneous clustered multi-core processor under user-defined QoS targets requires application migration and DVFS. However, selecting the core to execute each application and the VF levels of each cluster is a complex problem because (1) the diverse characteristics and QoS targets of applications require different optimizations, and (2) per-cluster DVFS requires a global
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Surrogate Lagrangian Relaxation: A Path to Retrain-Free Deep Neural Network Pruning ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-10-28 Shanglin Zhou, Mikhail A. Bragin, Deniz Gurevin, Lynn Pepin, Fei Miao, Caiwen Ding
Network pruning is a widely used technique to reduce computation cost and model size for deep neural networks. However, the typical three-stage pipeline (i.e., training, pruning, and retraining (fine-tuning)) significantly increases the overall training time. In this article, we develop a systematic weight-pruning optimization approach based on surrogate Lagrangian relaxation (SLR), which is tailored
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Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-10-28 Bo Ding, Jinglei Huang, Junpeng Wang, Qi Xu, Song Chen, Yi Kang
Some field programmable gate arrays (FPGAs) can be partially dynamically reconfigurable with heterogeneous resources distributed on the chip. FPGA-based partially dynamically reconfigurable system (FPGA-PDRS) can be used to accelerate computing and improve computing flexibility. However, the traditional design of FPGA-PDRS is based on manual design. Implementing the automation of FPGA-PDRS needs to
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Sequential Routing-based Time-division Multiplexing Optimization for Multi-FPGA Systems ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-10-28 Wenxiong Lin, Haojie Wu, Peng Gao, Wenjun Luo, Shuting Cai, Xiaoming Xiong
Multi-field programming gate array (FPGA) systems are widely used in various circuit design-related areas, such as hardware emulation, virtual prototypes, and chiplet design methodologies. However, a physical resource clash between inter-FPGA signals and I/O pins can create a bottleneck in a multi-FPGA system. Specifically, inter-FPGA signals often outnumber I/O pins in a multi-FPGA system. To solve
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Design of Enhanced Reversible 9T SRAM Design for the Reduction in Sub-threshold Leakage Current with14nm FinFET Technology ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-10-28 Pushkar Praveen, R. K. Singh
Power dissipation is considered one of the important issues in low power Very-large-scale integration (VLSI) circuit design and is related to the threshold voltage. Generally, the sub-threshold leakage current and the leakage power dissipation are increased by reducing the threshold voltage. The overall performance of the circuit completely depends on this leakage power dissipation because this leakage
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A General Layout Pattern Clustering Using Geometric Matching-based Clip Relocation and Lower-bound Aided Optimization ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-10-16 Xu He, Yao Wang, Zhiyong Fu, Yipei Wang, Yang Guo
With the continuous shrinking of feature size, detection of lithography hotspots has been raised as one of the major concerns in Design-for-Manufacturability (DFM) of semiconductor processing. Hotspot detection, along with other DFM measures, trades off turnaround time for the yield of IC manufacturing, and thus a simplified but wide-ranging pattern definition is a key to the problem. Layout pattern
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TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems ACM Trans. Des. Autom. Electron. Syst. (IF 1.4) Pub Date : 2023-10-16 Debabrata Senapati, Kousik Rajesh, Chandan Karfa, Arnab Sarkar
To meet application-specific performance demands, recent embedded platforms often involve the use of intricate micro-architectural designs and very small feature sizes leading to complex chips with multi-million gates. Such ultra-high gate densities often make these chips susceptible to inappropriate surges in core temperatures. Temperature surges above a specific threshold may throttle processor performance