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FPGA approximate logic synthesis through catalog-based AIG-rewriting technique J. Syst. Archit. (IF 4.5) Pub Date : 2024-03-18 Mario Barbareschi, Salvatore Barone, Nicola Mazzocca, Alberto Moriconi
Due to their run-time reconfigurability, short time-to-market, and lower prototype costs, FPGAs have become increasingly popular since their introduction. They found use in a wide variety of applications, including high-performance computing. However, when compared to ASICs, FPGAs offer lower performance, and they are power-hungry devices with low energy-efficiency. The emergence of Approximate Computing
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Adaptive approximate computing in edge AI and IoT applications: A review J. Syst. Archit. (IF 4.5) Pub Date : 2024-03-17 Hans Jakob Damsgaard, Antoine Grenier, Dewant Katare, Zain Taufique, Salar Shakibhamedan, Tiago Troccoli, Georgios Chatzitsompanis, Anil Kanduri, Aleksandr Ometov, Aaron Yi Ding, Nima Taherinejad, Georgios Karakonstantis, Roger Woods, Jari Nurmi
Recent advancements in hardware and software systems have been driven by the deployment of emerging smart health and mobility applications. These developments have modernized the traditional approaches by replacing conventional computing systems with cyber–physical and intelligent systems combining the Internet of Things (IoT) with Edge Artificial Intelligence. Despite the many advantages and opportunities
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Cold Start Latency Mitigation Mechanisms in Serverless Computing: Taxonomy, Review, and Future Directions J. Syst. Archit. (IF 4.5) Pub Date : 2024-03-16 Ana Ebrahimi, Mostafa Ghobaei-Arani, Hadi Saboohi
Today, Function-as-a-Service (FaaS), as an emerging path to implementing serverless computing paradigm, seems quite promising in responding to the growing increase in requests for microservices. However, the serverless computing model also brings new challenges. Although the execution time of the functions is very short in FaaS, the initialization of containers and cold start is time-consuming and
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Efficient and self-recoverable privacy-preserving k-NN classification system with robustness to network delay J. Syst. Archit. (IF 4.5) Pub Date : 2024-03-16 Jinhai Zhang, Junwei Zhang, Zhuo Ma, Yang Liu, Xindi Ma, Jianfeng Ma
Online classification services based on machine learning have been widely used in fields such as healthcare and finance. To enhance the data privacy and avoid server collusion, companies usually deploy each server on different cloud service providers in distant regions separately, which implies high network delay between servers. However, many existing schemes inevitably involve a large number of communication
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Pflow: An end-to-end heterogeneous acceleration framework for CNN inference on FPGAs J. Syst. Archit. (IF 4.5) Pub Date : 2024-03-15 Yi Wan, Xianzhong Xie, Lingjie Yi, Bo Jiang, Junfan Chen, Yi Jiang
Field-Programmable Gate Arrays (FPGAs), renowned for their high performance per watt, are extensively utilized to accelerate Convolutional Neural Networks (CNNs) in edge computing environments, primarily employing dataflow-based and instruction set-based approaches. Compared to the instruction set-based approach that features fast and versatile circuit design, the dataflow-based approach can significantly
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Fed-MPS: Federated learning with local differential privacy using model parameter selection for resource-constrained CPS J. Syst. Archit. (IF 4.5) Pub Date : 2024-03-15 Shui Jiang, Xiaoding Wang, Youxiong Que, Hui Lin
In Cyber-Physical Systems (CPS), distributed learning is essential for efficiently handling complex tasks when sufficient resources are available. However, when resources are limited, traditional distributed learning struggles to complete even simple tasks and presents a risk of privacy leakage. As a promising distributed learning paradigm, federated learning only requires the client to send the trained
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Caiti: I/O transit caching for persistent memory-based block device J. Syst. Archit. (IF 4.5) Pub Date : 2024-03-13 Qing Xu, Qisheng Jiang, Chundong Wang
Byte-addressable non-volatile memory (NVM) sitting on the memory bus is employed to make (pmem) in general-purpose computing systems and embedded systems for data storage. Researchers develop software drivers such as the block translation table (BTT) to build block devices on pmem, so programmers can keep using mature and reliable conventional storage stack while expecting high performance by exploiting
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Sensor attack detection based on active excitation response with uncertain delays J. Syst. Archit. (IF 4.5) Pub Date : 2024-03-13 Yanfeng Chen, Zhiwei Feng, Qingxu Deng, Yan Wang
Cyber–physical systems face the threat of sensor attacks, which can result in incorrect measurements of the physical state for the controller and lead to erroneous decisions and control instructions. To address this issue, our paper introduces a sensor attack detection method involving the active injection of excitation into the system and a comparison of actual sensor data with the expected response
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SecurityCloak: Protection against cache timing and speculative memory access attacks J. Syst. Archit. (IF 4.5) Pub Date : 2024-03-09 Fernando Mosquera, Ashen Ekanayake, William Hua, Krishna Kavi, Gayatri Mehta, Lizy John
Microarchitectural innovations such as deep cache hierarchies, out-of-order execution, branch prediction and speculative execution in modern processors have made possible to meet ever-increasing demands for performance. However, these innovations have inadvertently introduced vulnerabilities that are exploited by cache-side channel attacks such as Flush & Reload, Prime & Probe, Evict & Time, and attacks
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Blockchain-enabled one-to-many searchable encryption supporting designated server and multi-keywords for Cloud-IoMT J. Syst. Archit. (IF 4.5) Pub Date : 2024-03-07 Hongtao Yu, Suhui Liu, Liquan Chen, Yuan Gao
In smart wards, data generated by wearables and monitoring devices are periodically transferred to the cloud server for long-term logging and subsequent access. Remote cloud storage inevitably raises security and access control challenges. Encryption can secure data but may severely impact the value generated by sharing data. More importantly, the privacy leakage caused by keyword searches is unacceptable
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CUTE: A scalable CPU-centric and Ultra-utilized Tensor Engine for convolutions J. Syst. Archit. (IF 4.5) Pub Date : 2024-03-06 Wenqing Li, Jinpeng Ye, Fuxin Zhang, Tianyi Liu, Tingting Zhang, Jian Wang
Convolution is a fundamental and computationally expensive primitive and finds ubiquitous in deep neural networks (DNNs). The evolving DNNs have spurred the emergence of numerous accelerators and they successfully achieve high throughput. However, for DNN inference with small batch sizes, the computational resources of the accelerators are often under-utilized, and the overhead of offloading is significant
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An intelligent assistive driving solution based on smartphone for power wheelchair mobility J. Syst. Archit. (IF 4.5) Pub Date : 2024-03-06 Zhiwei Wang, Jingye Xu, Jianqiu Zhang, Rocky Slavin, Dakai Zhu
This research introduces a cost-effective, smartphone-powered, computer-vision-based system for Power Wheelchair Intelligent Assistive Driving (PWC IA-Driving). This system enables the safe, hands-free operation of a Power Wheelchair (PWC) with reduced attention required from the user in indoor environments, thereby easing the burden on disabled individuals and lessening their stress. Our objective
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A traceable and revocable broadcast encryption scheme for preventing malicious encryptors in Medical IoT J. Syst. Archit. (IF 4.5) Pub Date : 2024-03-06 Shuanggen Liu, Hailun Pan, Xu An Wang, Siyi Zhao, Qing Li
Medical data sharing is essential for the advancement of medical research, but the existence of malicious encryptors and malicious users poses a major challenge to the seamless sharing of information among healthcare providers. We proposed a traceable and revocable broadcast encryption scheme for preventing malicious encryptors in the Medical Internet of Things (MIoT). In 2023, Wang et al. first proposed
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Efficient public-key searchable encryption against inside keyword guessing attacks for cloud storage J. Syst. Archit. (IF 4.5) Pub Date : 2024-03-05 Axin Wu, Fagen Li, Xiangjun Xin, Yinghui Zhang, Jianhao Zhu
Cloud storage offers data users relief from cumbersome management tasks and enhances overall efficiency. However, while it brings convenience, there is also the risk of privacy breaches. To address this, public-key encryption with keyword search (PEKE) presents a solution that balances efficiency, convenience, and security in the context of cloud storage. Nevertheless, PEKS is vulnerable to inside
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Analyzing the memory ordering models of the Apple M1 J. Syst. Archit. (IF 4.5) Pub Date : 2024-03-04 Lars Wrenger, Dominik Töllner, Daniel Lohmann
The Apple M1 ARM processor family incorporates two memory consistency models: the conventional ARM weak memory ordering and the model from the x86 architecture utilized by Apple’s x86 emulator, Rosetta 2. The presence of both memory ordering models on the same hardware enables us to thoroughly benchmark and compare their performance characteristics and worst-case workloads.
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Active and passive virtual machine introspection on AMD and ARM processors J. Syst. Archit. (IF 4.5) Pub Date : 2024-03-01 Thomas Dangl, Stewart Sentanoe, Hans P. Reiser
Active and passive virtual machine introspection mechanisms are pivotal for monitoring virtual machines on top of a hypervisor. They enable external tools to monitor and inspect the state from the outside. Active virtual machine introspection mechanisms intercept the execution at predetermined locations of interest synchronous to the execution of the system. Such mechanisms, in particular, require
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Conflict-aware compiler for hierarchical register file on GPUs J. Syst. Archit. (IF 4.5) Pub Date : 2024-02-29 Eunbi Jeong, Eun Seong Park, Gunjae Koo, Yunho Oh, Myung Kuk Yoon
Modern graphics processing units (GPUs) leverage a high degree of thread-level parallelism, necessitating large-sized register files for storing numerous thread contexts. To reduce the energy consumption in traditional static random access memory (SRAM)-based register files, recent research has explored non-volatile memory (NVM) for implementing register files. The hierarchical register file (HI-RF)
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Hybrid Privacy Preserving Federated Learning Against Irregular Users in Next-Generation Internet of Things J. Syst. Archit. (IF 4.5) Pub Date : 2024-02-17 Abbas Yazdinejad, Ali Dehghantanha, Gautam Srivastava, Hadis Karimipour, Reza M. Parizi
While federated learning (FL) is a well-known privacy-preserving (PP) solution, recent studies demonstrate that it still has privacy problems and vulnerabilities, particularly in the context of the Next Generation Internet-of-Things (NG-IoT). Attackers on the server can potentially retrieve sensitive information such as data tabs and memberships. Additionally, current FL studies often overlook critical
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Network traffic classification based on federated semi-supervised learning J. Syst. Archit. (IF 4.5) Pub Date : 2024-02-17 ZiXuan Wang, ZeYi Li, MengYi Fu, YingChun Ye, Pan Wang
Traffic Classification (TC) has been applied to a wide range of applications, from security monitoring to quality of service (QoS) provisioning in network Internet Service Providers (ISPs). In recent years, many researchers have applied Machine Learning (ML) or Deep Learning (DL) to TC, namely AI-TC. However, AI-TC methods face significant challenges, including high data dependency, exhaustively costly
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Machine learning-based computation offloading in multi-access edge computing: A survey J. Syst. Archit. (IF 4.5) Pub Date : 2024-02-16 Alok Choudhury, Manojit Ghose, Akhirul Islam, Yogita
The advancement of technology towards the realization of the evolving mobile computing paradigm brings a rapid paradigm shift in its usage, especially in the Internet, computation, and communications, that has a profound impact on businesses, services, and users. With the rise in resource-intensive or edge-based mobile applications such as autonomous driving, Amazon Go, virtual and augmented reality
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Efficient secure channel free identity-based searchable encryption schemes with privacy preserving for cloud storage service J. Syst. Archit. (IF 4.5) Pub Date : 2024-02-15 Fenghe Wang, Han Xiao, Junquan Wang, Ye Wang, Chengliang Cao
Cloud storage is a basic service model of the cloud computing. Since the cloud data is stored in the ciphertext for the data confidentiality, how to search the cloud data again in ciphertext state for users is a natural requirement. The searchable encryption (SE) gives an efficient solution to achieve both the data confidentiality and the searchable requirement simultaneously. In SE schemes, the user
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Doppel: A BFT consensus algorithm for cyber-physical systems with low latency J. Syst. Archit. (IF 4.5) Pub Date : 2024-02-09 Rui Hao, Xiaohai Dai, Xia Xie
The integration of blockchain technology with (CPS) has gained significant attention across various industry domains such as manufacturing, healthcare, transportation, and energy management. The consensus mechanism serves as the fundamental component of decentralized blockchain systems, and the efficiency of the consensus algorithm greatly impacts the practicality of the entire system. One of the most
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Parametric WCET as a function of procedure arguments: Analysis and applications J. Syst. Archit. (IF 4.5) Pub Date : 2024-02-08 Sandro Grebant, Clément Ballabriga, Julien Forget, Giuseppe Lipari
Traditional Worst-Case Execution Time analysis derives an upper-bound to the execution time of a program for any possible combination of its software and hardware parameters. In comparison, Parametric Worst-Case Execution Time analysis derives a WCET formula that depends on the parameters. The formula can then be instantiated for some given parameter values, to produce a WCET that is specific to those
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An efficient multi-task learning CNN for driver attention monitoring J. Syst. Archit. (IF 4.5) Pub Date : 2024-02-07 Dawei Yang, Yan Wang, Ran Wei, Jiapeng Guan, Xiaohua Huang, Wei Cai, Zhe Jiang
Driver Monitoring System (DMS), usually equipped with a camera, is an emerging vehicle safety system that can monitor driver attentiveness and trigger timely alarms when signs of inattention are detected. Since a single indicator (e.g., eye blink rate) is insufficient and unreliable to analyze driver attentiveness, almost all existing solutions train several independent models to identify driver facial
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VPSS: A DAG scheduling heuristic with improved response time bound J. Syst. Archit. (IF 4.5) Pub Date : 2024-02-05 Feng Li, Ran Bi, Jiarui Wang, Jinghao Sun, Zhenyu Sun, Guozhen Tan, Minsong Chen
Real-time and embedded systems are shifting from single-core to multi-core platforms, on which software must be parallelized to fully utilize the computation power of multi-core hardware. Most current real-time parallel tasks can be modeled as directed acyclic graphs (DAG). Scheduling DAG tasks on multi-core processors is a key issue for high-performance computing, and in real-time scenario, a good
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HiEval: A scheduling performance estimation approach for spatial accelerators via hierarchical abstraction J. Syst. Archit. (IF 4.5) Pub Date : 2024-02-03 Zhipeng Wu, Yue Hu, Ning Li, Wei Lu, Yu Liu
Workload scheduling strategy, referred to as mapping, plays a vital role in exploring hardware spatial accelerator performance. Evaluating all possible mappings experimentally is infeasible, thus we propose HiEval, to efficiently and accurately evaluate the scheduling performance for the spatial accelerator. HiEval adopts a holistic representation that succinctly captures varying hardware organizations
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Ensuring consistent recovery under power failure with minimal NVM write overhead J. Syst. Archit. (IF 4.5) Pub Date : 2024-02-02 Min Jia, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Rui Xu
Intermittent embedded devices and systems are widely used in various scenarios, but they often experience power failures due to unstable power supplies. Non-volatile memory (NVM) is gaining popularity in embedded systems due to its byte-addressability, low access latency, and high density. As a result, backups can be stored in NVM, and global data are directly manipulated in NVM in this architecture
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Automating application-driven customization of ASIPs: A survey J. Syst. Archit. (IF 4.5) Pub Date : 2024-02-01 Eslam Hussein, Bernd Waschneck, Christian Mayr
The rapid advancements and stringent requirements of modern embedded computing systems have led to a surge in the demand for customized processors that can efficiently cater to specific application needs. This survey paper delves into the realm of automating application-driven customization of extensible processors, offering insights into the challenges, advancements, and trends in this domain. It
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VSPAKE: Provably secure verifier-based PAKE protocol for client/server model in TLS ciphersuite J. Syst. Archit. (IF 4.5) Pub Date : 2024-02-01 M, i, n, g, p, i, n, g, , Q, i
Nowadays, password-authenticated key exchange (PAKE) protocols have actually been widely used in our daily life to provide security assurance, by which two parties can achieve mutual authentication and cryptographic session key establishment via a shared memorable password. In this paper, an efficient verifier-based PAKE protocol is presented in the form of TLS ciphersuite, which is essentially a variant
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Attribute-based searchable encryption with decentralized key management for healthcare data sharing J. Syst. Archit. (IF 4.5) Pub Date : 2024-02-01 Hongjian Yin, Yiming Zhao, Lei Zhang, Baojun Qiao, Wenbo Chen, Huaqing Wang
In this paper, we address the secure sharing of sensitive healthcare data in blockchain-based healthcare. As a form of sensitive information, healthcare data is often encrypted before being uploaded to cloud servers. Extensive research has been conducted on Attribute-Based Searchable Encryption (ABSE) to achieve fine-grained searchability of encrypted sensitive healthcare data. However, the existing
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Homogeneous teacher based buffer knowledge distillation for tiny neural networks J. Syst. Archit. (IF 4.5) Pub Date : 2024-01-28 Xinru Dai, Gang Lu, Jianhua Shen, Shuo Huang, Tongquan Wei
Knowledge Distillation (KD) has shown great promise in improving the performance of tiny neural networks. Most existing KD methods have the large teacher–student discrepancy, thus, students hardly learn useful knowledge and may not achieve effective distillation.
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Code generation for Security and Stability Control System based on extended reactive component J. Syst. Archit. (IF 4.5) Pub Date : 2024-01-27 Qianwen Gou, Yunwei Dong, Bo Shen
The Security and Stability Control System (SSCS) is developed to ensure the safe and stable operation of power grids, effectively mitigating failure propagation through emergency control strategies. However, due to the diversity, complexity, and region-specific nature of SSCS, the need for individualized development often arises, leading to time-consuming and error-prone in SSCS development. To address
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Real-time rate control of WebRTC video streams in 5G networks: Improving quality of experience with Deep Reinforcement Learning J. Syst. Archit. (IF 4.5) Pub Date : 2024-01-26 Nikita Smirnov, Sven Tomforde
Adapting to a dynamic environment is a critical challenge in deploying robust systems that will be tasked with transmitting media streams in 5G networks. The Web Real-Time Communication (WebRTC) protocol is one of the most popular solutions for real-time communication, providing sub-second latency. This paper deals with a model-free Deep Reinforcement Learning approach designed to improve the quality
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HCEC: An efficient geo-distributed deep learning training strategy based on wait-free back-propagation J. Syst. Archit. (IF 4.5) Pub Date : 2024-01-26 Yingjie Song, Yongbao Ai, Xiong Xiao, Zhizhong Liu, Zhuo Tang, Kenli Li
Valuable data is often distributed across multiple data centers (DCs). Deep learning (DL) tasks, constrained by privacy regulations, utilize local training and model averaging to facilitate collaborative training across multiple DCs. However, the hierarchical bandwidth within and between DCs diminishes the training efficiency for decentralized data. Therefore, it is imperative to prioritize research
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Time-predictable task-to-thread mapping in multi-core processors J. Syst. Archit. (IF 4.5) Pub Date : 2024-01-26 Mohammad Samadi, Sara Royuela, Luis Miguel Pinho, Tiago Carvalho, Eduardo Quiñones
The performance of time-predictable systems can be improved in multi-core processors using parallel programming models (e.g., OpenMP). However, schedulability analysis of parallel applications is a big challenge due to their sophisticated structure. The common drawbacks of current task-to-thread mapping approaches in OpenMP are that they (i) utilize a global queue in the mapping process, which may
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CLFLDP: Communication-efficient layer clipping federated learning with local differential privacy J. Syst. Archit. (IF 4.5) Pub Date : 2024-01-26 Shuhong Chen, Jiawei Yang, Guojun Wang, Zijia Wang, Haojie Yin, Yinglin Feng
Privacy preserving is a severe challenge in machine learning and artificial intelligence. Recently, many works have been devoted to solving this problem by proposing various federated learning frameworks and introducing local differential privacy. However, applying local differential privacy to federated learning has lower utility after perturbing the parameters. Therefore, to improve the accuracy
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Post-training quantization for re-parameterization via coarse & fine weight splitting J. Syst. Archit. (IF 4.5) Pub Date : 2024-01-20 Dawei Yang, Ning He, Xing Hu, Zhihang Yuan, Jiangyong Yu, Chen Xu, Zhe Jiang
Although neural networks have made remarkable advancements in various applications, they require substantial computational and memory resources. Network quantization is a powerful technique to compress neural networks, allowing for more efficient and scalable AI deployments. Recently, Re-parameterization has emerged as a promising technique to enhance model performance while simultaneously alleviating
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A survey on mapping and scheduling techniques for 3D Network-on-chip J. Syst. Archit. (IF 4.5) Pub Date : 2024-01-10 Simran Preet Kaur, Manojit Ghose, Ananya Pathak, Rutuja Patole
Network-on-chips (NoCs) have been widely employed in the design of multiprocessor system-on-chips (MPSoCs) as a scalable communication solution. NoCs enable communications between on-chip Intellectual Property (IP) cores to perform a task seamlessly collaborating among them. Mapping and Scheduling methodologies are key elements in assigning application tasks, allocating the tasks to the IPs, and organizing
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FDAN: Fuzzy deep attention networks for driver behavior recognition J. Syst. Archit. (IF 4.5) Pub Date : 2024-01-09 Weichu Xiao, Guoqi Xie, Hongli Liu, Weihong Chen, Renfa Li
Driver behavior is an essential factor affecting traffic safety, and driver behavior monitoring systems (DMSs) are widely exploited in intelligent transportation systems to reduce the risk of traffic accidents. However, understanding driver behavior is challenging because of the uncertainty of real driving scenarios. Most of the existing methods use deterministic models, which suffer from data uncertainty
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BDACD: Blockchain-based decentralized auditing supporting ciphertext deduplication J. Syst. Archit. (IF 4.5) Pub Date : 2023-12-15 Yongliang Xu, Chunhua Jin, Wenyu Qin, Jie Zhao, Guanhua Chen, Fugeng Zeng
Public auditing enables data owners to entrust a third-party auditor (TPA) to perform auditing tasks periodically. To resist malicious TPAs, a plethora of blockchain-based public auditing mechanisms have been proposed. However, existing schemes cannot effectively mitigate single point of failure and collusion between TPAs and miners. These schemes are burdened by significant wastage of storage resources
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Hydra: Hybrid-model federated learning for human activity recognition on heterogeneous devices J. Syst. Archit. (IF 4.5) Pub Date : 2023-12-11 Pu Wang, Tao Ouyang, Qiong Wu, Qianyi Huang, Jie Gong, Xu Chen
Federated Learning (FL) has recently received extensive attention in enabling privacy-preserving edge AI services for Human Activity Recognition (HAR). However, users’ mobile and wearable devices in the HAR scenario usually possess dramatically different computing capability and diverse data distributions, making it very challenging for such heterogeneous HAR devices to conduct effective collaborative
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Mutation testing of unsupervised learning systems J. Syst. Archit. (IF 4.5) Pub Date : 2023-12-09 Yuteng Lu, Kaicheng Shao, Jia Zhao, Weidi Sun, Meng Sun
Unsupervised learning (UL) is one of the most important areas in artificial intelligence. UL systems are capable of learning patterns from unlabeled data and playing an increasingly critical role in many fields. Therefore, more and more attention has been paid to the security and stability of UL systems. Testing has achieved great success in ensuring the safety of traditional software systems and been
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LAG-based schedulability analysis for preemptive global EDF scheduling with dynamic cache allocation J. Syst. Archit. (IF 4.5) Pub Date : 2023-12-10 Yuhan Lin, Qingxu Deng, Meiling Han, Zhiwei Feng, Shumo Wang, Qize Peng
In recent years, the maturation of modern multicore processor technology and its increasing adoption in critical industrial domains have posed significant challenges for real-time systems, primarily due to contention for shared cache resources and the resulting uncertainty. To address this issue, contemporary processors employ cache partitioning techniques, enhancing temporal predictability by isolating
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Mean-field reinforcement learning for decentralized task offloading in vehicular edge computing J. Syst. Archit. (IF 4.5) Pub Date : 2023-12-07 Si Shen, Guojiang Shen, Xiaoxue Yang, Feng Xia, Hao Du, Xiangjie Kong
Vehicular Edge Computing (VEC) is a promising paradigm for providing low-latency and high-reliability services in the Internet of Vehicles (IoV). The increasing number of mobile devices and the diverse resource requirements of the growing IoV have resulted in a shift from centralized resource management to a decentralized approach. This shift offers improved fault tolerance, scalability, and privacy
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PED: Probabilistic Energy-efficient Deadline-aware scheduler for heterogeneous SoCs J. Syst. Archit. (IF 4.5) Pub Date : 2023-12-09 Xing Chen, Anish Krishnakumar, Umit Ogras, Chaitali Chakrabarti
Heterogeneous systems-on-chip (SoCs) integrate diverse cores with different performance and energy tradeoffs. Scheduling applications with soft deadline constraints is highly complex in such heterogeneous platforms, and the complexity is further exacerbated by the streaming jobs generated by applications from domains such as communication and radar systems. Existing deadline-aware schedulers typically
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SimplMM: A simplified and abstract multicore hardware model for large scale system software formal verification J. Syst. Archit. (IF 4.5) Pub Date : 2023-12-07 Jieung Kim, Ronghui Gu, Zhong Shao
This paper introduces SimplMM, a novel subsystem within the Certified Concurrent Abstraction Layers (CCAL) modular software verification framework, designed specifically for fine-grained concurrent software. SimplMM aims to provide a generic, practical, and realistic multicore machine model for verifying software within the CCAL framework. While formal multicore hardware semantics have seen extensive
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An efficient and secure certificateless aggregate signature scheme J. Syst. Archit. (IF 4.5) Pub Date : 2023-12-07 Ran Xu, Yanwei Zhou, Qiliang Yang, Kunwei Yang, Yu Han, Bo Yang, Zhe Xia
In recent years, the Internet of Things (IoT) has been developing rapidly and popularizing the world. Smart home is one of its important applications, the devices and household appliances are connected together through the network to provide intelligent services. However, malicious attacks often occur during the transmission of data information, resulting in data leakage or data changes. Therefore
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Vehicular network processor design for scalability & automation: Elastic Gateway SoC concept & builder J. Syst. Archit. (IF 4.5) Pub Date : 2023-12-01 Angela Gonzalez Mariño, Francesc Fons, Juan Manuel Moreno Arostegui
Application specific processors are now entering the world of automotive communications. Autonomous and connected vehicles bring with them new requirements in terms of reliability and performance that can no longer be met with traditional general purpose processing units. The challenge now is not only to design the right processor that can meet the requirements available today, but also to make this
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Online/offline attribute-based searchable encryption revised: Flexibility, security and efficiency J. Syst. Archit. (IF 4.5) Pub Date : 2023-12-05 Fei Meng
Attribute-based encryption with keyword search (ABKS) is a versatile public-key encryption system that supports access control and ciphertext retrieval. However, it often involves complex computations for ciphertext generation. To overcome this challenge, researchers have proposed several online/offline ABKS (OOABKS) schemes. These schemes optimize online ciphertext generation by pre-generating intermediate
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ThreadAbs: A template to build verified thread-local interfaces with software scheduler abstractions J. Syst. Archit. (IF 4.5) Pub Date : 2023-12-06 Jieung Kim, Jérémie Koenig, Hao Chen, Ronghui Gu, Zhong Shao
This paper presents ThreadAbs, an extension of the layer-based software formal verification toolkit CCAL (Gu et al., 2018). ThreadAbs is specifically designed to provide better expressiveness and proof management for thread abstraction in multithreaded libraries. Thread abstraction isolates the behavior of each thread from others when providing a top-level formal specification for software. Compared
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An efficient multi-data owner cooperative resource sharing scheme against key regeneration in edge computing J. Syst. Archit. (IF 4.5) Pub Date : 2023-12-03 Xue Yan Liu, Li Juan Huan, Wen Jing Li, Rui Rui Sun
In cloud storage, attribute-based keyword searchable encryption realizes multi-user fine-grained authorization access control and outsourcing data sharing. However, (1) resisting key regeneration is an urgent problem to be solved in practical applications of attribute-based keyword search; (2) the general attribute-based keyword search scheme ignores the application scenario where multiple data owners
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A portable blind cloud storage scheme against compromised servers J. Syst. Archit. (IF 4.5) Pub Date : 2023-11-27 Zhen Liu, Changsong Jiang, Chunxiang Xu
Applications (Apps) generate large amounts of data on users’ storage-limited local devices. To alleviate the burden of local storage, users can outsource their App-generated data to a remote cloud server. Secure data outsourcing needs data portability and blindness. The former enables users to access data from multiple devices using a single password, and the latter ensures data privacy against unauthorized
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Fine-grained adaptive parallelism for automotive systems through AMALTHEA and OpenMP J. Syst. Archit. (IF 4.5) Pub Date : 2023-11-29 Adrian Munera, Sara Royuela, Michael Pressler, Harald Mackamul, Dirk Ziegenbein, Eduardo Quiñones
The software development complexity of automotive systems has significantly increased during the last decade due to the latest Advanced Driving Assistance System (ADAS) functionalities. To effectively address this complexity, domain specific modeling languages (DSMLs) like AUTOSAR or an open-source system performance model for AUTOSAR-aligned systems, APP4MC, have become a common trend in the automotive
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Monintainer: An orchestration-independent extensible container-based monitoring solution for large clusters J. Syst. Archit. (IF 4.5) Pub Date : 2023-11-25 Miguel Correia, Wellington Oliveira, José Cecílio
Container virtualization has recently gained popularity due to its low performance and resource allocation overhead. The rise of this technology can be attributed to the advancement of cloud computing and the adoption of micro-services architecture. These new approaches offer a more efficient and fine-grained system design through the benefits of containerization, such as isolation, portability, and
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Systematic review on contract-based safety assurance and guidance for future research J. Syst. Archit. (IF 4.5) Pub Date : 2023-11-25 Samina Kanwal, Faiz Ul Muram, Muhammad Atif Javed
The safety requirements are often described via specifications called contracts. To verify that the system fulfils certain safety requirements, for instance, in the assume-guarantee contract specification, the key safety indicators are organized, so that if certain assumptions hold then the respective behaviour is guaranteed. Safety contracts provide a means of exposing potential incompatibilities
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Flexible and secure access control for EHR sharing based on blockchain J. Syst. Archit. (IF 4.5) Pub Date : 2023-11-25 Peng Li, Dehua Zhou, Haobin Ma, Junzuo Lai
With the rapid development of the healthcare industry, many Electronic Health Records (EHRs) have emerged in different healthcare centers. However, lots of personal medical data are stored directly in plaintext at a single healthcare center, which makes it suffer from the single point of failure and brings many security and privacy issues such as privacy information leakage or tampering. The combination
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A distributed message authentication scheme with reputation mechanism for Internet of Vehicles J. Syst. Archit. (IF 4.5) Pub Date : 2023-11-13 Xia Feng, Xiaofeng Wang, Kaiping Cui, Qingqing Xie, Liangmin Wang
Real-time and interactive traffic information sharing systems are crucial in the Internet of Vehicles (IoV) as they enable vehicles to make informed decisions, thereby improving the efficiency of intelligent transportation systems (ITS). Message authentication ensures the accuracy, integrity, and tamper-resistance of information in IoV. Existing schemes aim to achieve time-critical message authentication
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Guest editorial: Special issue on edge computing and machine learning-based sensor-cloud systems J. Syst. Archit. (IF 4.5) Pub Date : 2023-11-08 Chi Lin
Abstract not available
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Guest editorial: Special issue on Edge Computing Optimization and Security J. Syst. Archit. (IF 4.5) Pub Date : 2023-11-07 Meikang Qiu, Cheng Zhang
Abstract not available