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Physical Memory Attacks and a Memory Safe Management System for Memory Defense arXiv.cs.OS Pub Date : 2024-03-13 Alon Hillel-Tuch, Aspen Olmstead
Programming errors, defective hardware components (such as hard disk spindle defects), and environmental hazards can lead to invalid memory operations. In addition, less predictable forms of environmental stress, such as radiation, thermal influence, and energy fluctuations, can induce hardware faults. Sometimes, a soft error can occur instead of a complete failure, such as a bit-flip. The 'natural'
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Next4: Snapshots in Ext4 File System arXiv.cs.OS Pub Date : 2024-03-11 Aditya Dani, Shardul Mangade, Piyush Nimbalkar, Harshad Shirwadkar
The growing value of data as a strategic asset has given rise to the necessity of implementing reliable backup and recovery solutions in the most efficient and cost-effective manner. The data backup methods available today on linux are not effective enough, because while running, most of them block I/Os to guarantee data integrity. We propose and implement Next4 - file system based snapshot feature
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Virtuoso: An Open-Source, Comprehensive and Modular Simulation Framework for Virtual Memory Research arXiv.cs.OS Pub Date : 2024-03-07 Konstantinos Kanellopoulos, Konstantinos Sgouras, Onur Mutlu
Virtual memory is a cornerstone of modern computing systems.Introduced as one of the earliest instances of hardware-software co-design, VM facilitates programmer-transparent memory man agement, data sharing, process isolation and memory protection. Evaluating the efficiency of various virtual memory (VM) designs is crucial (i) given their significant impact on the system, including the CPU caches,
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Formal Definitions and Performance Comparison of Consistency Models for Parallel File Systems arXiv.cs.OS Pub Date : 2024-02-21 Chen Wang, Kathryn Mohror, Marc Snir
The semantics of HPC storage systems are defined by the consistency models to which they abide. Storage consistency models have been less studied than their counterparts in memory systems, with the exception of the POSIX standard and its strict consistency model. The use of POSIX consistency imposes a performance penalty that becomes more significant as the scale of parallel file systems increases
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Fight Hardware with Hardware: System-wide Detection and Mitigation of Side-Channel Attacks using Performance Counters arXiv.cs.OS Pub Date : 2024-02-18 Stefano Carnà, Serena Ferracci, Francesco Quaglia, Alessandro Pellegrini
We present a kernel-level infrastructure that allows system-wide detection of malicious applications attempting to exploit cache-based side-channel attacks to break the process confinement enforced by standard operating systems. This infrastructure relies on hardware performance counters to collect information at runtime from all applications running on the machine. High-level detection metrics are
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Everything You Always Wanted to Know About Storage Compressibility of Pre-Trained ML Models but Were Afraid to Ask arXiv.cs.OS Pub Date : 2024-02-20 Zhaoyuan Su, Ammar Ahmed, Zirui Wang, Ali Anwar, Yue Cheng
As the number of pre-trained machine learning (ML) models is growing exponentially, data reduction tools are not catching up. Existing data reduction techniques are not specifically designed for pre-trained model (PTM) dataset files. This is largely due to a lack of understanding of the patterns and characteristics of these datasets, especially those relevant to data reduction and compressibility.
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Enabling performance portability of data-parallel OpenMP applications on asymmetric multicore processors arXiv.cs.OS Pub Date : 2024-02-12 Juan Carlos Saez, Fernando Castro, Manuel Prieto-Matias
Asymmetric multicore processors (AMPs) couple high-performance big cores and low-power small cores with the same instruction-set architecture but different features, such as clock frequency or microarchitecture. Previous work has shown that asymmetric designs may deliver higher energy efficiency than symmetric multicores for diverse workloads. Despite their benefits, AMPs pose significant challenges
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Fiddler: CPU-GPU Orchestration for Fast Inference of Mixture-of-Experts Models arXiv.cs.OS Pub Date : 2024-02-10 Keisuke Kamahori, Yile Gu, Kan Zhu, Baris Kasikci
Large Language Models (LLMs) based on Mixture-of-Experts (MoE) architecture are showing promising performance on various tasks. However, running them on resource-constrained settings, where GPU memory resources are not abundant, is challenging due to huge model sizes. Existing systems that offload model weights to CPU memory suffer from the significant overhead of frequently moving data between CPU
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bypass4netns: Accelerating TCP/IP Communications in Rootless Containers arXiv.cs.OS Pub Date : 2024-02-01 Naoki Matsumoto, Akihiro Suda
"Rootless containers" is a concept to run the entire container runtimes and containers without the root privileges. It protects the host environment from attackers exploiting container runtime vulnerabilities. However, when rootless containers communicate with external endpoints, the network performance is low compared to rootful containers because of the overhead of rootless networking components
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Beyond Control: Exploring Novel File System Objects for Data-Only Attacks on Linux Systems arXiv.cs.OS Pub Date : 2024-01-31 Jinmeng Zhou, Jiayi Hu, Ziyue Pan, Jiaxun Zhu, Guoren Li, Wenbo Shen, Yulei Sui, Zhiyun Qian
The widespread deployment of control-flow integrity has propelled non-control data attacks into the mainstream. In the domain of OS kernel exploits, by corrupting critical non-control data, local attackers can directly gain root access or privilege escalation without hijacking the control flow. As a result, OS kernels have been restricting the availability of such non-control data. This forces attackers
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numaPTE: Managing Page-Tables and TLBs on NUMA Systems arXiv.cs.OS Pub Date : 2024-01-28 Bin Gao, Qingxuan Kang, Hao-Wei Tee, Kyle Timothy Ng Chu, Alireza Sanaee, Djordje Jevdjic
Memory management operations that modify page-tables, typically performed during memory allocation/deallocation, are infamous for their poor performance in highly threaded applications, largely due to process-wide TLB shootdowns that the OS must issue due to the lack of hardware support for TLB coherence. We study these operations in NUMA settings, where we observe up to 40x overhead for basic operations
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Characterizing Network Requirements for GPU API Remoting in AI Applications arXiv.cs.OS Pub Date : 2024-01-24 Tianxia Wang, Zhuofu Chen, Xingda Wei, Jinyu Gu, Rong Chen, Haibo Chen
GPU remoting is a promising technique for supporting AI applications. Networking plays a key role in enabling remoting. However, for efficient remoting, the network requirements in terms of latency and bandwidth are unknown. In this paper, we take a GPU-centric approach to derive the minimum latency and bandwidth requirements for GPU remoting, while ensuring no (or little) performance degradation for
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MATRYOSHKA: Non-Exclusive Memory Tiering via Transactional Page Migration arXiv.cs.OS Pub Date : 2024-01-24 Lingfeng Xiang, Zhen Lin, Weishu Deng, Hui Lu, Jia Rao, Yifan Yuan, Ren Wang
With the advent of byte-addressable memory devices, such as CXL memory, persistent memory, and storage-class memory, tiered memory systems have become a reality. Page migration is the de facto method within operating systems for managing tiered memory. It aims to bring hot data whenever possible into fast memory to optimize the performance of data accesses while using slow memory to accommodate data
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File System Aging arXiv.cs.OS Pub Date : 2024-01-16 Alex Conway, Ainesh Bakshi, Arghya Bhattacharya, Rory Bennett, Yizheng Jiao, Eric Knorr, Yang Zhan, Michael A. Bender, William Jannen, Rob Johnson, Bradley C. Kuszmaul, Donald E. Porter, Jun Yuan, Martin Farach-Colton
File systems must allocate space for files without knowing what will be added or removed in the future. Over the life of a file system, this may cause suboptimal file placement decisions that eventually lead to slower performance, or aging. Conventional wisdom suggests that file system aging is a solved problem in the common case; heuristics to avoid aging, such as colocating related files and data
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Dynamic Voltage and Frequency Scaling for Intermittent Computing arXiv.cs.OS Pub Date : 2024-01-15 Andrea Maioli, Kevin A. Quinones, Saad Ahmed, Muhammad H. Alizai, Luca Mottola
We present hardware/software techniques to intelligently regulate supply voltage and clock frequency of intermittently-computing devices. These devices rely on ambient energy harvesting to power their operation and small capacitors as energy buffers. Statically setting their clock frequency fails to capture the unique relations these devices expose between capacitor voltage, energy efficiency at a
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When eBPF Meets Machine Learning: On-the-fly OS Kernel Compartmentalization arXiv.cs.OS Pub Date : 2024-01-11 Zicheng Wang, Tiejin Chen, Qinrun Dai, Yueqi Chen, Hua Wei, Qingkai Zeng
Compartmentalization effectively prevents initial corruption from turning into a successful attack. This paper presents O2C, a pioneering system designed to enforce OS kernel compartmentalization on the fly. It not only provides immediate remediation for sudden threats but also maintains consistent system availability through the enforcement process. O2C is empowered by the newest advancements of the
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ALPC Is In Danger: ALPChecker Detects Spoofing and Blinding arXiv.cs.OS Pub Date : 2023-12-30 Anastasiia Kropova, Igor Korkin
The purpose of this study is to evaluate the possibility of implementing an attack on ALPC connection in the Windows operating system through the kernel without closing the connection covertly from programs and the operating system and to propose a method of protection against this type of attacks. Asynchronous Local Procedure Call technology (ALPC) is used in various Windows information protection
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Attention, Distillation, and Tabularization: Towards Practical Neural Network-Based Prefetching arXiv.cs.OS Pub Date : 2023-12-23 Pengmiao Zhang, Neelesh Gupta, Rajgopal Kannan, Viktor K. Prasanna
Attention-based Neural Networks (NN) have demonstrated their effectiveness in accurate memory access prediction, an essential step in data prefetching. However, the substantial computational overheads associated with these models result in high inference latency, limiting their feasibility as practical prefetchers. To close the gap, we propose a new approach based on tabularization that significantly
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PowerInfer: Fast Large Language Model Serving with a Consumer-grade GPU arXiv.cs.OS Pub Date : 2023-12-16 Yixin Song, Zeyu Mi, Haotong Xie, Haibo Chen
This paper introduces PowerInfer, a high-speed Large Language Model (LLM) inference engine on a personal computer (PC) equipped with a single consumer-grade GPU. The key underlying the design of PowerInfer is exploiting the high locality inherent in LLM inference, characterized by a power-law distribution in neuron activation. This distribution indicates that a small subset of neurons, termed hot neurons
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KEN: Kernel Extensions using Natural Language arXiv.cs.OS Pub Date : 2023-12-09 Yusheng Zheng, Yiwei Yang, Maolin Chen, Andrew Quinn
The ability to modify and extend an operating system is an important feature for improving a system's security, reliability, and performance. The extended Berkeley Packet Filters (eBPF) ecosystem has emerged as the standard mechanism for extending the Linux kernel and has recently been ported to Windows. eBPF programs inject new logic into the kernel that the system will execute before or after existing
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SYSFLOW: Efficient Execution Platform for IoT Devices arXiv.cs.OS Pub Date : 2023-12-08 Jun Lu, Zhenya Ma, Yinggang Gao, Ju Ren, Yaoxue Zhang
Traditional executable delivery models pose challenges for IoT devices with limited storage, necessitating the download of complete executables and dependencies. Network solutions like NFS, designed for data files, encounter high IO overhead for irregular access patterns. This paper introduces SYSFLOW, a lightweight network-based executable delivery system for IoT. SYSFLOW delivers on-demand, redirecting
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Lightweight Frequency-Based Tiering for CXL Memory Systems arXiv.cs.OS Pub Date : 2023-12-08 Kevin Song, Jiacheng Yang, Sihang Liu, Gennady Pekhimenko
Modern workloads are demanding increasingly larger memory capacity. Compute Express Link (CXL)-based memory tiering has emerged as a promising solution for addressing this trend by utilizing traditional DRAM alongside slow-tier CXL-memory devices in the same system. Unfortunately, most prior tiering systems are recency-based, which cannot accurately identify hot and cold pages, since a recently accessed
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Security, extensibility, and redundancy in the Metabolic Operating System arXiv.cs.OS Pub Date : 2023-12-11 Samuel T. King
People living with Type 1 Diabetes (T1D) lose the ability to produce insulin naturally. To compensate, they inject synthetic insulin. One common way to inject insulin is through automated insulin delivery systems, which use sensors to monitor their metabolic state and an insulin pump device to adjust insulin to adapt. In this paper, we present the Metabolic Operating System, a new automated insulin
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Stop Hiding The Sharp Knives: The WebAssembly Linux Interface arXiv.cs.OS Pub Date : 2023-12-06 Arjun Ramesh, Tianshu Huang, Ben L. Titzer, Anthony Rowe
WebAssembly is gaining popularity as a portable binary format targetable from many programming languages. With a well-specified low-level virtual instruction set, minimal memory footprint and many high-performance implementations, it has been successfully adopted for lightweight in-process memory sandboxing in many contexts. Despite these advantages, WebAssembly lacks many standard system interfaces
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Robust Resource Partitioning Approach for ARINC 653 RTOS arXiv.cs.OS Pub Date : 2023-12-03 Vitaly Cheptsov, Alexey Khoroshilov
Modern airborne operating systems implement the concept of robust time and resource partitioning imposed by the standards for aerospace and airborne-embedded software systems, such as ARINC 653. While these standards do provide a considerable amount of design choices in regards to resource partitioning on the architectural and API levels, such as isolated memory spaces between the application partitions
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MaxMem: Colocation and Performance for Big Data Applications on Tiered Main Memory Servers arXiv.cs.OS Pub Date : 2023-12-01 Amanda RaybuckThe University of Texas at Austin, Wei ZhangMicrosoft, Kayvan MansoorshahiThe University of Texas at Austin, Aditya K. KamathUniversity of Washington, Mattan ErezThe University of Texas at Austin, Simon PeterUniversity of Washington
We present MaxMem, a tiered main memory management system that aims to maximize Big Data application colocation and performance. MaxMem uses an application-agnostic and lightweight memory occupancy control mechanism based on fast memory miss ratios to provide application QoS under increasing colocation. By relying on memory access sampling and binning to quickly identify per-process memory heat gradients
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Cascade: A Platform for Delay-Sensitive Edge Intelligence arXiv.cs.OS Pub Date : 2023-11-29 Weijia Song, Thiago Garrett, Yuting Yang, Mingzhao Liu, Edward Tremel, Lorenzo Rosa, Andrea Merlina, Roman Vitenberg, Ken Birman
Interactive intelligent computing applications are increasingly prevalent, creating a need for AI/ML platforms optimized to reduce per-event latency while maintaining high throughput and efficient resource management. Yet many intelligent applications run on AI/ML platforms that optimize for high throughput even at the cost of high tail-latency. Cascade is a new AI/ML hosting platform intended to untangle
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Trace-enabled Timing Model Synthesis for ROS2-based Autonomous Applications arXiv.cs.OS Pub Date : 2023-11-22 Hazem Abaza, Debayan Roy, Shiqing Fan, Selma Saidi, Antonios Motakis
Autonomous applications are typically developed over Robot Operating System 2.0 (ROS2) even in time-critical systems like automotive. Recent years have seen increased interest in developing model-based timing analysis and schedule optimization approaches for ROS2-based applications. To complement these approaches, we propose a tracing and measurement framework to \emph{obtain timing models} of ROS2-based
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Telescope: Telemetry at Terabyte Scale arXiv.cs.OS Pub Date : 2023-11-17 Alan Nair, Sandeep Kumar, Aravinda Prasad, Andy Rudoff, Sreenivas Subramoney
Data-hungry applications that require terabytes of memory have become widespread in recent years. To meet the memory needs of these applications, data centers are embracing tiered memory architectures with near and far memory tiers. Precise, efficient, and timely identification of hot and cold data and their placement in appropriate tiers is critical for performance in such systems. Unfortunately,
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Memory Management Strategies for an Internet of Things System arXiv.cs.OS Pub Date : 2023-11-17 Ana-Maria Comeagă, Iuliana Marin
The rise of the Internet has brought about significant changes in our lives, and the rapid expansion of the Internet of Things (IoT) is poised to have an even more substantial impact by connecting a wide range of devices across various application domains. IoT devices, especially low-end ones, are constrained by limited memory and processing capabilities, necessitating efficient memory management within
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HAL 9000: Skynet's Risk Manager arXiv.cs.OS Pub Date : 2023-11-15 Tadeu Freitas, Mário Neto, Inês Dutra, João Soares, Manuel Correia, Rolando Martins
Intrusion Tolerant Systems (ITSs) are a necessary component for cyber-services/infrastructures. Additionally, as cyberattacks follow a multi-domain attack surface, a similar defensive approach should be applied, namely, the use of an evolving multi-disciplinary solution that combines ITS, cybersecurity and Artificial Intelligence (AI). With the increased popularity of AI solutions, due to Big Data
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Nahida: In-Band Distributed Tracing with eBPF arXiv.cs.OS Pub Date : 2023-11-15 Wanqi Yang, Pengfei Chen, Kai Liu, Huxing Zhang
Microservices are commonly used in modern cloud-native applications to achieve agility. However, the complexity of service dependencies in large-scale microservices systems can lead to anomaly propagation, making fault troubleshooting a challenge. To address this issue, distributed tracing systems have been proposed to trace complete request execution paths, enabling developers to troubleshoot anomalous
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bpftime: userspace eBPF Runtime for Uprobe, Syscall and Kernel-User Interactions arXiv.cs.OS Pub Date : 2023-11-14 Yusheng Zheng, Tong Yu, Yiwei Yang, Yanpeng Hu, XiaoZheng Lai, Andrew Quinn
In kernel-centric operations, the uprobe component of eBPF frequently encounters performance bottlenecks, largely attributed to the overheads borne by context switches. Transitioning eBPF operations to user space bypasses these hindrances, thereby optimizing performance. This also enhances configurability and obviates the necessity for root access or privileges for kernel eBPF, subsequently minimizing
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Laccolith: Hypervisor-Based Adversary Emulation with Anti-Detection arXiv.cs.OS Pub Date : 2023-11-14 Vittorio Orbinato, Marco Carlo Feliciano, Domenico Cotroneo, Roberto Natella
Advanced Persistent Threats (APTs) represent the most threatening form of attack nowadays since they can stay undetected for a long time. Adversary emulation is a proactive approach for preparing against these attacks. However, adversary emulation tools lack the anti-detection abilities of APTs. We introduce Laccolith, a hypervisor-based solution for adversary emulation with anti-detection to fill
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CARTOS: A Charging-Aware Real-Time Operating System for Intermittent Batteryless Devices arXiv.cs.OS Pub Date : 2023-11-13 Mohsen Karimi, Yidi Wang, Youngbin Kim, Yoojin Lim, Hyoseung Kim
This paper presents CARTOS, a charging-aware real-time operating system designed to enhance the functionality of intermittently-powered batteryless devices (IPDs) for various Internet of Things (IoT) applications. While IPDs offer significant advantages such as extended lifespan and operability in extreme environments, they pose unique challenges, including the need to ensure forward progress of program
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Pinky: A Modern Malware-oriented Dynamic Information Retrieval Tool arXiv.cs.OS Pub Date : 2023-11-06 Paul Irofti
We present here a reverse engineering tool that can be used for information retrieval and anti-malware techniques. Our main contribution is the design and implementation of an instrumentation framework aimed at providing insight on the emulation process. Sample emulation is achieved via translation of the binary code to an intermediate representation followed by compilation and execution. The design
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OpenBSD formal driver verification with SeL4 arXiv.cs.OS Pub Date : 2023-11-06 Adriana Nicolae, Paul Irofti, Ioana Leustean
The seL4 microkernel is currently the only kernel that has been fully formally verified. In general, the increased interest in ensuring the security of a kernel's code results from its important role in the entire operating system. One of the basic features of an operating system is that it abstracts the handling of devices. This abstraction is represented by device drivers - the software that manages
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A Survey of the Security Challenges and Requirements for IoT Operating Systems arXiv.cs.OS Pub Date : 2023-10-27 Alvi Jawad
The Internet of Things (IoT) is becoming an integral part of our modern lives as we converge towards a world surrounded by ubiquitous connectivity. The inherent complexity presented by the vast IoT ecosystem ends up in an insufficient understanding of individual system components and their interactions, leading to numerous security challenges. In order to create a secure IoT platform from the ground
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MOSEL: Inference Serving Using Dynamic Modality Selection arXiv.cs.OS Pub Date : 2023-10-27 Bodun Hu, Le Xu, Jeongyoon Moon, Neeraja J. Yadwadkar, Aditya Akella
Rapid advancements over the years have helped machine learning models reach previously hard-to-achieve goals, sometimes even exceeding human capabilities. However, to attain the desired accuracy, the model sizes and in turn their computational requirements have increased drastically. Thus, serving predictions from these models to meet any target latency and cost requirements of applications remains
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Optimizing Logical Execution Time Model for Both Determinism and Low Latency arXiv.cs.OS Pub Date : 2023-10-30 Sen Wang, Dong Li, Ashrarul H. Sifat, Shao-Yu Huang, Xuanliang Deng, Changhee Jung, Ryan Williams, Haibo Zeng
The Logical Execution Time (LET) programming model has recently received considerable attention, particularly because of its timing and dataflow determinism. In LET, task computation appears always to take the same amount of time (called the task's LET interval), and the task reads (resp. writes) at the beginning (resp. end) of the interval. Compared to other communication mechanisms, such as implicit
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Proving the Absence of Microarchitectural Timing Channels arXiv.cs.OS Pub Date : 2023-10-25 Scott BuckleyUNSW Sydney, Robert SisonUNSW SydneyUniversity of Melbourne, Nils WistoffETH Zürich, Curtis MillarUNSW Sydney, Toby MurrayUniversity of Melbourne, Gerwin KleinProofcraftUNSW Sydney, Gernot HeiserUNSW Sydney
Microarchitectural timing channels are a major threat to computer security. A set of OS mechanisms called time protection was recently proposed as a principled way of preventing information leakage through such channels and prototyped in the seL4 microkernel. We formalise time protection and the underlying hardware mechanisms in a way that allows linking them to the information-flow proofs that showed
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Snapshot: Fast, Userspace Crash Consistency for CXL and PM Using msync arXiv.cs.OS Pub Date : 2023-10-25 Suyash Mahar, Mingyao Shen, Terence Kelly, Steven Swanson
Crash consistency using persistent memory programming libraries requires programmers to use complex transactions and manual annotations. In contrast, the failure-atomic msync() (FAMS) interface is much simpler as it transparently tracks updates and guarantees that modified data is atomically durable on a call to the failure-atomic variant of msync(). However, FAMS suffers from several drawbacks, like
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Adaptive CPU Resource Allocation for Emulator in Kernel-based Virtual Machine arXiv.cs.OS Pub Date : 2023-10-23 Yecheng Yang, Pu Pang, Jiawen Wang, Quan Chen, Minyi Guo
The technologies of heterogeneous multi-core architectures, co-location, and virtualization can be used to reduce server power consumption and improve system utilization, which are three important technologies for data centers. This article explores the scheduling strategy of Emulator threads within virtual machine processes in a scenario of co-location of multiple virtual machines on heterogeneous
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GMEM: Generalized Memory Management for Peripheral Devices arXiv.cs.OS Pub Date : 2023-10-19 Weixi Zhu, Alan L. Cox, Scott Rixner
This paper presents GMEM, generalized memory management, for peripheral devices. GMEM provides OS support for centralized memory management of both CPU and devices. GMEM provides a high-level interface that decouples MMU-specific functions. Device drivers can thus attach themselves to a process's address space and let the OS take charge of their memory management. This eliminates the need for device
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Configuration Validation with Large Language Models arXiv.cs.OS Pub Date : 2023-10-15 Xinyu Lian, Yinfang Chen, Runxiang Cheng, Jie Huang, Parth Thakkar, Tianyin Xu
Misconfigurations are the major causes of software failures. Existing configuration validation techniques rely on manually written rules or test cases, which are expensive to implement and maintain, and are hard to be comprehensive. Leveraging machine learning (ML) and natural language processing (NLP) for configuration validation is considered a promising direction, but has been facing challenges
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Taking the Shortcut: Actively Incorporating the Virtual Memory Index of the OS to Hardware-Accelerate Database Indexing arXiv.cs.OS Pub Date : 2023-10-13 Felix Schuhknecht
Index structures often materialize one or multiple levels of explicit indirections (aka pointers) to allow for a quick traversal to the data of interest. Unfortunately, dereferencing a pointer to go from one level to the other is costly since additionally to following the address, it involves two address translations from virtual memory to physical memory under the hood. In the worst case, such an
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Towards a debuggable kernel design arXiv.cs.OS Pub Date : 2023-10-09 Chandrika Parimoo, Ashish Gupta
This paper describes what it means for a kernel to be debuggable and proposes a kernel design with debuggability in mind. We evaluate the proposed kernel design by comparing the iterations required in cyclic debugging for different classes of bugs in a vanilla monolithic kernel to a variant enhanced with our design rules for debuggability. We discuss the trade offs involved in designing a debuggable
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Prompt-to-OS (P2OS): Revolutionizing Operating Systems and Human-Computer Interaction with Integrated AI Generative Models arXiv.cs.OS Pub Date : 2023-10-07 Gabriele Tolomei, Cesare Campagnano, Fabrizio Silvestri, Giovanni Trappolini
In this paper, we present a groundbreaking paradigm for human-computer interaction that revolutionizes the traditional notion of an operating system. Within this innovative framework, user requests issued to the machine are handled by an interconnected ecosystem of generative AI models that seamlessly integrate with or even replace traditional software applications. At the core of this paradigm shift
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Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources arXiv.cs.OS Pub Date : 2023-10-06 Konstantinos Kanellopoulos, Hong Chul Nam, F. Nisa Bostanci, Rahul Bera, Mohammad Sadrosadati, Rakesh Kumar, Davide-Basilio Bartolini, Onur Mutlu
Address translation is a performance bottleneck in data-intensive workloads due to large datasets and irregular access patterns that lead to frequent high-latency page table walks (PTWs). PTWs can be reduced by using (i) large hardware TLBs or (ii) large software-managed TLBs. Unfortunately, both solutions have significant drawbacks: increased access latency, power and area (for hardware TLBs), and
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Motivating Next-Generation OS Physical Memory Management for Terabyte-Scale NVMMs arXiv.cs.OS Pub Date : 2023-10-05 Shivank Garg, Aravinda Prasad, Debadatta Mishra, Sreenivas Subramoney
Software managed byte-addressable hybrid memory systems consisting of DRAMs and NVMMs offer a lot of flexibility to design efficient large scale data processing applications. Operating systems (OS) play an important role in enabling the applications to realize the integrated benefits of DRAMs' low access latency and NVMMs' large capacity along with its persistent characteristics. In this paper, we
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Persistent Memory File Systems: A Survey arXiv.cs.OS Pub Date : 2023-10-04 Wiebe van Breukelen, Animesh Trivedi
Persistent Memory (PM) is non-volatile byte-addressable memory that offers read and write latencies in the order of magnitude smaller than flash storage, such as SSDs. This survey discusses how file systems address the most prominent challenges in the implementation of file systems for Persistent Memory. First, we discuss how the properties of Persistent Memory change file system design. Second, we
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Co-Optimizing Cache Partitioning and Multi-Core Task Scheduling: Exploit Cache Sensitivity or Not? arXiv.cs.OS Pub Date : 2023-10-04 Binqi Sun, Debayan Roy, Tomasz Kloda, Andrea Bastoni, Rodolfo Pellizzoni, Marco Caccamo
Cache partitioning techniques have been successfully adopted to mitigate interference among concurrently executing real-time tasks on multi-core processors. Considering that the execution time of a cache-sensitive task strongly depends on the cache available for it to use, co-optimizing cache partitioning and task allocation improves the system's schedulability. In this paper, we propose a hybrid multi-layer
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Case Study: Securing Embedded Linux Using CHERI arXiv.cs.OS Pub Date : 2023-10-02 Hesham Almatary
The current embedded Linux variant lacks security as it does not have or use MMU support. It does not also use MPUs as they do not fit with its software model because of the design drawbacks of MPUs (i.e., coarse-grained protection with fixed number of protected regions). We secure the existing embedded Linux version of the RISC-V port using CHERI. CHERI is hardware-software capability-based system
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The First Principles of Big Memory Systems arXiv.cs.OS Pub Date : 2023-09-30 Yu Hua
In this paper, we comprehensively analyze the vertical and horizontal extensions of existing memory hierarchy. The difference between memory and big memory is well reported. We present the state-of-the-art studies upon the big memory systems, together with design methodology and implementations. Persistence is the first principle of big memory systems. We further show the full-stack and moving persistence
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Loupe: Driving the Development of OS Compatibility Layers arXiv.cs.OS Pub Date : 2023-09-27 Hugo Lefeuvre, Gaulthier Gain, Vlad-Andrei Bădoiu, Daniel Dinca, Vlad-Radu Schiller, Costin Raiciu, Felipe Huici, Pierre Olivier
Supporting mainstream applications is fundamental for a new OS to have impact. It is generally achieved by developing a layer of compatibility allowing applications developed for a mainstream OS like Linux to run unmodified on the new OS. Building such a layer, as we show, results in large engineering inefficiencies due to the lack of efficient methods to precisely measure the OS features required
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Carbon Containers: A System-level Facility for Managing Application-level Carbon Emissions arXiv.cs.OS Pub Date : 2023-09-25 John Thiede, Noman Bashir, David Irwin, Prashant Shenoy
To reduce their environmental impact, cloud datacenters' are increasingly focused on optimizing applications' carbon-efficiency, or work done per mass of carbon emitted. To facilitate such optimizations, we present Carbon Containers, a simple system-level facility, which extends prior work on power containers, that automatically regulates applications' carbon emissions in response to variations in
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Expedited Data Transfers for Serverless Clouds arXiv.cs.OS Pub Date : 2023-09-26 Dmitrii Ustiugov, Shyam Jesalpura, Mert Bora Alper, Michal Baczun, Rustem Feyzkhanov, Edouard Bugnion, Boris Grot, Marios Kogias
Serverless computing has emerged as a popular cloud deployment paradigm. In serverless, the developers implement their application as a set of chained functions that form a workflow in which functions invoke each other. The cloud providers are responsible for automatically scaling the number of instances for each function on demand and forwarding the requests in a workflow to the appropriate function
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Virtuoso: High Resource Utilization and μs-scale Performance Isolation in a Shared Virtual Machine TCP Network Stack arXiv.cs.OS Pub Date : 2023-09-25 Matheus Stolet, Liam Arzola, Simon Peter, Antoine Kaufmann
Virtualization improves resource efficiency and ensures security and performance isolation for cloud applications. To that end, operators today use a layered architecture that runs a separate network stack instance in each VM and container connected to a separate virtual switch. Decoupling through layering reduces complexity, but induces performance and resource overheads that are at odds with increasing
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Software Compartmentalization Trade-Offs with Hardware Capabilities arXiv.cs.OS Pub Date : 2023-09-20 John Alistair Kressel, Hugo Lefeuvre, Pierre Olivier
Compartmentalization is a form of defensive software design in which an application is broken down into isolated but communicating components. Retrofitting compartmentalization into existing applications is often thought to be expensive from the engineering effort and performance overhead points of view. Still, recent years have seen proposals of compartmentalization methods with promises of low engineering
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A Discussion on Generalization in Next-Activity Prediction arXiv.cs.OS Pub Date : 2023-09-18 Luka Abb, Peter Pfeiffer, Peter Fettke, Jana-Rebecca Rehse
Next activity prediction aims to forecast the future behavior of running process instances. Recent publications in this field predominantly employ deep learning techniques and evaluate their prediction performance using publicly available event logs. This paper presents empirical evidence that calls into question the effectiveness of these current evaluation approaches. We show that there is an enormous