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New Compact Finite-Field Arithmetic Circuits Over GF(p) Based On Spiking Neural P Systems With Communication On Request Implemented in a Low Cost FPGA IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2024-03-13 José L. I. Rangel, Moises I. Arroyo, Eduardo Vázquez, Juan G. Avalos, Giovanny Sánchez
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A Graph Attention Network Approach to Partitioned Scheduling in Real-Time Systems IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2024-03-13 Seunghoon Lee, Jinkyu Lee
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RDMA-Based Sampling Port of ARINC-653 IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2024-03-07 Jong-Bin Lee, Sang-Jae Kim, Wook-Hee Kim, Hyun-Wook Jin
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Crypto-Coding Scheme via Dynamic Interleaver for New Communication Standards IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2024-02-28 Raúl Eduardo Lopresti, Jorge Castiñeira Moreira, Luciana De Micco
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IEEE Embedded Systems Letters Publication Information IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2024-02-28
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Real-Time Tomato Quality Assessment Using Hybrid CNN-SVM Model IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2024-02-27 Hassan Shabani Mputu, Ahmed-Abdel Mawgood, Atsushi Shimada, Mohammed S. Sayed
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FPGA Implementation of the Proposed DCNN Model for Detection of Tuberculosis and Pneumonia Using CXR Images IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2024-02-27 Prabhav Guddati, Shaswati Dash, Rajesh Kumar Tripathy
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High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2024-02-12 Mitul Sudhirkumar Nagar, Aditya Mathuriya, Sohan H. Patel, Pinalkumar J. Engineer
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LOTUS: A Scalable Framework to Lock Multi-Module Designs With One-Time Key and Self-Destructive Approaches IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2024-02-05 Mona Hashemi, Siamak Mohammadi, Trevor E. Carlson
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PROMISE: A Programmable Hardware Monitor for Secure Execution in Zero Trust Networks IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2024-01-16 Nikhilesh Singh, Shagnik Pal, Rainer Leupers, Farhad Merchant, Chester Rebeiro
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Middleton Class A Noise Median Estimator: FPGA and Software Implementation IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2024-01-15 L. A. Rabioglio, M. C. Cebedio, L. Arnone, L. De Micco, J. Castiñeira Moreira
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SoC-Based Implementation of 1D Convolutional Neural Network for 3-Channel ECG Arrhythmia Classification via HLS4ML IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2024-01-15 Feroz Ahmad, Saima Zafar
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An Area and Energy Efficient Serial-Multiplier IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2024-01-10 Mohd. Tasleem Khan, Jinti Hazarika
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Adaptive Kernel Merge and Fusion for Multi-Tenant Inference in Embedded GPUs IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2024-01-09 Jaebeom Jeon, Gunjae Koo, Myung Kuk Yoon, Yunho Oh
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Controlling a House’s Air-Conditioning Using Nonlinear Model Predictive Control IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2024-01-04 Bashra Kadhim Oleiwi, Ahmad H. Sabry
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Editorial IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-11-28 Preeti Ranjan Panda
Greetings from the IEEE Embedded Systems Letters (ESL) editorial board! As our term draws to a conclusion this year, it is time to reflect on the current status of the journal and the way forward.
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Design and Implementation of an NoC-Based Convolution Architecture With GEMM and Systolic Arrays IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-29 S. Ortega-Cisneros
Neural networks have been used for a long time for image detection and recognition applications due to their ability and efficiency in complex problem solving. Several researchers have chosen to design and develop hardware accelerators for the convolution layer due to the large computational expense consumed by this layer. For that reason, a system that performs indirect GEMM convolution is implemented
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NvMISC: Toward an FPGA-Based Emulation Platform for RISC-V and Nonvolatile Memories IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Yuankang Zhao, Salim Ullah, Siva Satyendra Sahoo, Akash Kumar
The emerging nonvolatile memories (NVMs), such as spin transfer torque random access memory (STT-RAM) and racetrack memory (RTM), offer a promising solution to satisfy the memory and performance requirements of modern applications. Compared to the commonly utilized volatile static random-access memories (SRAMs), the NVMs provide better capacity and energy efficiency. However, many of these NVMs are
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High-Flexibility Designs of Quantized Runtime Reconfigurable Multi-Precision Multipliers IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Yuhao Liu, Shubham Rai, Salim Ullah, Akash Kumar
Recent research widely explored the quantization schemes on hardware. However, for recent accelerators only supporting 8 bits quantization, such as Google TPU, the lower-precision inputs, such as 1/2-bit quantized neural network models in FINN, need to extend the data width to meet the hardware interface requirements. This conversion influences communication and computing efficiency. To improve the
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CNN Workloads Characterization and Integrated CPU–GPU DVFS Governors on Embedded Systems IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Meruyert Karzhaubayeva, Aidar Amangeldi, Jurn-Gyu Park
Dynamic power management (DPM) techniques on mobile systems are indispensable for deep learning (DL) inference optimization, which is mainly performed on battery-based mobile and/or embedded platforms with constrained resources. To this end, we characterize CNN workloads using object detection applications of YOLOv4/-tiny and YOLOv3/-tiny, and then propose integrated CPU–GPU DVFS governor policies
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No-Multiplication Deterministic Hyperdimensional Encoding for Resource-Constrained Devices IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Mehran Shoushtari Moghadam, Sercan Aygun, M. Hassan Najafi
Hyperdimensional vector processing is a nascent computing approach that mimics the brain structure and offers lightweight, robust, and efficient hardware solutions for different learning and cognitive tasks. For image recognition and classification, hyperdimensional computing (HDC) utilizes the intensity values of captured images and the positions of image pixels. Traditional HDC systems represent
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An Approximate Parallel Annealing Ising Machine for Solving Traveling Salesman Problems IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Qichao Tao, Tingting Zhang, Jie Han
Annealing-based Ising machines have emerged as high-performance solvers for combinatorial optimization problems (COPs). As a typical COP with constraints imposed on the solution, traveling salesman problems (TSPs) are difficult to solve using conventional methods. To address this challenge, we design an approximate parallel annealing Ising machine (APAIM) based on an improved parallel annealing algorithm
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Effects of Runtime Reconfiguration on PUFs Implemented as FPGA-Based Accelerators IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Hassan Nassar, Lars Bauer, Jörg Henkel
Physical unclonable functions (PUFs) are a handy security primitive for resource-constrained devices. They offer an alternative to the resource-intensive classical hash algorithms. Using the IC differences resulting from the fabrication process, PUFs give device-specific outputs (responses) when given the same inputs (challenges). Hence, without using a device-specific key, PUFs can generate device-specific
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LOCoCAT: Low-Overhead Classification of CAN Bus Attack Types IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Caio Batista de Melo, Nikil Dutt
Although research has shown vulnerabilities and shortcomings of the controller area network bus (CAN bus) and proposed alternatives, the CAN bus protocol is still the industry standard and present in most vehicles. Due to its vulnerability to potential intruders that can hinder execution or even take control of the vehicles, much work has focused on detecting intrusions on the CAN bus. However, most
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Vector-Based Dedicated Processor Architecture for Efficient Tracking in VSLAM Systems IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Dejian Li, Xi Feng, Chongfei Shen, Qi Chen, Lixin Yang, Sihai Qiu, Xin Jin, Meng Liu
This letter introduces a dedicated processor architecture, called MEGACORE, which leverages vector technology to enhance tracking performance in visual simultaneous localization and mapping (VSLAM) systems. By harnessing the inherent parallelism of vector processing and incorporating a floating point unit (FPU), MEGACORE achieves significant acceleration in the tracking task of VSLAM. Through careful
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Differentiable Slimming for Memory-Efficient Transformers IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Nikolay Penkov, Konstantinos Balaskas, Martin Rapp, Joerg Henkel
Transformer models are continuously achieving state-of-the-art performance on a wide range of benchmarks. To meet demanding performance targets, the number of model parameters is continuously increased. As a result, state-of-the-art Transformers require substantial computational resources prohibiting their deployment on consumer-grade hardware. In the literature, overparameterized Transformers are
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Hardware–Software Co-Optimization of Long-Latency Stochastic Computing IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Sercan Aygun, Lida Kouhalvandi, M. Hassan Najafi, Serdar Ozoguz, Ece Olcay Gunes
Stochastic computing (SC) is an emerging paradigm that offers hardware-efficient solutions for developing low-cost and noise-robust architectures. In SC, deterministic logic systems are employed along with bit-stream sources to process scalar values. However, using long bit-streams introduces challenges, such as increased latency and significant energy consumption. To address these issues, we present
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External Timed I/O Semantics Preserving Utilization Optimization for LET-Based Effect Chain IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Bo Zhang, Caixu Zhao, Xi Li
In real-time systems, it is essential to verify the end-to-end constraints that regulate the external input/output (I/O) semantics of the head and tail tasks in each effect chain during the design phase and preserve them during implementation. The logical execution time (LET) model has been adopted by the industry due to the predictability and composability of its timed behavior. However, during the
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Efficient Partial Weight Update Techniques for Lightweight On-Device Learning on Tiny Flash-Embedded MCUs IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Jisu Kwon, Daejin Park
Typical training procedures involve read and write operations for weight updates during backpropagation. However, on-device training on microcontroller units (MCUs) presents two challenges. First, the on-chip SRAM has insufficient capacity to store the weight. Second, the large flash memory, which has a constraint on write access, becomes necessary to accommodate the network for on-device training
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Optimized Local Path Planner Implementation for GPU-Accelerated Embedded Systems IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Filippo Muzzini, Nicola Capodieci, Federico Ramanzin, Paolo Burgio
Autonomous vehicles are latency-sensitive systems. The planning phase is a critical component of such systems, during which the in-vehicle compute platform is responsible for determining the future maneuvers that the vehicle will follow. In this letter, we present a GPU-accelerated optimized implementation of the Frenet Path Planner, a widely known path planning algorithm. Unlike the current state
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Flipping Bits Like a Pro: Precise Rowhammering on Embedded Devices IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Anandpreet Kaur, Pravin Srivastav, Bibhas Ghoshal
In this article, we introduce Flip-On-Chip, the first end-to-end tool that thoroughly examines the vulnerability of embedded DRAM against rowhammer bit flips. Our tool, Flip-On-Chip, utilizes DRAM address mapping information to efficiently and deterministically perform a double-sided RowHammer test. We evaluated Flip-On-Chip on two DRAM modules: 1) LPDDR2 and 2) LPDDR4. It is found that our proposed
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DynaFuse: Dynamic Fusion for Resource Efficient Multimodal Machine Learning Inference IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Hamidreza Alikhani, Anil Kanduri, Pasi Liljeberg, Amir M. Rahmani, Nikil Dutt
Multimodal machine learning (MMML) applications combine results from different modalities in the inference phase to improve prediction accuracy. Existing MMML fusion strategies use static modality weight assignment, based on the intrinsic value of sensor modalities determined during the training phase. However, input data perturbations in practical scenarios affect the intrinsic value of modalities
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Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin Patkar, Rolf Drechsler, Farhad Merchant
Memristor-based logic-in-memory (LiM) has become popular as a means to overcome the von Neumann bottleneck in traditional data-intensive computing. Recently, the memristor-aided logic (MAGIC) design style has gained immense traction for LiM due to its simplicity. However, understanding the energy distribution during the design of logic operations within the memristive memory is crucial in assessing
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Swift-CNN: Leveraging PCM Memory’s Fast Write Mode to Accelerate CNNs IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Lokesh Siddhu, Hassan Nassar, Lars Bauer, Christian Hakert, Nils Hölscher, Jian-Jia Chen, Joerg Henkel
Nonvolatile memories [especially phase change memories (PCMs)] offer scalability and higher density. However, reduced write performance has limited their use as main memory. Researchers have explored using the fast write mode available in PCM to alleviate the challenges. The fast write mode offers lower write latency and energy consumption. However, the fast-written data are retained for a limited
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FPGA Implementation of Modified SNOW 3G Stream Ciphers Using Fast and Resource Efficient Substitution Box IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-09-25 Sushree Sila P. Goswami, Gaurav Trivedi
Security plays a vital role in electronic communication, particularly in wireless networks like long term evolution (LTE), where safeguarding data and resources from malicious activities is crucial. Cryptographic algorithms are at the core of security mechanisms, ensuring the protection of sensitive information. While software implementations of these algorithms are relatively straightforward, they
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Respiratory Rate Estimation on Embedded System IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-05-24 Isabel Morales, Leonardo Martínez-Hornak, Alfredo Solari, Julián Oreggioni
We present the design, implementation, and results of an algorithm for respiratory rate (RR) estimation using respiratory-induced frequency, intensity, and amplitude variation calculated from the infrared (IR) channel of the SEN-15219 board for photoplethysmography (PPG) acquisition. First, the algorithm was developed in Python (on a PC) using synthetic signals and publicly available respiration and
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Hardware-in-the-Loop Simulation of an On-Board Energy-Driven Scheduling Algorithm for CubeSats IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-04-19 Vinicius Pimenta Bernardo, Laio Oriel Seman, Eduardo Augusto Bezerra, Brenda Fernandes Ribeiro
Optimizing energy consumption and management in small satellites includes evaluating the most efficient electrical power system architecture. The primary goal is to improve energy harvesting using solar panels and techniques, such as maximum power point tracking (MPPT). In this sense, in this letter, an integrated thermal-electrical nanosatellite framework is employed to test different strategies of
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Automatic Fecal Eggs Counting in Ruminants Using Xilinx DPU IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-04-18 Lucas Leiva, Bruno Constanzo, Martín Vázquez, Juan Manuel Toloza
Parasite control is vital in the cattle industry. Infection control is based on counting parasite eggs on samples obtained from animals, and processed later in laboratories by human technicians using optical microscopes. This traditional monitoring method affects the yield of production, delaying the start of treatment of infected animals. It also implies an additional cost of mobility of the veterinary
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Vector Accelerator Unit for Caravel IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-04-14 Emilio Isaac Baungarten-Leon, Susana Ortega-Cisneros, Uriel Jaramillo-Toral, Francisco J. Rodriguez-Navarrete, L. Pizano-Escalante, J. J. Raygoza Panduro
Caravel is an open-source project developed by Efabless for creating custom system-on-chips (SoCs). It includes the design of a configurable chip, development tools, and documentation. The Caravel SoC includes a RISC-V with the Instruction Set Architecture RV32I. One of the key features of Caravel is its open-source nature. In this letter, the vector accelerator unit for the Caravel SoC template is
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FloripaSat-2: An Open-Source Platform for CubeSats IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2023-03-21 Gabriel Mariano Marcelino, André Martins Pio de Mattos, João Cláudio Elsen Barcellos, Brenda Fernandes Ribeiro, Laio Oriel Seman, Edemar Morsch Filho, Eduardo Augusto Bezerra
This letter presents the FloripaSat-2 platform, an open-source service platform already on its second version, including, but not limited to, onboard data handling (OBDH), telemetry, tracking and command (TTC), and electrical power system (EPS) modules. The platform is conceived to be general purpose, i.e., easily adaptable for missions with different payloads and requirements. In this context, an
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Efficient Exploitation of Noise Leakage for Template Attack IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-12-15 Song Cheng, Hailong Zhang, Xiaobo Hu, Shunxian Gao, Huizhi Liu
Because of its strong leakage characterization ability and high-key-recovery efficiency, template attack (TA) is the strongest side-channel attack from the information-theoretic point-of-view. In light of this, TA can be used as a powerful tool to evaluate the security of a crypto device in real scenarios. In fact, by evaluating the key-recovery efficiency of TA, the security of a crypto device can
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An XSLT-Based Proposal to Ease Embedded Critical Systems Tools Implementation, Verification, Validation, Testing, and Certification Efforts IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-11-14 Santiago Germino, Martín N. Menéndez, Ariel Lutenberg
Implementing embedded critical system tools using general-purpose programming languages usually challenges conformance to relevant standards. This letter proposes implementing tools that manipulate a system model expressed in extensive markup language using the extensive stylesheet language transformations (XSLT) and related technologies playing specific roles in a particular sequence developed to
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Accelerating the Verification of Forward Error Correction Decoders by PCIe FPGA Cards IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-11-01 Daniel Suárez, Víctor Fernández, Héctor Posadas, Pablo Sánchez
Presilicon forward error correction (FEC) decoding hardware is typically designed using hardware description languages (HDLs). Its verification is a hard task due to its intrinsic tendency to correct errors. The generation and injection of millions of random inputs as well as the cross-checking of the corresponding outputs are highly recommended. Using HDL simulations for such work leads to prohibitive
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FPGA-Based Accelerator for AI-Toolbox Reinforcement Learning Library IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-10-31 Lucas Leiva, Jordina Torrents-Barrena, Martín Vázquez
In reinforcement learning (RL) an agent interacts with the environment based on sequential decisions. This agent receives a reward from the environment according to decisions and tries to maximize the reward. RL is used in several domains, such as production, autonomous driving, business management, education, games, healthcare, natural language processing, robotics, and among others. RL methodologies
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Design of Leading Zero Counters on FPGAs IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-10-28 Stefania Perri, Fanny Spagnolo, Fabio Frustaci, Pasquale Corsonello
This letter presents a novel leading zero counter (LZC) able to efficiently exploits the hardware resources available within state-of-the-art FPGA devices to achieve high-speed performances with limited energy consumption. Post-implementation results, obtained for operands bit-widths varying between 4- and 64-bit, demonstrate that the new design improves its direct competitors in terms of occupied
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Device-Free Human Motion Detection Using Single Link WiFi Channel Measurements for Building Energy Management IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-10-12 Anisha Natarajan, Vijayakumar Krishnasamy, Munesh Singh
Human motion is a vital parameter signaling indoor occupancy in occupant-centric building energy management systems. In this letter, a WiFi-based device-free sensing model employing ESP32—a low-cost embedded Internet of Things device, is proposed as a suitable retrofit for human motion sensing in new and existing buildings. A low complexity feature set derived from WiFi received signal strength indicator
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LoFFT: Low-Voltage FFT Using Lightweight Fault Detection for Energy Efficiency IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-10-10 Mehdi Safarpour, Olli Silvén
Operating at reduced voltage is an effective technique for improving the energy efficiency of computing. However, the approach is constrained by its exacerbated sensitivity to process, voltage, and temperature (PVT) variations, which under throughput constraints challenges finding the energy minimizing voltage-frequency operating point. Commonly utilized design approaches for adaptive voltage scaling
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Efficient Nonprofiled Side-Channel Attack Using Multi-Output Classification Neural Network IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-10-10 Van-Phuc Hoang, Ngoc-Tuan Do, Van Sang Doan
Differential deep learning analysis (DDLA) is the first deep-learning-based nonprofiled side-channel attack (SCA) on embedded systems. However, DDLA requires many training processes to distinguish the correct key. In this letter, we introduce a nonprofiled SCA technique using multi-output classification to mitigate the aforementioned issue. Specifically, a multi-output multilayer perceptron and a multi-output
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Multigateway Designation for Real-Time TSCH Networks Using Spectral Clustering and Centrality IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-09-23 Miguel Gutiérrez Gaitán, Diego Dujovne, Julián Zuñiga, Alejandro Figueroa, Luís Almeida
This letter proposes a multigateway designation framework to design real-time wireless sensor networks (WSNs) improving traffic schedulability, i.e., meeting the traffic time constraints. To this end, we resort to spectral clustering-unsupervised learning that allows defining arbitrary $k$ disjoint clusters without the knowledge of the node’s physical position. In each cluster, we use a centrality
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Embedded System for the Simultaneous Study of SAHS and Cardiac Arrhythmia IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-09-21 Carlos R. Dell’Aquila, Gabriel E. Cañadas, Eric Laciar
This letter presents a proposed embedded system for the simultaneous study of sleep apnea/hypopnea syndrome (SAHS) and related cardiac arrhythmias, which can affect about 1 billion people worldwide. Its objective is to become a tool to research the relational causes of these disruptions. It can record biomedical signals and vital parameters related to cardiac and respiratory activity commonly used
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A Novel Approach to Design Multiplexer Using Magnetic Quantum-Dot Cellular Automata IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-09-16 Vineet Jaiswal, Trailokya Nath Sasamal
Magnetic quantum-dot cellular automata (MQCA) is a recent technology in computation based on closely coupled ferromagnetic and antiferromagnetic dots; it is favorable as the fabrication issues arise day by day at the nanometer scale in CMOS technology. In this letter, first, we propose an MQCA-based 2:1 Multiplexer (Mux) using conventional horizontal and vertical approaches. In the next step, we propose
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Middleton’s Class A Noise Parameter Estimator IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-09-12 Lucas A. Rabioglio, María C. Cebedio, Jorge Castiñeira Moreira, Leonardo J. Arnone
For the development of communication systems that intend to be based on the cognitive radio paradigm, it is of vital importance to obtain the characteristics of the communication channel in a simple and fast way. This letter presents a simple method for estimating the parameters of the probability density function, corresponding to Middleton’s Class A noise. The method is presented, justified, and
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Regularized Differentiable Architecture Search IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-09-06 Lanfei Wang, Lingxi Xie, Kaili Zhao, Jun Guo, Qi Tian
Differentiable architecture search (DARTS) transforms architectural optimization into a super network optimization by stacking two cells (2 c.). However, repeatedly stacking two cells is a suboptimal operation since cells in different depths should be various. Besides, we find that the performance is slightly improved by increasing the number of searched cells (e.g., from 2 c. to 5 c.), but it leads
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Are You Sitting With Good Posture? Tracking the Position of the Legs via 2-D LiDAR IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-09-05 Francesco Pistolesi, Michele Baldassini, Beatrice Lazzerini
Desk workers spend long periods sitting with poor posture. This leads to back pain and musculoskeletal disorders. Current solutions to track posture use sensors or cameras that may make sitting uncomfortable and violate privacy. This letter presents a system that detects the leg position when sitting at a desk via 2-D light detection and ranging (LiDAR), and a support vector machine running on a Raspberry
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Table of Contents IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-08-29
Presents the table of contents for this issue of the publication.
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IEEE Embedded Systems Letters Publication Information IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-08-29
Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
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New Paradigm for Contactless Vital Sign Sensing Using UWB Radar and Hybrid Optical Wireless Communications IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-08-16 Wei-Wen Hu, Chia-Hung Chang, Geng-Xi Yang, Chih-Peng Li
This work proposes a new paradigm for contactless vital sign sensing that adopts an integrated ultrawideband (UWB) radar and hybrid optical wireless communication (OWC) technologies. The proposed system is composed of a sensor node and a receiver node. The sensor node is responsible for detecting continuous vital sign signals and then transmitting these signals via the hybrid OWC transmitters, which
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CAAM: Compressor-Based Adaptive Approximate Multiplier for Neural Network Applications IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-08-16 U. Anil Kumar, S Vignesh Bharadwaj, Avinash Bhat Pattaje, Suresh Nambi, Syed Ershad Ahmed
Approximate computing is an evolving paradigm that aims to improve the power, speed, and area in neural network applications that can tolerate errors up to a specific limit. This letter proposes a new multiplier architecture based on the algorithm that adapts the approximate compressor from the existing and proposed compressors’ set to reduce error in the respective partial product columns. Further
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Monitoring Software Execution Flow Through Power Consumption and Dynamic Time Warping IEEE Embed. Syst. Lett. (IF 1.6) Pub Date : 2022-08-08 Boris Vidal, Carlos Moreno, Sebastian Fischmeister, Gonzalo Carvajal
This letter presents a technique for nonintrusive code execution tracking using side-channel signals of power consumption. Using a nearest-neighbor classifier that integrates the dynamic time warping distance with information from the control flow graph, it is possible to identify executed basic blocks from a trace of power consumption that exhibits temporal distortions due to assembly-level artifacts