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Indoor localization using device sensors: A threat to privacy Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-03-06 Hitesh Verma, Smita Naval, Bala Prakasa Rao Killi, Vinod P.
The localization techniques used in today’s smartphone are mainly based on Global Positioning System (GPS). However, GPS Sensors cannot work properly under in-door and underground locations. Therefore, many applications utilize device sensors such as accelerometer, gyrometer, and magnetometer for indoor localization. In this paper, we present a misuse case of how device sensors can be used to exploit
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A light-weight neuromorphic controlling clock gating based multi-core cryptography platform Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-02-26 Pham-Khoi Dong, Khanh N. Dang, Duy-Anh Nguyen, Xuan-Tu Tran
While speeding up cryptography tasks can be accomplished by using a multi-core architecture to parallelize computation, one of the major challenges is optimizing power consumption. In principle, depending on the computation workload, individual cores can be turned off to save power during operation. However, too few active cores may lead to computational bottlenecks. In this work, we propose a novel
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MOSAIC: Maximizing ResOurce Sharing in Behavioral Application SpecIfic ProCessors Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-02-20 Qilin Si, Benjamin Carrion Schafer
This work presents a method that can quickly determine which hardware accelerators (HWaccs) should be mapped together onto an Application-Specific Instruction Set Processor (ASIP), such that the resources shared among them are maximized. This work in particular targets HWaccs generated from untimed behavioral descriptions for High-Level Synthesis (HLS). Although HLS is a single process synthesis method
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Design and evaluation of low power and area efficient approximate Booth multipliers for error tolerant applications Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-02-17 Vishal Gundavarapu, P. Gowtham, A. Anita Angeline, P. Sasipriya
Approximate computing is an innovative design methodology to reduce the design complexity with an improvement in power efficiency, performance and area by compromising on the requirement of accuracy. In this paper, 8-bit approximate Booth multipliers have been proposed based on the approximate Radix-4 modified Booth encoding algorithm and approximate compressors for partial product accumulation to
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A Real-time P-SFA hardware implementation of Deep Neural Networks using FPGA Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-02-17 Nour Elshahawy, Sandy A. Wasif, Maggie Mashaly, Eman Azab
Machine Learning (ML) algorithms, specifically Artificial Neural Networks (ANNs), have proved their effectiveness in solving complex problems in many different applications and multiple fields. This paper focuses on optimizing the activation function (AF) block of the NN hardware architecture. The AF block used is based on a probability-based sigmoid function approximation block (P-SFA) combined with
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Retraction notice to 'A machine learning based IoT for providing an intrusion detection system for security' [Microprocessors and Microsystems 82 (2021) 103741] Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-02-14 Dhanke Jyoti Atul, R. Kamalraj, G. Ramesh, K. Sakthidasan Sankaran, Sudhir Sharma, Syed Khasim
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Retraction notice to “FPGA implementation of low power and high speed image edge detection algorithm” [Microprocessors and Microsystems 75, 2020, 103053] Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-02-14 R. Menaka, R. Janarthanan, K. Deeba
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Retraction notice to ‘Virtual garden landscape planning based on FPGA and GIS platform’ [Microprocessors and Microsystems 79 (2020) 103314] Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-02-14 Xiaoxia Bai
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Retraction notice to 'An Improved Dynamic Process Neural Network Prediction Model Identification Method' [Microprocessors and Microsystems 80 (2021) 103573] Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-02-14 Shuran Lyu, Peng Liu, Lu Liu, Shuqi Ma, Tao Wang
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Flip-and-Patch: A fault-tolerant technique for on-chip memories of CNN accelerators at low supply voltage Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-02-10 Yamilka Toca-Díaz, Reynier Hernández Palacios, Rubén Gran Tejero, Alejandro Valero
Aggressively reducing the supply voltage () below the safe threshold voltage () can effectively lead to significant energy savings in digital circuits. However, operating at such low supply voltages poses challenges due to a high occurrence of permanent faults resulting from manufacturing process variations in current technology nodes.
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Non-intrusive study on FPGA of the SEU sensitivity on the COTS RISC-V VeeR EH1 soft processor from Western Digital Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-02-01 Daniel León, Juan Carlos Fabero, Juan A. Clemente
This article studies the ISA-extension and application-specific soft error sensitivity of the RISC-V VeeR EH1 commercial processor core from Western Digital. To this end, a modified VeeRwolf SoC from Chips Alliance was deployed in a Digilent Nexys-A7 FPGA. Then, a fault injection platform was created for injecting soft errors in all architectural and micro-architectural registers of the VeeR EH1, without
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A Novel Hybrid Fast Fourier Transform Processor in 5G+ and Bio Medical Applications Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-01-26 Priyadharsini R, Sasipriya S
To address the growing demand for real-time and high-performance signal processing, Field-Programmable Gate Array (FPGA) technology provides an influential platform for implementing Fast Fourier Transform (FFT) algorithms. The existing topologies of FFT processors encounters challenges related to high power consumption, limiting their viability for energy-efficient applications. In this research work
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Parametrized low-complexity hardware architecture of an H.264-based video encoder for FPGAs Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-01-13 Azam Tayyebi, Darrin Hanna, Bryant Jones
This paper presents a scalable, efficient, and real-time intra H.264 video encoder architecture designed for FPGAs. The system achieves up to 2.3 Gbit/s throughput using parallel and pipelined architecture described in VHDL. The architecture prioritizes hardware efficiency, with all modules optimized for minimal resource usage. It proposes a parametrized encoding system and a flexible design with varying
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FPGA-based remote target classification in hyperspectral imaging using multi-graph neural network Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-01-13 C Chellaswamy, M Muthu Manjula, B Ramasubramanian, A Sriram
Hyperspectral imagery (HSI) is widely used in remote sensing for target classification; however, its accurate classification remains challenging due to the scarcity of labeled data. Graph Neural Networks (GNNs) have emerged as a popular method for semi-supervised classification, attracting significant interest in the context of HSI analysis. Nevertheless, conventional GNN-based approaches often rely
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Edge-sorter: A hardware sorting engine for area & power constrained edge computing devices Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-01-05 Hakem Beitollahi, Marziye Pandi, Mostafa Moghaddas
In recent years, hardware sorters have been an attracted topic for researchers. Since hardware sorters play a crucial role in embedded systems, several attempts have been made to efficiently design and implement these sorters. Previous state-of-the-art hardware sorters are not suitable for embedded edge computing devices because they (1) consume high power, (2) occupy high area, (3) work for limited
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FPGA-friendly compact and efficient AES-like 8 × 8 S-box Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-01-08 Ahmet Malal, Cihangir Tezcan
One of the main layers in the Advanced Encryption Standard (AES) is the substitution layer, where an 8 × 8 S-Box is used 16 times. The substitution layer provides confusion and makes the algorithm resistant to cryptanalysis techniques. Therefore, the security of the algorithm is also highly dependent on this layer. However, the cost of implementing 8 × 8 S-Box on FPGA platforms is considerably higher
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Model-based, fully simulated, system-level power consumption estimation of IoT devices Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-01-08 Özen Özkaya, Berna Örs
Internet of things (IoT) gaining more importance due to its crucial role in pervasive computing and also Industry 4.0. Since the number of IoT devices is scaling up to multiple dozens of billions, the importance of energy efficiency is significantly increased. With the consideration of huge variety of IoT device hardware and software, a comprehensive model and estimation methodology on energy consumption
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Retraction notice to “real-time monitoring of the athlete's musculoskeletal health based on an embedded processor” [Microprocessors and Microsystems 81 (2021) 103742] Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-01-04 Rongjun Zhu
Abstract not available
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Retraction notice to “Business English visualization system based on video surveillance and the internet of things” [Microprocessors and Microsystems 80 (2021) 103639] Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-01-04 Xiaolei Qin
Abstract not available
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A Micro-architecture that supports the Fano–Elias encoding and a hardware accelerator for approximate membership queries Microprocess. Microsyst. (IF 2.6) Pub Date : 2024-01-03 Guy Even, Gabriel Marques Domingues
We present the first hardware design that supports operations over the Fano–Elias encoding (FE-encoding). Our design is a combinational circuit (i.e., single clock cycle) that supports insertions, deletions, and queries. FE-encoding allows one to store f binary strings, each of length ℓ+logm using a string that is m+f+fℓ bits long (rather than f(ℓ+logm)). The asymptotic gate-count of the circuit is
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H2-RAID: Improving the reliability of SSD RAID with unified SSD and HDD hybrid architecture Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-12-30 Jiarong Liu, Tianyu Wang, Xiaowei Chen, Chao Li, Zhaoyan Shen, Zhiyong Zhang
With the increasing development of SSD (Solid-State Drives) technology, SSD RAID (Redundant Arrays of Independent Disks) has been widely deployed in enterprise data centers. However, the inherent write endurance issue of SSD seriously affects the reliability of the array. Meanwhile, compared with conventional HDD-based RAID, SSD RAID exhibits very different failure characteristics, such as correlated
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Retraction notice to “Intelligent control for new topological structure of Z-Source inverter based on ARM” [Microprocessors and Microsystems 81 (2021) 103735] Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-12-29 Hailong Liu, Jiaona Chen
Abstract not available
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Retraction notice to “Searching and Learning English Translation Long Text Information Based on Heterogeneous Multiprocessors and Data Mining” [Microprocessors and Microsystems 82 (2021) 103895] Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-12-28 Xiaoping Shen, Runjuan Qin
Abstract not available
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Retraction notice to “Design of Embedded Digital Image Processing System Based on Zynq” [Microprocessors and Microsystems 83 (2021) 104005] Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-12-28 Jin Liu, Jie Feng
Abstract not available
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Retraction notice to ‘Medical IoT system platform and elderly patients’ femoral shaft fracture nursing’: [Microprocessors and Microsystems 82 (2021) 103868] Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-12-28 Weiwei Liu, Kun Yao
Abstract not available
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Retraction notice to “Design of Sino–Japanese cross border e-commerce platform based on FPGA and data mining ” [Microprocessors and Microsystems 80 (2021) 103360] Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-12-28 Lai Junfang, Cai Shan
Abstract not available
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Retraction notice to “An Improved Multilayer Perceptron Approach for Detecting Sugarcane Yield Production in IoT based Smart Agriculture” [Microprocessors and Microsystems 82 (2021) 103822] Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-12-28 Pengwen Wang, Behzad Aalipur Hafshejani, Daluyo Wang
Abstract not available
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Retraction notice to “Optimization of Storage Location Assignment in Automated Warehouse” [Microprocessors and Microsystems 80 (2021)103356] Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-12-28 Dong Yang, Yaohua Wu, Wenkai Ma
Abstract not available
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Advantages of unsupervised learning analysis methods in single-trace SCA attacks Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-12-28 Marcin Aftowicz, Ievgen Kabin, Zoya Dyka, Peter Langendoerfer
Machine learning techniques are commonly employed in the context of Side Channel Analysis attacks. The clustering algorithms can be successfully used as classifiers in single execution attacks against implementations of Elliptic Curve point multiplication known as kP operation. They can distinguish between the processing of ‘ones’ and ‘zeros’ during secret scalar processing in the binary kP algorithm
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Abeto: An automated benchmarking tool to manage heterogeneous IP core databases Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-12-27 Antonio J. Sánchez, Yubal Barrios, Lucana Santos, Roberto Sarmiento
System-level design makes use of building blocks, known as soft IP cores, to build complex developments. The usage of these IP cores allows to reduce design and verification time, and also to save costs. However, the use of third-party IP cores tends to present difficulties because of a lack of standardization in their organization, distribution and management, which derive in heterogeneous databases
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Implementation of survivability aware protocols in WSN for IoT applications using Contiki-OS and hardware testbed evaluation Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-12-27 Manu Elappila, Suchismita Chinara
The Internet of Things is a network of devices capable of operating and communicating individually and working for a specific goal collectively. Technologically, many networking and computing mechanisms have to work together with a common objective for the IoT applications to function, and many sensing and actuating devices have to get connected to the Internet backbone. The networks of resource-constrained
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A real-time SVM-based hardware accelerator for hyperspectral images classification in FPGA Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-12-27 Lucas Amilton Martins, Felipe Viel, Laio Oriel Seman, Eduardo Augusto Bezerra, Cesar Albenes Zeferino
Hyperspectral imaging can be conceptualized as a three-dimensional dataset of spectral information related to a particular landscape. Generally speaking, these are aerial photographs captured by Earth observation satellites. A useful analogy for a hyperspectral image is one of a cube formed with the image acquired along the X and Y axes and a third dimension of spectral bands of varying wavelengths
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Deep neural networks accelerators with focus on tensor processors Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-12-27 Hamidreza Bolhasani, Mohammad Marandinejad
The massive amount of data and the problem of processing them is one of the main challenges of the digital age, and the development of artificial intelligence and machine learning can be useful in solving this problem. Using deep neural networks to improve the efficiency of these two areas is a good solution. So far, several architectures have been introduced for data processing with the benefit of
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A novel low hardware configurable ring oscillator (CRO) PUF for lightweight security applications Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-12-23 Husam Kareem, Dmitriy Dunaev
Physical unclonable function (PUF) is a promising hardware security primitive that can generate a unique secret key peculiar to each chip by extracting the differences of non-reproducible manufacturing variations for the same implementations. Although there are several types of PUF designs and structures, ring oscillator (RO) PUF is one of the most prominent PUFs due to its straightforward implementation
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Experimental evaluation of RISC-V micro-architecture against fault injection attack Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-12-20 Maryam Esmaeilian, Hakem Beitollahi
Today, the use of embedded processors is increasing dramatically and they are used in all aspects from our daily life to security applications. Physical access to hardware has made the hardware security a major concern. Hardware attacks compromise the hardware security by physically accessing target devices. Among the available techniques for hardware attacks, Fault Injection Attacks (FIAs), such as
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Improved DWT and IDWT architectures for image compression Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-12-19 Ritesh Sur Chowdhury, Jhilam Jana, Sayan Tripathi, Jaydeb Bhaumik
In the recent era, a rapid development in the field of image processing has been observed. One of the important applications in image processing is compression. Several wavelet transform based image compression techniques have already been introduced. In this paper, Discrete Wavelet Transform (DWT) and Inverse Discrete Wavelet Transform (IDWT) based improved image compression and decompression techniques
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A novel partition strategy for efficient implementation of 3D Cellular Genetic Algorithms Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-12-09 Martín Letras, Alicia Morales-Reyes, René Cumplido, María-Guadalupe Martínez-Peñaloza, Claudia Feregrino-Uribe
Solving optimization problems while fulfilling real-time constraints requires high algorithmic and processing performance. Cellular Genetic Algorithms (cGAs) have been competitive at difficult single objective combinatorial and continuous domain problems. Moreover, it has been demonstrated that structural properties in cGAs, such as population topology dimension, local neighborhood configuration and
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Retraction notice to “FPGA implementation of PMSG based AC conversion using soft switching twin–mode PWM/FPGA control for high power IM application” [Microprocessors and Microsystems 75 (2020) 103044] Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-11-30 C. Kadhiravan, J. Baskaran
Abstract not available
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On the interactions between ILP and TLP with hardware transactional memory Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-11-19 Víctor Nicolás-Conesa, Rubén Titos-Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
Hardware implementations of Transactional Memory (HTM) are designed to facilitate efficient thread synchronization in parallel programs, encouraging the use of larger critical sections. By employing optimistic concurrency control to execute transactions speculatively, HTM systems promise to deliver the performance benefits typically associated with fine-grained locks. In doing so, HTM systems must
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Wiretap resisting and privacy preserving data exchange with physical layer security and blockchain based authentication in Internet of Vehicles Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-11-23 Qiao Liu, Qi Han, Guangze Luo, Jin Cao, Hui Li, Yong Wang
With the development of automobile industry technology, vehicles have greatly affected everyday life, work and other aspects. With the continuous innovation of sensor technology, computer technology, wireless communication technology, and GPS technology, the concept of Inter of Vehicles (IoV) has been widely regarded as the core technology to solve a series of problems. However, as a complexity network
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Retraction notice to the articles published in the special issue embedded system from “Microprocessors and Microsystems” Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-11-18
Abstract not available
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Vision-based robotics using open FPGAs Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-11-14 Felipe Machado, Rubén Nieto, Jesús Fernández-Conde, David Lobato, José M. Cañas
Robotics increasingly provides practical applications for society, such as manufacturing, autonomous driving, robot vacuum cleaners, robots in logistics, drones for inspection, etc. Typical requirements in this field are fast response time, low power consumption, parallelism, and flexibility. According to these features, FPGAs are a suitable computing substrate for robots. A few vendors have dominated
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Exploration of optimal functional Trojan-resistant hardware intellectual property (IP) core designs during high level synthesis Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-11-10 Anirban Sengupta, Aditya Anshul, Rahul Chaurasia
Hardware Trojans that have the capability to change the computed functional output in intellectual property (IP) cores, integrated into computing systems can be a vital reliability concern in the context of correct system operation. Therefore, determining an optimal Trojan-resistant hardware design architecture that considers multi-objective orthogonal parameters such as area and delay is crucial.
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Retraction notice to “Applications of internet of things (IOT) to improve the stability of a grid connected power system using interline power flow controller” [Microprocessors and Microsystems 76 (2020) 103038] Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-11-02 G. Radhakrishnan, V. Gopalakrishnan
Abstract not available
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GWalloc: A self-adaptive generational wear-aware allocator for non-volatile main memory Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-11-01 Ziwei Wang, Wei Li, Ziqi Shuai, Qingan Li
Phase Change Memory (PCM) is considered a promising replacement for DRAM due to its superior performance characteristics such as low leakage power, high integration density, byte addressability and non-volatility. However, PCM’s limited write endurance significantly hinders its wide application. For example, PCM wears out quickly with traditional dynamic memory allocation policy in embedded systems
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Retraction notice to “Application of Machine Learning and Big Data in Doubly Fed Induction Generator based Stability Analysis of Multi Machine System using Substantial Transformative Optimization Algorithm” [Microprocessors and Microsystems 73 (2020) 102971] Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-11-04 V. Subha Seethalakshmi, R. Karthigaivel, N. Vengadachalam, S. Selvakumaran
Abstract not available
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SmartDelta project: Automated quality assurance and optimization across product versions and variants Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-10-31 Mehrdad Saadatmand, Muhammad Abbas, Eduard Paul Enoiu, Bernd-Holger Schlingloff, Wasif Afzal, Benedikt Dornauer, Michael Felderer
Software systems are often built in increments with additional features or enhancements on top of existing products. This incremental development may result in the deterioration of certain quality aspects. In other words, the software can be considered an evolving entity emanating different quality characteristics as it gets updated over time with new features or deployed in different operational environments
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Experimental EMFI detection on a RISC-V core using the Trace Verifier solution Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-10-30 Anthony Zgheib, Olivier Potin, Jean-Baptiste Rigaud, Jean-Max Dutertre
Physical attacks are powerful threats that can cause changes in the execution behavior of a program. Control-Flow Integrity (CFI) is used to check the program’s flow execution, ensuring that it remains unaltered by these attacks. The RISC-V Trace Encoder (TE) provides valuable information about the user program’s execution path, and is used as part of a CFI solution. An enhanced version of the TE specifications
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Optimizing Network-on-Chip using metaheuristic algorithms: A comprehensive survey Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-10-29 Mohammad Masdari, Sultan Noman Qasem, Hao-Ting Pai
Network on Chip (NoC) is an interesting technology that benefits from several processing elements and the necessary communication facilities, to provide an answer to the ever-growing need for more processing power. Metaheuristic algorithms are important tools that have been used for dealing with various NP-hard problems in different domains. Such algorithms are also widely used in the NoC context by
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Designing an ultra-efficient Hamming code generator circuit for a secure nano-telecommunication network Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-10-27 Hongbo Xie, Yincheng Qi, Farah Qasim Ahmed Alyousuf
Communication links forming secure telecommunications networks rely on various technologies such as message switching, circuit switching, or packet switching to transmit messages and data. Hamming codes, a family of linear error-correcting codes, are commonly used in communication networks to detect and correct one-bit and two-bit errors. However, reducing power consumption, occupied area, and latency
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A framework for detection of cyber attacks by the classification of intrusion detection datasets Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-10-22 Durgesh Srivastava, Rajeshwar Singh, Chinmay Chakraborty, Sunil Kr. Maakar, Aaisha Makkar, Deepak Sinwar
Recognition of the consequence for advanced tools and techniques to secure the network infrastructure from the security risks has prompted the advancement of many machine learning-based intrusion detection strategies. However, it is a big challenge for the researchers to make improvements in an Intrusion Detection System with desired advantages and constraints. This paper has developed a proficient
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Fischer machine learning for mobile cloud computing in eHealth systems using blockchain mechanism Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-10-21 Nithya Rekha Sivakumar, Sara Abdelwahab Ghorashi, Nada Ahmed, Hafiza Elbadie Ahmed Elsrej, Shakila Basheer
The Electronic Healthcare (eHealth) systems are competent to ensure effective care engineering and intensified healthcare quality which are user-friendly cache and administration, in Electronic Health Records (EHRs). For secure EHRs of Mobile Cloud-based eHealth systems, ensuring high security and data privacy, Interplanetary File System in healthcare has traditionally been concentrated. However, there
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Echo state network implementation for chaotic time series prediction Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-10-14 Luis Gerardo de la Fraga, Brisbane Ovilla-Martínez, Esteban Tlelo-Cuautle
The implementation of an Echo State Neural Network (ESNN) for chaotic time series prediction is introduced. First, the ESNN is simulated using floating-point arithmetic and afterwards fixed-point arithmetic. The synthesis of the ESNN is done in a field-programmable gate array (FPGA), in which the activation function of the neurons’ outputs is a hyperbolic tangent one, and is approximated with a new
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3-D spatial correlation model for reducing the transmitting nodes in densely deployed WSN Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-10-14 Rajesh Kumar Garg, Surender Kumar Soni, S. Vimal, Gaurav Dhiman
In Wireless Sensor Networks, a large number of sensor nodes are distributed in the monitoring area to increase fault tolerance, coverage and communication range. In highly dense network, many nodes belong to common sensing region and record almost similar data of the event. Base station, however, can also identify the event features from data of a few representative nodes of the sensing region. The
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An Intrusion Detection Model using election-Based Feature Selection and K-NN Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-10-15 Mouaad Mohy-eddine, Azidine Guezzaz, Said Benkirane, Mourade Azrour
The Internet of Things (IoT) is a harmonized embedded object and sensor set. It is a target of intrusions, which leads to considering the security of the IoT environment. Considering their vital role in network security, intrusion detection systems (IDS) have received significant interest in the research community. IDS can be divided into anomaly intrusion detection systems (AIDS) and signature intrusion
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Artificial Intelligence Algorithm with ICD Coding Technology Guided by Embedded Electronic Medical Record System in Medical Record Information Management Microprocess. Microsyst. (IF 2.6) Pub Date : 2023-10-13 Cheng Wang, Chenlong Yao, Pengfei Chen, Jiamin Shi, Zhe Gu, Zheying Zhou
Objective The study aims to discuss the coding technology of international classification of diseases (ICD) and the application of embedded electronic medical record (EMR) system through clinical diagnosis selection and medical record information management by Artificial Intelligence Algorithm. Methods According to the embedded medical record input interface, the embedded medical record information