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A High-Performance Transparent Memory Data Encryption and Authentication Scheme Based on Ascon Cipher IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-14 Dongdong Xu, Xiang Wang, Qiang Hao, Jiqing Wang, Shuangjie Cui, Bo Liu
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Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-08 Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
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Trade-Offs in Design of Wide-Band Inverter-Based Amplifiers IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-06 Behdad Jamadi, Shiuh-Hua Wood Chiang, Armin Tajalli
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Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVs IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-05 Daijoon Hyun, Younggwang Jung, Youngsoo Shin
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A Single Ring-Oscillator-Based Test Structure for Timing Characterization of Dynamic Circuit IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-04 Haoming Zhang, Shuowei Li, Tetsuya Iizuka
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Layer-Sensitive Neural Processing Architecture for Error-Tolerant Applications IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-04 Zeju Li, Qinfan Wang, Zihan Zou, Qiao Shen, Na Xie, Hao Cai, Hao Zhang, Bo Liu
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Reconfigurable Stateful Logic Circuit With Cu/CuI/Pt Memristors for In-Memory Computing IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-03-04 Li Luo, Bochang Li, Lidan Wang, Jinpei Tan, Shukai Duan, Chunxiang Zhu
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Design of a High-Performance Iterative Barrett Modular Multiplier for Crypto Systems IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-29 Bo Zhang, Zeming Cheng, Massoud Pedram
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BSSE: Design Space Exploration on the BOOM With Semi-Supervised Learning IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-29 Xin Zheng, Mingjun Cheng, Jiasong Chen, Huaien Gao, Xiaoming Xiong, Shuting Cai
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A Hardware Acceleration of Maximum Likelihood Estimation Algorithm With Alternating Projection on FPGA IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-29 Zhuo Xuan, Shiwei Ren, Chengbo Xue, Guiyu Wang, Xiangnan Li
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A Neuromorphic Spiking Neural Network Using Time-to-First-Spike Coding Scheme and Analog Computing in Low-Leakage 8T SRAM IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-29 Chao-Yu Chen, Yan-Siou Dai, Hao-Chiao Hong
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A Reliable and Efficient Online Solution for Adaptive Voltage and Frequency Scaling on FPGAs IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-28 Wei Xiong, Jiacheng Cao, Yaozhang Liu, Jian Wang, Jinmei Lai, Miaoqing Huang
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Unveiling the Advantages of Full Coherency Architecture for FPSoC Systems IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-27 Enlai Li, Sharad Sinha, Wei Zhang
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Rowhammer Vulnerability of DRAMs in 3-D Integration IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-27 Eduardo Ortega, Jonti Talukdar, Woohyun Paik, Tyler Bletsch, Krishnendu Chakrabarty
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-26
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Memory-Efficient Multiplier-Less 2-D DWT Design Using Combined Convolution and Lifting Schemes for Wireless Visual Sensors IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-26 Basant Kumar Mohanty
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A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-26 Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Chua-Chin Wang
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Bit-Complemented Test Data to Replace the Tail of a Fault Coverage Curve IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-19 Irith Pomeranz
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A 24-Gb/s MIPI C-/D-PHY Receiver Bridge Chip With Phase Error Calibration Supporting FPGA-Based Frame Grabber IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-16 Changmin Song, Hoyong Jung, Kyoungseop Chang, Kwanglae Cho, Seungyong Yoon, Young-Chan Jang
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Reliable Hardware Watermarks for Deep Learning Systems IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-09 Joseph Franklin Clements, Yingjie Lao
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Design and FPGA Implementation of Grid-Scroll Hamiltonian Conservative Chaotic Flows With a Line Equilibrium IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-09 Musha Ji’e, Hongxin Peng, Shukai Duan, Lidan Wang, Fengqing Zhang, Dengwei Yan
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FSpGEMM: A Framework for Accelerating Sparse General Matrix–Matrix Multiplication Using Gustavson’s Algorithm on FPGAs IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-02 Erfan Bank Tavakoli, Michael Riera, Masudul Hassan Quraishi, Fengbo Ren
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Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-02 Licai Hao, Yaling Wang, Yunlong Liu, Shiyu Zhao, Xinyi Zhang, Yang Li, Wenjuan Lu, Chunyu Peng, Qiang Zhao, Yongliang Zhou, Chenghu Dai, Zhiting Lin, Xiulong Wu
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FEC-Aided Decision Feedback Blind Mismatch Calibration of TIADCs in Wireless Time-Varying Channel Environments IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-02-01 Haoyang Shen, Deepu John, Barry Cardiff
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FLNA: Flexibly Accelerating Feature Learning Networks for Large-Scale Point Clouds With Efficient Dataflow Decoupling IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-30 Dongxu Lyu, Zhenyu Li, Yuzhou Chen, Gang Wang, Weifeng He, Ningyi Xu, Guanghui He
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An Ultralow-Power Real-Time Machine Learning Based fNIRS Motion Artifacts Detection IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-30 Renas Ercan, Yunjia Xia, Yunyi Zhao, Rui Loureiro, Shufan Yang, Hubin Zhao
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Area-Efficient Iterative Logarithmic Approximate Multipliers for IEEE 754 and Posit Numbers IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-25 Sunwoong Kim, Cameron J. Norris, James I. Oelund, Rob A. Rutenbar
The IEEE 754 standard for floating-point (FP) arithmetic is widely used for real numbers. Recently, a variant called posit was proposed to improve the precision around 1 and −1. Since FP multiplication requires high computational complexity, various algorithmic approaches and hardware accelerator solutions have been explored. In this context, this article proposes a novel area-efficient logarithmic
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A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-25 Po-Yuan Chou, Wei-Ming Chen, Shen-Iuan Liu
A 16-Gb/s baud-rate clock and data recovery (CDR) circuit with a one-tap decision-feedback equalizer (DFE) and a wide frequency capture range (FCR) is presented. The proposed asymmetrical pattern-based phase detectors are used to achieve a wide FCR. This quarter-rate CDR circuit is fabricated in 40-nm CMOS technology and the active area is 0.1094 mm2. For a 16 Gb/s PRBS of 27–1, the power of the CDR
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems Society Information IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-22
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ALT: Area-Efficient and Low-Latency FPGA Design for Torus Fully Homomorphic Encryption IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-22 Xiao Hu, Zhihao Li, Zhongfeng Wang, Xianhui Lu
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A CMOS AFE Array With DC Input Current Cancellation for FMCW LiDAR IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-16 Xiaoxiao Zheng, Mao Ye, Zhiwei Li, Yao Li, Qiuwei Wang, Yiqiang Zhao
This article presents a low noise and wide linear dynamic 20-channel analog front-end (AFE) array for frequency-modulated continuous-wave (FMCW) light detection and ranging (LiDAR) system. Each channel of the AFE array mainly consists of a shunt feedback transimpedance amplifier (SF-TIA) with a dc cancellation loop (DCL), a post amplifier, and an output buffer. The DCL is proposed to eliminate the
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In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-12 Yajuan Hui, Qingzhen Li, Leimin Wang, Cheng Liu, Deming Zhang, Xiangshui Miao
In-memory computing represents an efficient paradigm for high-performance computing using crossbar arrays of emerging nonvolatile devices. While various techniques have emerged to implement Boolean logic in memory, the latency of arithmetic circuits, particularly multipliers, significantly increases with bit-width. In this work, we introduce an in-memory Wallace tree multiplier based on majority gates
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A Wideband Input Buffer Based on Cascade Complementary Source Follower IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-12 Dengquan Li, Tian Feng, Jiale Ding, Yi Shen, Shubin Liu, Zhangming Zhu
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Design of a Stochastic Computing Architecture for the Phansalkar Algorithm IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-10 Yongqiang Zhang, Jiao Qin, Jie Han, Guangjun Xie
Binarization plays a key role in image processing. Its performance directly affects the success of subsequent character segmentation and recognition. The Phansalkar algorithm performs excellent in processing heavily degraded or poor-quality images. However, this algorithm incurs significant hardware costs. In this article, efficient stochastic computing (SC) functions and an architecture are proposed
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Thermal Exploration of RSFQ Integrated Circuits IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-10 Ana Mitrovic, Eby G. Friedman
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Heterogeneous Monolithic 3-D IC Designs: Challenges, EDA Solutions, and Power, Performance, Cost Tradeoffs IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2024-01-04 Sai Pentapati, Sung-Kyu Lim
Monolithic 3-D (M3D) integrated circuits (ICs) introduce a new aspect to the physical design problem by stacking dies vertically. We introduce a novel heterogeneous design for M3D ICs, which utilizes different technology processes for each die. We also propose enhancements to the design flow and improved partitioning methods to support our suggested heterogeneous 3-D IC design. We perform 3-D partitioning
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A PPA Study for Heterogeneous 3-D IC Options: Monolithic, Hybrid Bonding, and Microbumping IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-12-28 Jinwoo Kim, Lingjun Zhu, Hakki Mert Torun, Madhavan Swaminathan, Sung Kyu Lim
In this article, we present three commercial-grade 3-D IC designs based on state-of-the-art design technologies, specifically microbumping (3-D die stacking), hybrid bonding (wafer-on-wafer bonding), and monolithic 3-D (M3D) ICs. To highlight tradeoffs present in these three designs, we perform analyses on power, performance, and area (PPA) and the clock tree. We also model the tier-to-tier interconnection
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GateLock: Input-Dependent Key-Based Locked Gates for SAT Resistant Logic Locking IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-12-28 Vijaypal Singh Rathor, Munesh Singh, Kshira Sagar Sahoo, Saraju P. Mohanty
Logic locking has become a robust method for reducing the risk of intellectual property (IP) piracy, overbuilding, and hardware Trojan threats throughout the lifespan of integrated circuits (ICs). Nevertheless, the majority of reported logic locking approaches are susceptible to satisfiability (SAT)-based attacks. The existing SAT-resistant logic locking methods provide a tradeoff between security
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Improving Radiation Reliability of SRAM-Based Physical Unclonable Function With Self-Healing and Pre-Irradiation Masking Techniques IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-12-28 Zhuojun Chen, Wenhao Yang, Jinghang Chen, Zujun Wang, Ding Ding
Physical unclonable function (PUF) is an innovative primitive used for key generation and device authentication, which has promising applications for resource-limited scenarios such as satellite communication. However, the reliability of traditional PUF circuits is low and the power consumption is high. Maintaining reliability also requires high costs, which limits its practical application. This article
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An RRAM-Based Computing-in-Memory Architecture and Its Application in Accelerating Transformer Inference IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-12-27 Zhaojun Lu, Xueyan Wang, Md Tanvir Arafin, Haoxiang Yang, Zhenglin Liu, Jiliang Zhang, Gang Qu
Deep neural network (DNN)-based transformer models have demonstrated remarkable performance in natural language processing (NLP) applications. Unfortunately, the unique scaled dot-product attention mechanism and intensive memory access pose a significant challenge during inference on power-constrained edge devices. One emerging solution to this challenge is computing-in-memory (CIM), which uses memory
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HETA: A Heterogeneous Temporal CGRA Modeling and Design Space Exploration via Bayesian Optimization IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-12-25 Yuan Dai, Jingyuan Li, Qilong Zhu, Yunhui Qiu, Yihan Hu, Wenbo Yin, Lingli Wang
Due to its high energy efficiency and flexibility, coarse-grained reconfigurable architecture (CGRA) has gained increasing attention. Temporal CGRA is a typical category of CGRA that supports single-cycle context switching and time-multiplexing hardware resources to perform spatial and temporal computations. Although multiple temporal CGRAs have been proposed, an architecture with rich design parameters
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HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-12-20 Shiwei Liu, Chen Mu, Hao Jiang, Yunzhengmao Wang, Jinshan Zhang, Feng Lin, Keji Zhou, Qi Liu, Chixiao Chen
Self-attention-based transformers have outperformed recurrent and convolutional neural networks (RNN/ CNNs) in many applications. Despite the effectiveness, calculating self-attention is prohibitively costly due to quadratic computation and memory requirements. To solve this challenge, this article proposes a hybrid analog-ReRAM and digital-SRAM in-memory computing accelerator (HARDSEA), a computing-in-memory
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A 0.4–1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-12-19 Rakesh Varma Rena, Raviteja Kammari, Vijay Shankar Pasupureddi
Subsampling down-conversion has not been a popular choice for mixer-first RF front-ends for two interdependent reasons. One, the subsampling down-conversion is inherently heterodyne in nature. Two, as a consequence to one, the passive mixer transparency property can not be exploited for providing impedance matching at the RF port by impedance translation. In this work, an eight-path quarter-rate subsampling
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Efficient Error Detection Schemes for ECSM Window Method Benchmarked on FPGAs IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-12-18 Kasra Ahmadi, Saeed Aghapour, Mehran Mozaffari Kermani, Reza Azarderakhsh
Elliptic curve scalar multiplication (ECSM) stands as a crucial subblock in elliptic curve cryptography (ECC), which represents the most widely used prequantum public key cryptography. Hardware constructions of cryptographic systems utilizing ECSM have been subject to permanent or transient errors. In cryptographic systems, it is important to validate the correctness of the underlying computation performed
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A Masked Hardware Accelerator for Feed-Forward Neural Networks With Fixed-Point Arithmetic IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-12-13 Manuel Brosch, Matthias Probst, Matthias Glaser, Georg Sigl
Neural network (NN) execution on resource-constrained edge devices is increasing. Commonly, hardware accelerators are introduced in small devices to support the execution of NNs. However, an attacker can often gain physical access to edge devices. Therefore, side-channel attacks are a potential threat to obtain valuable information about the NN. In order to keep the network secret and protect it from
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Compacting Side-Channel Measurements With Amplitude Peak Location Algorithm IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-12-12 Thai-Ha Tran, Duc-Thuan Dam, Ba-Anh Dao, Van-Phuc Hoang, Cong-Kha Pham, Trong-Thuc Hoang
Nowadays, cryptographic algorithms are widely used to build safety mechanisms for specific objects in security services. Nevertheless, these algorithms are implemented in the hardware or software of the physical devices. Consequently, attackers will exploit physical information leakages, such as the device’s power consumption, and use them to get secret keys. The correlation power analysis (CPA) attack
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IOLock: An Input/Output Locking Scheme for Protection Against Reverse Engineering Attacks IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-12-12 Christopher Vega, Patanjali SLPSK, Swarup Bhunia
Reverse engineering (RE) of hardware designs poses a significant threat to the modern distributed electronics supply chain. RE can be performed at both chip and printed circuit board (PCB) levels by using structural, functional, or combined analysis techniques. Recent studies on artificial intelligence (AI)-inspired RE techniques have seen a drastic increase in the effectiveness of such attacks. While
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FeFET Local Multiply and Global Accumulate Voltage-Sensing Computation-In-Memory Circuit Design for Neuromorphic Computing IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-12-06 Chihiro Matsui, Kasidit Toprasertpong, Shinichi Takagi, Ken Takeuchi
This work presents a design of voltage-sensing Computation-in-Memory (CiM) using ferroelectric FET (FeFET) in the point of device and circuit for neuromorphic computing. FeFET CiM with Local Multiply and Global Accumulate (LM-GA) operation works for multiply–accumulate (MAC) of artificial neural networks (ANNs) and integrate operation of spiking neural networks (SNNs). The high scalability and high
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Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-12-06 Sureum Choi, Daejin Han, Chanyeong Choi, Yeongkyo Seo
This article presents a layout-aware area optimization methodology for transposable spin-transfer torque magnetic random access memory (STT-MRAM). Although transposable STT-MRAM achieves high performance in processing-in-memory (PIM) systems for a spiking neural network (SNN), challenges in layout design and optimization remain owing to the vertical arrangement of its two wordlines (WLs). We propose
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An Area-Efficient, Conflict-Free, and Configurable Architecture for Accelerating NTT/INTT IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-12-05 Si-Huang Liu, Chia-Yi Kuo, Yan-Nan Mo, Tao Su
The Number Theoretic Transform (NTT) is a widely adopted method for accelerating polynomial multiplication in lattice-based cryptosystems. Consequently, numerous hardware accelerators have been developed to enhance the speed of the NTT algorithm. Area-Time Product (ATP) and configurability are critical metrics for evaluating these accelerators. ATP measures efficiency, while configurability ensures
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An Open-Loop VCO-ADC Based on a Linearized Current Control Technique IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-12-05 Mahsa Zareie, Kamal El-Sankary, Ezz El-Masry, Ximing Fu
This brief presents an open-loop current-controlled oscillator (CCO)-based analog-to-digital converter (ADC) intended for ultralow power direct digitizing micro-sensors readout applications. The proposed highly linearized pseudo-differential ${G}_{M}$ -stage mitigates the harmonic distortions induced by the tune circuit to the nonlinear transfer characteristic of the voltage-controlled oscillator (VCO)
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TrustGuard: Standalone FPGA-Based Security Monitoring Through Power Side-Channel IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-12-05 Tao Zhang, Mark Tehranipoor, Farimah Farahmandi
The Internet-of-Thing (IoT) era inspires a surge of networked embedded devices in the real world. However, cyber-attacks such as malware intrusions pose severe concerns about the security of the entire IoT space by hijacking the devices, altering the application’s execution, and/or causing a denial of services. Traditional operating-system-level and built-in hardware detection solutions either induce
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Reducing Power Dissipation in Memory Repair for High Fault Rates IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-11-27 Panagiota Papavramidou, Michael Nicolaidis
Nanometric scaling steadily increases failure rates, which are particularly acute for ultimate complementary metal–oxide–semiconductor (CMOS) and post-CMOS devices. We previously established an ECC-based method of memory repair that dramatically reduced the cost for high fault rates, and in this article, we establish a repair architecture that further reduces the power cost. Since CAMs are power hungry
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Enabling Voltage Over-Scaling in Multiplierless DSP Architectures via Algorithm-Hardware Co-Design IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-11-29 Charalampos Eleftheriadis, Georgios Chatzitsompanis, Georgios Karakonstantis
The design of low-power digital signal processing (DSP) architectures have gained a lot of attention due to their use in a variety of smart edge applications and portable devices. Recent efforts have focused on the replacement of power-hungry multipliers with various approximation frameworks such as multiplierless architectures that require only a few bit-shifts, additions and/or multiplexers when
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Variable Conversion Approach for Design Optimization of Low-Voltage Low-Pass Filters IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-11-29 Lucas Compassi-Severo, Tailize C. De-Oliveira, Paulo César C. de Aguirre, Wilhelmus Van Noije, Alessandro G. Girardi
This article describes a design optimization method based on variable conversion applied to low-voltage (LV) CMOS analog integrated circuits. For supply voltages in the range of 0.3 to 0.6 V, traditional design variables (e.g., transistor channel width $W$ and $\text {gm}/I_{D}$ ) are not suitable for exploring the design space, leading to impractical design solutions. We show that it is more efficient
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High-Performance ECC Scalar Multiplication Architecture Based on Comb Method and Low-Latency Window Recoding Algorithm IEEE Trans. Very Larg. Scale Integr. Syst. (IF 2.8) Pub Date : 2023-11-29 Jingqi Zhang, Zhiming Chen, Mingzhi Ma, Rongkun Jiang, Hongshuo Li, Weijiang Wang
Elliptic curve scalar multiplication (ECSM) is the essential operation in elliptic curve cryptography (ECC) for achieving high performance and security. We introduce a novel high-performance ECSM architecture over binary fields to meet the growing demand for performance and security. A low-latency window (LLW) recoding algorithm for hardware implementation is proposed to enhance the resistance toward