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  • ArmorAll
    ACM Trans. Archit. Code Optim. (IF 1.309) Pub Date : 2020-05-29
    Charu Kalra; Fritz Previlon; Norm Rubin; David Kaeli

    The vulnerability of GPUs to soft errors has become a first-class design concern as they are increasingly being used in accuracy-sensitive and safety-critical domains. Existing solutions used to enhance the reliability of GPUs come with significant overhead in terms of area, power, and/or performance. In this article, we propose ArmorAll, a light-weight, adaptive, selective, and portable software solution

    更新日期:2020-05-29
  • Dynamic Precision Autotuning with TAFFO
    ACM Trans. Archit. Code Optim. (IF 1.309) Pub Date : 2020-05-29
    Stefano Cherubin; Daniele Cattaneo; Michele Chiari; Giovanni Agosta

    Many classes of applications, both in the embedded and high performance domains, can trade off the accuracy of the computed results for computation performance. One way to achieve such a trade-off is precision tuning—that is, to modify the data types used for the computation by reducing the bit width, or by changing the representation from floating point to fixed point. We present a methodology for

    更新日期:2020-05-29
  • Runtime Design Space Exploration and Mapping of DCNNs for the Ultra-Low-Power Orlando SoC
    ACM Trans. Archit. Code Optim. (IF 1.309) Pub Date : 2020-05-29
    Ahmet Erdem; Cristina Silvano; Thomas Boesch; Andrea Carlo Ornstein; Surinder-Pal Singh; Giuseppe Desoli

    Recent trends in deep convolutional neural networks (DCNNs) impose hardware accelerators as a viable solution for computer vision and speech recognition. The Orlando SoC architecture from STMicroelectronics targets exactly this class of problems by integrating hardware-accelerated convolutional blocks together with DSPs and on-chip memory resources to enable energy-efficient designs of DCNNs. The main

    更新日期:2020-05-29
  • Reliability Analysis for Unreliable FSM Computations
    ACM Trans. Archit. Code Optim. (IF 1.309) Pub Date : 2020-05-29
    Amir Hossein Nodehi Sabet; Junqiao Qiu; Zhijia Zhao; Sriram Krishnamoorthy

    Finite State Machines (FSMs) are fundamental in both hardware design and software development. However, the reliability of FSM computations remains poorly understood. Existing reliability analyses are mainly designed for generic computations and are unaware of the special error tolerance characteristics in FSM computations. This work introduces RelyFSM -- a state-level reliability analysis framework

    更新日期:2020-05-29
  • Network Interface Architecture for Remote Indirect Memory Access (RIMA) in Datacenters
    ACM Trans. Archit. Code Optim. (IF 1.309) Pub Date : 2020-05-29
    Jiachen Xue; T. N. Vijaykumar; Mithuna Thottethodi

    Remote Direct Memory Access (RDMA) fabrics such as InfiniBand and Converged Ethernet report latency shorter by a factor of 50 than TCP. As such, RDMA is a potential replacement for TCP in datacenters (DCs) running low-latency applications, such as Web search and memcached. InfiniBand’s Shared Receive Queues (SRQs), which use two-sided send/recv verbs (i.e., channel semantics), reduce the amount of

    更新日期:2020-05-29
  • A Conflict-free Scheduler for High-performance Graph Processing on Multi-pipeline FPGAs
    ACM Trans. Archit. Code Optim. (IF 1.309) Pub Date : 2020-05-29
    Qinggang Wang; Long Zheng; Jieshan Zhao; Xiaofei Liao; Hai Jin; Jingling Xue

    FPGA-based graph processing accelerators are nowadays equipped with multiple pipelines for hardware acceleration of graph computations. However, their multi-pipeline efficiency can suffer greatly from the considerable overheads caused by the read/write conflicts in their on-chip BRAM from different pipelines, leading to significant performance degradation and poor scalability. In this article, we investigate

    更新日期:2020-05-29
  • SIMT-X
    ACM Trans. Archit. Code Optim. (IF 1.309) Pub Date : 2020-05-29
    Anita Tino; Caroline Collange; André Seznec

    This work introduces Single Instruction Multi-Thread Express (SIMT-X), a general-purpose Central Processing Unit (CPU) microarchitecture that enables Graphics Processing Units (GPUs)-style SIMT execution across multiple threads of the same program for high throughput, while retaining the latency benefits of out-of-order execution, and the programming convenience of homogeneous multi-thread processors

    更新日期:2020-05-29
  • Zeroploit: Exploiting Zero Valued Operands in Interactive Gaming Applications
    ACM Trans. Archit. Code Optim. (IF 1.309) Pub Date : 2020-04-09
    Ram Rangan; Mark Stephenson; Aditya Ukarande; Shyam Murthy; Virat Agarwal; Marc Blackstein

    In this paper, we present Zeroploit, a profile-guided transform for shader programs of gaming applications, that exploits dynamically zero valued register operands to optimize program execution through code specialization. With an offline value profiler and manually optimized shader programs, we demonstrate that Zeroploit is able to achieve an average speedup of 38.1% for targeted shader programs,

    更新日期:2020-04-09
  • GPU Fast Convolution via the Overlap-and-Save Method in Shared Memory
    ACM Trans. Archit. Code Optim. (IF 1.309) Pub Date : 2020-04-09
    Karel Adámek; Sofia Dimoudi; Mike Giles; Wesley Armour

    We present an implementation of the overlap-and-save method, a method for the convolution of very long signals with short response functions, which is tailored to GPUs. We have implemented several FFT algorithms (using the CUDA programming language) which exploit GPU shared memory, allowing for GPU accelerated convolution. We compare our implementation with an implementation of the overlap-and-save

    更新日期:2020-04-09
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