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  • IT Professional
    IEEE Micro (IF 2.570) Pub Date : 2020-03-24

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    更新日期:2020-03-27
  • MLPerf: An Industry Standard Benchmark Suite for Machine Learning Performance
    IEEE Micro (IF 2.570) Pub Date : 2020-02-18
    Peter Mattson; Vijay Janapa Reddi; Christine Cheng; Cody Coleman; Greg Diamos; David Kanter; Paulius Micikevicius; David Patterson; Guenther Schmuelling; Hanlin Tang; Gu-Yeon Wei; Carole-Jean Wu

    In this article, we describe the design choices behind MLPerf, a machine learning performance benchmark that has become an industry standard. The first two rounds of the MLPerf Training benchmark helped drive improvements to software-stack performance and scalability, showing a 1.3× speedup in the top 16-chip results despite higher quality targets and a 5.5× increase in system scale. The first round

    更新日期:2020-03-20
  • Habana Labs Purpose-Built AI Inference and Training Processor Architectures: Scaling AI Training Systems Using Standard Ethernet With Gaudi Processor
    IEEE Micro (IF 2.570) Pub Date : 2020-02-28
    Eitan Medina; Eran Dagan

    The growing computational requirements of AI applications are challenging today's general-purpose CPU and GPU architectures and driving the need for purpose-built, programmable AI solutions. Habana Labs designed its Goya processor to meet the high throughput/low latency demands of Inference workloads, and its Gaudi processor for throughput combined with massive scale up and scale out capability needed

    更新日期:2020-03-20
  • Compute Solution for Tesla's Full Self-Driving Computer
    IEEE Micro (IF 2.570) Pub Date : 2020-02-24
    Emil Talpes; Debjit Das Sarma; Ganesh Venkataramanan; Peter Bannon; Bill McGee; Benjamin Floering; Ankit Jalote; Christopher Hsiong; Sahil Arora; Atchyuth Gorti; Gagandeep S. Sachdev

    Tesla's full self-driving (FSD) computer is the world's first purpose-built computer for the highly demanding workloads of autonomous driving. It is based on a new System on a Chip (SoC) that integrates industry standard components such as CPUs, ISP, and GPU, together with our custom neural network accelerators. The FSD computer is capable of processing up to 2300 frames per second, a 21× improvement

    更新日期:2020-03-20
  • RTX on—The NVIDIA Turing GPU
    IEEE Micro (IF 2.570) Pub Date : 2020-02-04
    John Burgess

    NVIDIA's latest processor family, the Turing GPU, was designed to realize a vision for next-generation graphics combining rasterization, ray tracing, and deep learning. It includes fundamental advancements in several key areas: streaming multiprocessor efficiency, a Tensor Core for accelerated AI inferencing, and an RTCore for accelerated ray tracing. With these innovations, Turing unlocks both real-time

    更新日期:2020-03-20
  • The AMD “Zen 2” Processor
    IEEE Micro (IF 2.570) Pub Date : 2020-02-17
    David Suggs; Mahesh Subramony; Dan Bouvier

    The “Zen 2” processor is designed to meet the needs of diverse markets spanning server, desktop, mobile, and workstation. The core delivers significant performance and energy-efficiency improvements over “Zen” by microarchitectural changes including a new TAGE branch predictor, a double-size op cache, and a double-width floating-point unit. Building upon the core design, a modular chiplet approach

    更新日期:2020-03-20
  • The Arm Neoverse N1 Platform: Building Blocks for the Next-Gen Cloud-to-Edge Infrastructure SoC
    IEEE Micro (IF 2.570) Pub Date : 2020-02-07
    Andrea Pellegrini; Nigel Stephens; Magnus Bruce; Yasuo Ishii; Joseph Pusdesris; Abhishek Raja; Chris Abernathy; Jinson Koppanalil; Tushar Ringe; Ashok Tummala; Jamshed Jalal; Mark Werkheiser; Anitha Kona

    Recent years have seen an explosion of demand for high-performance, high-efficiency compute available at scale. This demand has skyrocketed with the move to the public cloud and 5G networking, where compute nodes must operate within strict latency constraints and power budgets. The Neoverse N1 platform is Arm's latest high end offering from a scalable portfolio of IP for high performance and energy

    更新日期:2020-03-20
  • TeraPHY: A Chiplet Technology for Low-Power, High-Bandwidth In-Package Optical I/O
    IEEE Micro (IF 2.570) Pub Date : 2020-02-24
    Mark Wade; Erik Anderson; Shahab Ardalan; Pavan Bhargava; Sidney Buchbinder; Michael L. Davenport; John Fini; Haiwei Lu; Chen Li; Roy Meade; Chandru Ramamurthy; Michael Rust; Forrest Sedgwick; Vladimir Stojanovic; Derek Van Orden; Chong Zhang; Chen Sun; Sergey Y. Shumarayev; Conor O'Keeffe; Tim T. Hoang; David Kehlet; Ravi V. Mahajan; Matthew T. Guzy; Allen Chan; Tina Tran

    In this article, we present TeraPHY, a monolithic electronic–photonic chiplet technology for low power and low latency, multi-Tb/s chip-to-chip communications. Integration of the TeraPHY optical technology with open source advanced interconnect bus interface enables communication between chips at board, rack, and row level at the energy and latency cost of in-package interconnect. This enables the

    更新日期:2020-03-20
  • Path2SL: Leveraging InfiniBand Resources to Reduce Head-of-Line Blocking in Fat Trees
    IEEE Micro (IF 2.570) Pub Date : 2019-10-25
    German Maglione-Mathey; Jesus Escudero-Sahuquillo; Pedro Javier Garcia; Francisco J. Quiles; José Duato

    The number of endnodes in high-performance computing and datacenter systems is constantly increasing. Hence, it is crucial to minimize the impact of network congestion to guarantee a suitable network performance. InfiniBand is a prominent interconnect technology that allows implementing efficient topologies and routing algorithms, as well as queuing schemes that reduce the head-of-line (HoL) blocking

    更新日期:2020-01-17
  • A Bunch-of-Wires (BoW) Interface for Interchiplet Communication
    IEEE Micro (IF 2.570) Pub Date : 2019-10-30
    Ramin Farjadrad; Mark Kuemerle; Bapi Vinnakota

    Multichiplet system-in-package designs have recently received a lot of attention as a mechanism to combat high SoC design costs and to economically manufacture large ASICs. These designs require low-power area-efficient off-die on-package die-to-die communication. Current technologies either extend on-die high-wire count buses using silicon interposers or off-package serial buses. The former approach

    更新日期:2020-01-17
  • Toward FPGA-Based HPC: Advancing Interconnect Technologies
    IEEE Micro (IF 2.570) Pub Date : 2019-10-31
    Joshua Lant; Javier Navaridas; Mikel Luján; John Goodacre

    HPC architects are currently facing myriad challenges from ever tighter power constraints and changing workload characteristics. In this article, we discuss the current state of FPGAs within HPC systems. Recent technological advances show that they are well placed for penetration into the HPC market. However, there are still a number of research problems to overcome; we address the requirements for

    更新日期:2020-01-17
  • Communication Profiling and Characterization of Deep-Learning Workloads on Clusters With High-Performance Interconnects
    IEEE Micro (IF 2.570) Pub Date : 2019-10-30
    Ammar Ahmad Awan; Arpan Jain; Ching-Hsiang Chu; Hari Subramoni; Dhableswar K. Panda

    Heterogeneous high-performance computing systems with GPUs are equipped with high-performance interconnects like InfiniBand, Omni-Path, PCIe, and NVLink. However, little exists in the literature that captures the performance impact of these interconnects on distributed deep learning (DL). In this article, we choose Horovod, a distributed training middleware, to analyze and profile various DNN training

    更新日期:2020-01-17
  • High-Quality Fault Resiliency in Fat Trees
    IEEE Micro (IF 2.570) Pub Date : 2019-10-30
    John Gliksberg; Antoine Capra; Alexandre Louvet; Pedro Javier García; Devan Sohier

    Coupling regular topologies with optimized routing algorithms is key in pushing the performance of interconnection networks of supercomputers. In this article, we present Dmodc, a fast deterministic routing algorithm for parallel generalized fat trees (PGFTs), which minimizes congestion risk even under massive network degradation caused by equipment failure. Dmodc computes forwarding tables with a

    更新日期:2020-01-17
  • A High-Throughput Network Processor Architecture for Latency-Critical Applications
    IEEE Micro (IF 2.570) Pub Date : 2019-12-10
    Sourav Roy; Arvind Kaushik; Rajkumar Agrawal; Joseph Gergen; Wim Rouwet; John Arends

    This article presents the recent advancements on the Advanced IO Processor (AIOP), a network processor architecture designed by NXP Semiconductors. The AIOP is a multicore accelerated computing architecture where each core is equipped with dedicated hardware for rapid task switching on every hardware accelerator call. A hardware preemption controller snoops on the accelerator completions and sends

    更新日期:2020-01-17
  • Warp: A Hardware Platform for Efficient Multimodal Sensing With Adaptive Approximation
    IEEE Micro (IF 2.570) Pub Date : 2020-01-14
    Phillip Stanley-Marbell; Martin Rinard

    In this article, we present Warp, the first open hardware platform designed explicitly to support research in approximate computing. Warp incorporates 21 sensors, computation, and circuit-level facilities designed explicitly to enable approximate computing research, in a 3.6 cm × 3.3 cm × 0.5 cm device. Warp supports a wide range of precision and accuracy versus power and performance tradeoffs.

    更新日期:2020-01-17
  • $\Delta$ΔNN: Power-Efficient Neural Network Acceleration Using Differential Weights
    IEEE Micro (IF 2.570) Pub Date : 2019-10-21
    Hoda Mahdiani; Alireza Khadem; Azam Ghanbari; Mehdi Modarressi; Farima Fattahi-Bayat; Masoud Daneshtalab

    The enormous and ever-increasing complexity of state-of-the-art neural networks has impeded the deployment of deep learning on resource-limited embedded and mobile devices. To reduce the complexity of neural networks, this article presents $\Delta$ΔNN, a power-efficient architecture that leverages a combination of the approximate value locality of neuron weights and algorithmic structure of neural

    更新日期:2020-01-17
  • AutoML for Architecting Efficient and Specialized Neural Networks
    IEEE Micro (IF 2.570) Pub Date : 2019-11-12
    Han Cai; Ji Lin; Yujun Lin; Zhijian Liu; Kuan Wang; Tianzhe Wang; Ligeng Zhu; Song Han

    Efficient deep learning inference requires algorithm and hardware codesign to enable specialization: we usually need to change the algorithm to reduce memory footprint and improve energy efficiency. However, the extra degree of freedom from the neural architecture design makes the design space much larger: it is not only about designing the hardware architecture but also codesigning the neural architecture

    更新日期:2020-01-17
  • In-Hardware Moving Compute to Data Model to Accelerate Thread Synchronization on Large Multicores
    IEEE Micro (IF 2.570) Pub Date : 2019-11-22
    Masab Ahmad; Halit Dogan; José A. Joao; Omer Khan

    In this article, the moving computation to data model (MC2D) is proposed to accelerate thread synchronization by pinning shared data to dedicated cores, and utilize in-hardware core-to-core messaging to communicate critical code execution. The MC2D model optimizes shared data locality by eliminating unnecessary data movement, and alleviates contended synchronization using nonblocking communication

    更新日期:2020-01-17
  • [Front cover]
    IEEE Micro (IF 2.570) Pub Date : 2019-11-07

    Presents the front cover for this issue of the publication.

    更新日期:2020-01-04
  • Keep Your Career Options Open
    IEEE Micro (IF 2.570) Pub Date : 2019-11-07

    Advertisement, IEEE.

    更新日期:2020-01-04
  • Masthead
    IEEE Micro (IF 2.570) Pub Date : 2019-11-07

    Provides a listing of current staff, committee members and society officers.

    更新日期:2020-01-04
  • Table of contents
    IEEE Micro (IF 2.570) Pub Date : 2019-11-07

    Presents the table of contents for this issue of this publication.

    更新日期:2020-01-04
  • 3-D Chips! Chips are Getting Denser and Taller Than Ever!!
    IEEE Micro (IF 2.570) Pub Date : 2019-11-07
    Lizy Kurian John

    Presents the introductory editorial for this issue of the publication.

    更新日期:2020-01-04
  • Security & Privacy
    IEEE Micro (IF 2.570) Pub Date : 2019-11-07

    Advertisement, IEEE.

    更新日期:2020-01-04
  • Going Vertical: The Future of Electronics
    IEEE Micro (IF 2.570) Pub Date : 2019-11-07
    Vijaykrishnan Narayanan

    This special issue provides an overview of the foundational advances enabling 3-D monolithic systems, reports on exciting new advances, and identifies open opportunities and challenges.

    更新日期:2020-01-04
  • Back-End-of-Line Compatible Transistors for Monolithic 3-D Integration
    IEEE Micro (IF 2.570) Pub Date : 2019-11-07
    Suman Datta; Sourav Dutta; Benjamin Grisafe; Jeff Smith; Srivatsa Srinivasa; Huacheng Ye

    The manufacturers of high-performance logic have been ardent champions of Moore's Law, which has resulted in exponential increase in aerial transistor density to 100 million transistors per square millimeter of silicon real estate. However, it is the memory chip makers who have taken the first step toward escaping the confines of scaling within the horizontal plane and have embraced the vertical or

    更新日期:2020-01-04
  • Monolithic 3-D Integration
    IEEE Micro (IF 2.570) Pub Date : 2019-11-07
    Mindy D. Bishop; H.-S. Philip Wong; Subhasish Mitra; Max M. Shulaker

    The demands of future applications in computing (from self-driving cars to bioinformatics) overwhelm the projected capabilities of current electronic systems. The need to process unprecedented amounts of loosely structured data is driving the push for ultradense and fine-grained integration of traditionally off-chip components (e.g., sensors, memories) with energy-efficient computation units-all within

    更新日期:2020-01-04
  • Recent Advances in Compute-in-Memory Support for SRAM Using Monolithic 3-D Integration
    IEEE Micro (IF 2.570) Pub Date : 2019-11-07
    Zhixiao Zhang; Xin Si; Srivatsa Srinivasa; Akshay Krishna Ramanathan; Meng-Fan Chang

    Computing-in-memory (CiM) is a popular design alternative to overcome the von Neumann bottleneck and improve the performance of artificial intelligence computing applications. Monolithic three-dimensional (M3D) technology is a promising solution to extend Moore's law through the development of CiM for data-intensive applications. In this article, we first discuss the motivation and challenges associated

    更新日期:2020-01-04
  • IEEE Computer Society Has You Covered!
    IEEE Micro (IF 2.570) Pub Date : 2019-11-07

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    更新日期:2020-01-04
  • A Logic-on-Memory Processor-System Design With Monolithic 3-D Technology
    IEEE Micro (IF 2.570) Pub Date : 2019-09-27
    Sai Pentapati; Lingjun Zhu; Lennart Bamberg; Da Eun Shim; Alberto García-Ortiz; Sung Kyu Lim

    In recent years, the size of transistors has been scaled down to a few nanometers and further shrinking will eventually reach the atomic scale. Monolithic three-dimensional (M3D) ICs use the third dimension for placement and routing, which helps reduce footprint and improve power and performance of circuits without relying on technology shrinking. This article explores the benefits of M3D ICs using

    更新日期:2020-01-04
  • Network-on-Chip Design Guidelines for Monolithic 3-D Integration
    IEEE Micro (IF 2.570) Pub Date : 2019-08-27
    Itir Akgun; Dylan Stow; Yuan Xie

    Monolithic three-dimensional (M3D) integration is viewed as a promising improvement over through-silicon-via-based 3-D integration due to its greater inter-tier connectivity, higher circuit density, and lower parasitic capacitance. With M3D integration, network-on-chip (NoC) communication fabric can benefit from reduced link distances and improved intra-router efficiency. However, the sequential fabrication

    更新日期:2020-01-04
  • Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning
    IEEE Micro (IF 2.570) Pub Date : 2019-11-08
    Shihui Yin; Yulhwa Kim; Xu Han; Hugh Barnaby; Shimeng Yu; Yandong Luo; Wangxin He; Xiaoyu Sun; Jae-Joon Kim; Jae-sun Seo

    Resistive RAM (RRAM) has been presented as a promising memory technology toward deep neural network (DNN) hardware design, with nonvolatility, high density, high ON/OFF ratio, and compatibility with logic process. However, prior RRAM works for DNNs have shown limitations on parallelism for in-memory computing, array efficiency with large peripheral circuits, multilevel analog operation, and demonstration

    更新日期:2020-01-04
  • Analyzing the Monolithic Integration of a ReRAM-Based Main Memory Into a CPU's Die
    IEEE Micro (IF 2.570) Pub Date : 2019-09-27
    Meenatchi Jagasivamani; Candace Walden; Devesh Singh; Luyi Kang; Shang Li; Mehdi Asnaashari; Sylvain Dubois; Bruce Jacob; Donald Yeung

    Nonvolatile memory, such as resistive RAM (ReRAM), is compatible with standard CMOS logic processes, allowing a sizable main memory system to be integrated into a CPU's die. ReRAM bitcells are fabricated within crosspoint subarrays that leave the bulk of transistors underneath the subarrays vacant. This permits placing the memory system over the CPU, improving area, parallelism, and power. Our work

    更新日期:2020-01-04
  • MEMTI: Optimizing On-Chip Nonvolatile Storage for Visual Multitask Inference at the Edge
    IEEE Micro (IF 2.570) Pub Date : 2019-10-04
    Marco Donato; Lillian Pentecost; David Brooks; Gu-Yeon Wei

    The combination of specialized hardware and embedded nonvolatile memories (eNVM) holds promise for energy-efficient deep neural network (DNN) inference at the edge. However, integrating DNN hardware accelerators with eNVMs still presents several challenges. Multilevel programming is desirable for achieving maximal storage density on chip, but the stochastic nature of eNVM writes makes them prone to

    更新日期:2020-01-04
  • Call for Papers: IEEE Transactions on Computers
    IEEE Micro (IF 2.570) Pub Date : 2019-11-07

    Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

    更新日期:2020-01-04
  • Antitrust in Three Acts
    IEEE Micro (IF 2.570) Pub Date : 2019-11-07
    Shane Greenstein

    Economic analysis frames the debates in U.S. antitrust, and as such, it resembles an Italian Opera. While the best economists in the world sing in front of judges, most of the audience loses something in the translation. Without a guide, it is easy for the spectacle to distract. Observers miss crucial details, and lose the plot. Which motivates the topic today: How does antitrust economics inform a

    更新日期:2020-01-04
  • IEEE COMPUTER SOCIETY
    IEEE Micro (IF 2.570) Pub Date : 2019-11-07

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    更新日期:2020-01-04
  • Computing Edge
    IEEE Micro (IF 2.570) Pub Date : 2019-11-07

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    更新日期:2020-01-04
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