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Reports on the top articles for 2020 from IEEE Micro.

Every year, IEEE Micro selects some of the most notable articles published in the previous year's computer architecture conferences to highlight in this Special Issue. In early 2021, the selection committee chose 12 articles to appear as “Top Picks” and an additional 12 deserving an “Honorable Mention” from among the 2020 conferences.

The superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising solution for the post-Moore era, thanks to the ultrafast and low-power switching characteristics of superconductor devices. Researchers have made tremendous efforts in various aspects, especially in device and circuit design. However, there has been little progress in designing a convincing SFQ-based architectural

We offer the first security analysis of cache compression, a promising architectural technique that is likely to appear in future mainstream processors. We find that cache compression has novel security implications because the compressibility of a cache line reveals information about its contents. Compressed caches introduce a new side channel that is especially insidious, as simply storing data transmits

Modern web services run across hundreds of thousands of servers in a data center, i.e., at hyperscale. With the end of Moore’s Law and Dennard scaling, successive server generations running these web services exhibit diminishing performance returns, resulting in architects adopting hardware customization. An important question arises: Which web service software operations are worth building custom

This article presents a framework, Genesis (genome analysis), to efficiently and flexibly accelerate generic data manipulation operations that have become performance bottlenecks in the genomic data processing pipeline utilizing FPGAs-as-a-service. Genesis conceptualizes genomic data as a very large relational database and uses extended SQL as a domain-specific language to construct data manipulation

Cloud computing has begun a transformation from using virtual machines to using containers. Containers are attractive because of their “build once, run anywhere” computing model and their minimal performance overhead. Cloud providers leverage the lean nature of containers to run hundreds of them or more on a few cores. Furthermore, containers enable the serverless paradigm, which involves the creation

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

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Cryogenic computing can achieve high performance and power efficiency by dramatically reducing the device’s leakage power and wire resistance at low temperatures. Recent advances in cryogenic computing focus on developing cryogenic-optimal cache and memory devices to overcome memory capacity, latency, and power walls. However, little research has been conducted to develop a cryogenic-optimal core architecture

Fault-tolerant quantum computing is required to execute many of the most promising quantum applications. In recent years, numerous error correcting codes, such as the surface code, have emerged which are well suited for current and future limited connectivity 2-D devices. We find quantum memory, particularly resonant cavities with transmon qubits arranged in a 2.5-D architecture, can efficiently implement

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The modern technology supply chain is highly complex. Throughout the various stages of design, manufacture, assembly, transport, and operation, a compute device is subject to tampering (malicious or otherwise). This exposes end users and consumers of compute devices to a variety of risks at varying levels of impact. Two potential technology solutions, which aim to provide transparency and insight into

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We are living through a monumental change in work. Experiments during the pandemic turned into regular operations, and have had a profound impact on perceptions of the viability of remote work. I do not lightly use the word “profound.” The trend reverses more than two centuries of separating the location of work and residences. That separation has deep roots, and reflects something fundamental about

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The IBM POWER10 processor represents the 10th generation of the POWER family of enterprise computing engines. It is built on a balance of computation and bandwidth, delivered by powerful processing cores and intrachip interconnect, respectively. Multiple system interconnect infrastructures support configurations with up to 16 processor chips and up to 1920 simultaneous threads of execution, as well

Marvell ThunderX3 is the third-generation Arm-based server processor from Marvell. This article describes the architecture of ThunderX3, going into details of core microarchitecture. ThunderX3 is distinctive among mainstream processors in supporting four SMT threads. The article describes the threading microarchitecture of ThunderX3 and highlights threading benefits. The article also touches on the

NVIDIA A100 Tensor Core GPU is NVIDIA's latest flagship GPU. It has been designed with many new innovative features to provide performance and capabilities for HPC, AI, and data analytics workloads. Feature enhancements include a Third-Generation Tensor Core, new asynchronous data movement and programming model, enhanced L2 cache, HBM2 DRAM, and third-generation NVIDIA NVLink I/O.

The Xbox Series X console, released in November 2020, contains a System on Chip (SoC) created in partnership with AMD. This article describes its architecture including the intelligence for input processing, rendering game graphics and audio, managing storage, user services, and security, all under a tiered operating system.

The Pensando distributed services architecture is designed to provide programmable security, network, storage, and visibility services to a data center landscape growing in scale and complexity. This domain-specific architecture combines P4 packet processing pipelines with embedded ARM CPUs and hardware offload engines in a tightly coupled, cache coherent interconnect. Millions of flows are tracked

The rapidly growing compute demands of AI necessitate the creation of new computing architectures and approaches. Tenstorrent designed its architecture (embodied in Grayskull and Wormhole devices) to tackle this challenge via two fundamental and synergistic approaches. The first is via compute-on-packets fabric that is built from ground up for massive scaleout. The second is the ability to execute

Five years ago, few would have predicted that a software company like Google would build its own computers. Nevertheless, Google has been deploying computers for machine learning (ML) training since 2017, powering key Google services. These Tensor Processing Units (TPUs) are composed of chips, systems, and software, all co-designed in-house. In this paper, we detail the circumstances that led to this

Video game consoles share many of the characteristics of an ideal device for use in enterprise deployments. In comparison to many desktop and notebook PCs available in the market, modern video game consoles are actually quite powerful and capable. They provide an excellent user experience with simple and intuitive setup and operation. At the heart of the design of many modern video game consoles is

Deep learning has sparked a renaissance in computer systems and architecture. Despite the breakneck pace of innovation, there is a crucial issue concerning the research and industry communities at large: how to enable neutral and useful performance assessment for machine learning (ML) software frameworks, ML hardware accelerators, and ML systems comprising both the software stack and the hardware.

Creating computing systems able to address our ever-increasing needs, especially as we reach the end of CMOS transistor scaling, will require truly novel methods of computing. However, the traditional logic abstractions and the digital design patterns we understand so well have coevolved with the hardware technology that has embodied them. As we look past CMOS, there is no reason to think that those

General matrix multiplication (GEMM) is pervasive in various domains, such as signal processing, computer vision, and machine learning. Conventional binary architectures for GEMM exhibit poor scalability in area and energy efficiency, due to the spatial nature of number representation and computing. On the contrary, unary computing processes data in temporal domain with extremely simple logic. However

Scalable server-grade nonvolatile RAM (NVRAM) DIMMs are commercially available with the release of Intel’s Optane DIMM. Recent studies on Optane DIMM-based systems unveil discrepant performance characteristics, compared with what many researchers thought before the product release. To thoroughly analyze the source of the discrepancy and facilitate real-NVRAM-aware system design, we develop an NVRAM

We are building HALO, a flexible ultralow-power processing architecture for implantable brain– computer interfaces (BCIs) that directly communicate with biological neurons in real time. This article discusses the rigid power, performance, and flexibility tradeoffs that BCI designers must balance, and how we overcome them via HALO’s palette of domain-specific hardware accelerators, general-purpose microcontroller

Today's field-programmable gate arrays (FPGAs) offer not only programmable acceleration capabilities but also include advanced features that are on-par with a mainstream processor platform. However, rather than being deployed as autonomous acceleration nodes, they are generally deployed as second-class citizens under the control of a standard processor platform. The configurable network protocol accelerator

In distributed deep learning (DL), collective communication algorithms, such as Allreduce, used to share training results between graphical processing units (GPUs) are an inevitable bottleneck. We hypothesize that a cache access latency occurred at every Allreduce is a significant bottleneck in the current computational systems with high-bandwidth interconnects for distributed DL. To reduce this frequency

PCI Express (PCIe) specification has been doubling the data rate every generation in a backward compatible manner every two to three years. PCIe 6.0 specification will adopt PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach of prior generations. A forward error correction (FEC) mechanism will offset the high BER of PAM-4. We propose a new flit-based approach with a lightweight, low-latency

Chiplet technology can significantly reduce the cost and time needed to develop custom high-performance silicon products. To realize a chiplet-based product, a die-to-die (D2D) network to interconnect the chiplets is required. Almost all of today's chiplet-based products use proprietary D2D interfaces. Industry has primarily paid attention to D2D PHYs. A design also requires logical information flow

The performance of lossy data-center networks (DCNs) may degrade due to packet dropping (and possible retransmission) under congestion. In this article, we propose and evaluate a solution to deal with congestion in lossy DCNs, based on the same approach as the dynamic virtual lanes technique, previously proposed for lossless DCNs. This approach consists of isolating congesting flows in special queues

Reliability and time-efficiency are two key elements to consider in network design. Commonly, each is measured per service—availability probability of a specific service, the latency of a specific service, and overall—system average reliability and average latency, considering the demand for every service. Intuitively, minimizing latency requires minimizing the number of network elements a service

Bunch of wires (BoW) is a new open die-to-die (D2D) interface that aims to gracefully tradeoff performance for design and packaging complexity across a wide range of process nodes. BoW performance can range from 320 Gb/s/mm with a simple design and packaging to 1+ Tb/s/mm with complex design and/or packaging. BoW directly enables heterogeneous integration, a primary advantage of chiplets. We discuss

Computation-intensive kernels, such as convolutions, matrix multiplication, and Fourier transform, are fundamental to edge-computing AI, signal processing, and cryptographic applications. Interleaved-multithreading (IMT) processor cores are interesting to pursue energy efficiency and low hardware cost for edge computing, yet they need hardware acceleration schemes to run heavy computational workloads

Data-parallel problems demand ever growing floating-point (FP) operations per second under tight area- and energy-efficiency constraints. In this work, we present Manticore, a general-purpose, ultraefficient chiplet-based architecture for data-parallel FP workloads. We have manufactured a prototype of the chiplet’s computational core in Globalfoundries 22FDX process and demonstrate more than 5x improvement

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This special issue of IEEE Micro aimed at publishing some of the most significant research that can highlight the trends in IC design in 2020 and provide directions for the future IC design era.

Machine learning applications, especially deep neural networks (DNNs) have seen ubiquitous use in computer vision, speech recognition, and robotics. However, the growing complexity of DNN models have necessitated efficient hardware implementations. The key compute primitives of DNNs are matrix vector multiplications, which lead to significant data movement between memory and processing units in today's

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

Recent advancements in machine learning provide an opportunity to transform chip design workflows. We review recent research applying techniques such as deep convolutional neural networks and graph-based neural networks in the areas of automatic design space exploration, power analysis, VLSI physical design, and analog design. We also present a future vision of an AI-assisted automated chip design

The future data-centric world demands edge intelligence (EI) - the ability to analyze data locally and to decide on a course of action autonomously. Challenges with Moore's Law scaling and limitations of von Neumann computing architectures are limiting the performance and energy efficiency of conventional electronics. Promising new discoveries of advanced CMOS-compatible HfO2-based ferroelectric devices

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

This special issue is a result of the enthusiastic response to the initiation of a new industry paper track at the 2020 International Symposium on Computer Architecture, as we could not accept all the great submissions to that track.1 We are excited to share our interest in commercial products with many industry colleagues who answered our call for papers.

IBM Z is both the oldest and among the most modern of computing platforms. Launched as S/360 in 1964, the mainframe became synonymous with large-scale computing for business and remains the workhorse of enterprise computing for businesses worldwide. Most of the world's largest banks, insurers, retailers, airlines, and enterprises from many other industries have IBM Z at the center of their IT infrastructure

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.