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This special issue of IEEE Micro aimed at publishing some of the most significant research that can highlight the trends in IC design in 2020 and provide directions for the future IC design era.

Machine learning applications, especially deep neural networks (DNNs) have seen ubiquitous use in computer vision, speech recognition, and robotics. However, the growing complexity of DNN models have necessitated efficient hardware implementations. The key compute primitives of DNNs are matrix vector multiplications, which lead to significant data movement between memory and processing units in today's

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

Recent advancements in machine learning provide an opportunity to transform chip design workflows. We review recent research applying techniques such as deep convolutional neural networks and graph-based neural networks in the areas of automatic design space exploration, power analysis, VLSI physical design, and analog design. We also present a future vision of an AI-assisted automated chip design

The future data-centric world demands edge intelligence (EI) - the ability to analyze data locally and to decide on a course of action autonomously. Challenges with Moore's Law scaling and limitations of von Neumann computing architectures are limiting the performance and energy efficiency of conventional electronics. Promising new discoveries of advanced CMOS-compatible HfO2-based ferroelectric devices

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

This special issue is a result of the enthusiastic response to the initiation of a new industry paper track at the 2020 International Symposium on Computer Architecture, as we could not accept all the great submissions to that track.1 We are excited to share our interest in commercial products with many industry colleagues who answered our call for papers.

IBM Z is both the oldest and among the most modern of computing platforms. Launched as S/360 in 1964, the mainframe became synonymous with large-scale computing for business and remains the workhorse of enterprise computing for businesses worldwide. Most of the world's largest banks, insurers, retailers, airlines, and enterprises from many other industries have IBM Z at the center of their IT infrastructure

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Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

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Reports on anti-trust issues that are likely to impact Facebook, Google/Alphabet, Apple, and Amazon.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

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Deep neural networks (DNNs) frequently contain far more weights, represented at a higher precision, than are required for the specific task, which they are trained to perform. Consequently, they can often be compressed using techniques such as weight pruning and quantization that reduce both the model size and inference time without appreciable loss in accuracy. However, finding the best compression

Deep Quantization (below eight bits) can significantly reduce the DNN computation and storage by decreasing the bitwidth of network encodings. However, without arduous manual effort, this deep quantization can lead to significant accuracy loss, leaving it in a position of questionable utility. We propose a systematic approach to tackle this problem, by automating the process of discovering the bitwidths

Genome analysis fundamentally starts with a process known as read mapping, where sequenced fragments of an organism's genome are compared against a reference genome. Read mapping is currently a major bottleneck in the entire genome analysis pipeline, because state-of-the-art genome sequencing technologies are able to sequence a genome much faster than the computational techniques employed to analyze

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The six papers in this special section focus on machine learning for computer systems. Specialized computer systems have driven the performance and capability of deep learning over the past decade.1 However, as machine learning models and systems improve, there is a growing opportunity to also use these models to improve how we design, architect, optimize, and automate computer systems and software

Machine learning has the potential to significantly improve systems, but only under certain conditions. We describe a taxonomy to help identify whether or not machine learning should be applied to particular systems problems, and which approaches are most promising. We believe that this taxonomy can help practitioners and researchers decide how to most effectively use machine learning in their systems

With increasingly complex neural network architectures and heterogeneous device characteristics, finding a reasonable graph partitioning and device placement strategy is challenging. There have been prior attempts at learned approaches for solving device placement, these approaches are computationally expensive, unable to handle large graphs consisting over 50000 nodes, and do not generalize well to

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

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The two articles in this special section focus on the intersection of systems and biology. Biological systems carry out computation and store information with efficiency levels and complexity that far exceeds those of synthetic computer systems. Consider, for example, that biological neural networks are estimated to offer at least four orders of magnitude with better ops/Joule than synthetic neural

Molecular manipulation and analysis are the cornerstone of life sciences. With the recent advances in molecular data storage and computing, it has become an increasingly exciting and viable alternative for the post-CMOS scaling era. Widespread use of molecular manipulation/analysis and data storage/computing requires a scalable and low-cost platform for hybrid molecular-electronics systems. This enables

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Amazon Web Services (AWS) took a fresh look at the network to provide consistently low latency required for supercomputing applications, while keeping the benefits of public cloud: scalability, elastic on-demand capacity, cost effectiveness, and fast adoption of newer CPUs and GPUs. We built a new network transport protocol, scalable reliable datagram (SRD), designed to utilize modern commodity multitenant

Among its various improvements over prior NVIDIA GPUs, the NVIDIA Turing GPU boasts of four key performance enhancements to effectively counter memory load-to-use stalls. First, reduced latency on L1 hits for global memory loads helps lower average memory lookup latency. Next, the ability to dynamically configure the L1 data RAM between cacheable memory and scratchpad or shared memory, enables driver

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The thirteen articles in this special section focus on agile and open source hardware. These papers cover variety of research topics related to fast, agile, and open hardware design, including methodologies, languages, abstractions, and simulators. As the benefits f traditional technology scaling, like Dennard Scaling and Moore’s Law, slow significantly, computer architecture is poised to enter a golden

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Continued improvement in computing efficiency requires functional specialization of hardware designs. Agile hardware design methodologies have been proposed to alleviate the increased design costs of custom silicon architectures, but their practice thus far has been accompanied with challenges in integration and validation of complex systems-on-a-chip (SoCs). We present the Chipyard framework, an integrated

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For five years, OpenPiton has provided hardware designs, build and verification scripts, and other infrastructure to enable efficient, detailed research into manycores and systems-on-chip. It enables open-source hardware development through its open design and support of a plethora of open simulators and CAD tools. OpenPiton was first designed to perform cutting-edge computer architecture research

The current trend for domain-specific architectures has led to renewed interest in research test chips to demonstrate new specialized hardware. Tapeouts also offer huge pedagogical value garnered from real hands-on exposure to the whole system stack. However, success with tapeouts requires hard-earned experience, and the design process is time consuming and fraught with challenges. Therefore, custom

Demanded by ever-evolving data processing algorithms, field-programmable gate arrays (FPGAs) have become essential components of modern computing systems, thanks to their reconfigurable and distributed computing capabilities. However, FPGAs are among the very few integrated chips that still require long development cycles and high human efforts, even for industrial vendors. In this article, we introduce

As the benefits of Moore's Law diminish, computing performance, and efficiency gains are increasingly achieved through specializing hardware to a domain of computation. However, this limits the hardware's generality and flexibility. Field-programmable gate arrays (FPGAs), microchips which can be reprogrammed to implement arbitrary digital circuits, enable the benefits of specialization while remaining

In this article, we present PyMTL3, a Python framework for open-source hardware modeling, generation, simulation, and verification. In addition to compelling benefits from using the Python language, PyMTL3 is designed to provide flexible, modular, and extensible workflows for both hardware designers and computer architects. PyMTL3 supports a seamless multilevel modeling environment and carefully designed

Synthesis and simulation of hardware design can take hours before results are available even for small changes. In contrast, software development embraced live programming to boost productivity. This article proposes LiveHD, an open-source incremental framework for hardware synthesis and simulation that provides feedback within seconds. Three principles for incremental design automation are presented

Domain-specific architectures have emerged as a promising solution to meet growing technology demands but with this comes an urgent need to improve hardware methodologies which often have long design cycles, rely on closed source and expensive tools, and have high nonrecurring engineering costs. In this article, we describe how our work developing PyRTL, an open source Python-based Hardware Development

Systolic array architecture is widely used in spatial hardware and well-suited for many tensor processing algorithms. Many systolic array architectures are implemented with high-level synthesis (HLS) design flow. However, existing HLS tools do not favor of modular and reusable design, which brings inefficiency for design iteration. In this article, we analyze the systolic array design space, and identify

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