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AMD Next Generation "Zen 4" Core and 4th Gen AMD EPYC™ Server CPUs IEEE Micro (IF 3.6) Pub Date : 2024-03-12 Ravi Bhargava, Kai Troester
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Quantifying CO2 Emission Reduction through Spatial Partitioning in Deep Learning Recommendation System Workloads IEEE Micro (IF 3.6) Pub Date : 2024-03-05 Andrei Bersatti, Euna Kim, Hyesoon Kim
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Special Issue on COOL Chips IEEE Micro (IF 3.6) Pub Date : 2024-02-13 Ryusuke Egawa, Yasutaka Wada
This introduction to the special issue on low-power, high speed chips (COOL chips) discusses state-of-the-art COOL chips and the challenges facing researchers. It introduces four articles exploring different solutions for reducing power consumption and enhancing chip performance.
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Computing With COOL Chips IEEE Micro (IF 3.6) Pub Date : 2024-02-13 Hsien-Hsin S. Lee
In this issue, IEEE MICRO welcomes the newly inaugurated Editor-in-Chief Dr. Hsien-Hsin Sean Lee and introduces the Special Issue on COOL chips for the state-of-the-art in low-power design for computing.
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Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies—Part VIII: Patent Families IEEE Micro (IF 3.6) Pub Date : 2024-02-13 Joshua J. Yi
This article is the next article in the series on the patenting behavior and characteristics of computer architecture companies. This article analyzes the characteristics for patent families.
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After the Gold Rush IEEE Micro (IF 3.6) Pub Date : 2024-02-13 Shane Greenstein
What determines market prospects during and after a commercial gold rush, such as the boom presently taking place in commercial generative AI? Many firms face similar technical challenges and commercial risks, and the resolution of one firm’s challenge correlates with that of another. That provides a way of cataloging risks, and the general prospects of some categories of firms, even though it does
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High-Speed Data Communication with Advanced Networks in Large Language Model Training IEEE Micro (IF 3.6) Pub Date : 2024-01-30 Liuyao Dai, Hao Qi, Weicong Chen, Xiaoyi Lu
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High Performance Cooling for Power Electronics Via Electrochemical Additive Manufacturing IEEE Micro (IF 3.6) Pub Date : 2024-01-30 Ian Winfield, Tim Ouradnik, Joseph Madril, Michael Matthews, Guillermo Romero
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Improving key-value cache performance with heterogeneous memory tiering: A case study of CXL-based memory expansion IEEE Micro (IF 3.6) Pub Date : 2024-01-26 KyungSoo Lee, Sohyun Kim, Joohee Lee, Donguk Moon, Rakie Kim, Honggyu Kim, Hyeongtak Ji, Yunjeong Mun, Youngpyo Joo
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Advancing TinyMLOps: Robust Model Updates in the Internet of Intelligent Vehicles IEEE Micro (IF 3.6) Pub Date : 2024-01-17 Thommas K. S. Flores, Ivanovitch Silva, Mariana B. Azevedo, Thais de A. de Medeiros, Morsinaldo de A. Medeiros, Daniel G. Costa, Paolo Ferrari, Emiliano Sisinni
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Cachet: Low-Overhead Integrity Verification on Metadata Cache in Secure Nonvolatile Memory Systems IEEE Micro (IF 3.6) Pub Date : 2023-11-28 Tatsuya Kubo, Shinya Takamaeda-Yamazaki
Data confidentiality, integrity, and persistence are essential in secure nonvolatile memory (NVM) systems. However, coupling authenticated memory encryption with security metadata persistence incurs nonnegligible performance overheads. Particularly, the integrity update process for the metadata cache bottlenecks execution performance. In this article, we propose Cachet, a novel integrity verification
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Privacy by Memory Design: Visions and Open Problems IEEE Micro (IF 3.6) Pub Date : 2023-11-28 Jianqing Liu, Na Gong
The threat to data privacy has never been more alarming than it is today. Among existing privacy-enhancing technologies, differential privacy (DP) is widely accepted as the de facto standard for privacy preservation. Yet, the software-based implementation of DP mechanisms is neither friendly for lightweight devices nor secure against side-channel attacks. In this article, we propose a first-of-its-kind
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TinyML but by No Means a Tiny Feat! IEEE Micro (IF 3.6) Pub Date : 2023-11-10 Lizy Kurian John
In this article, the EIC introduces the Special Issue on TinyML and bids farewell to the readers, editors, and staff. A collage with the cover pages of IEEE Micro for the last five years is included.
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Special Issue on TinyML IEEE Micro (IF 3.6) Pub Date : 2023-11-10 Vijay Janapa Reddi, Boris Murmann
This IEEE Micro special issue on tiny machine learning (TinyML) explores cutting-edge research on optimizing machine learning models for highly resource-constrained devices like microcontrollers and embedded systems. The articles cover techniques across the full TinyML stack, including efficient neural network design, on-device learning, model compression, hardware–software co-design, and specialized
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Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies—Part VII: Relationship Between Prosecution Time and Claims IEEE Micro (IF 3.6) Pub Date : 2023-11-10 Joshua J. Yi
A previous article in this series showed that the correlation between the prosecution time and the number of claims was relatively low. This article further analyzes that correlation by examining the effect that patent class has.
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Fifty Years of the International Symposium on Computer Architecture: A Data-Driven Retrospective IEEE Micro (IF 3.6) Pub Date : 2023-11-10 Matthew D. Sinclair, Parthasarathy Ranganathan, Gaurang Upasani, Adrian Sampson, David Patterson, Rutwik Jain, Nidhi Parthasarathy, Shaan Shah
2023 marked the fiftieth year of the International Symposium on Computer Architecture (ISCA). As one of the oldest and preeminent computer architecture conferences, ISCA represents a microcosm of the broader community; correspondingly, a 50-year-retrospective offers us a great way to track the impact and evolution of the field. Analyzing the content and impact of all the papers published at ISCA so
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The AI Gold Rush IEEE Micro (IF 3.6) Pub Date : 2023-11-10 Shane Greenstein
The recent frenzy of commercial interest in large language models could be compared to a gold rush. We consider the metaphor and where it illuminates the mechanisms shaping business decisions. If the rush indicates the presence of a large long-term opportunity, then expect the supply chain of equipment and software to develop to support it.
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COOL-NPU: Complementary Online Learning Neural Processing Unit IEEE Micro (IF 3.6) Pub Date : 2023-11-06 Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Jiwon Choi, Donghyeon Han, Hoi-Jun Yoo
The authors propose a complementary online learning neural processing unit (COOL-NPU) to implement a highly accurate and high-energy-efficient online learning system. It reduces the energy consumption by combining the training methods of convolutional neural network (CNN) and spiking neural network (SNN) and eliminates the power overhead due to the redundant weight update by training trigger with SNN
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A Low-Power Artificial-Intelligence-Based 3-D Rendering Processor With Hybrid Deep Neural Network Computing IEEE Micro (IF 3.6) Pub Date : 2023-11-03 Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Jongjun Park, Hoi-Jun Yoo
A low-power artificial intelligence (AI)-based 3-D rendering processor is proposed for metaverse solutions in mobile platforms. It suggests a brain-inspired rendering acceleration architecture designed with a visual perception core. It removes useless computations by realizing 1) spatial attention, 2) temporal familiarity, and 3) top-down attention. The remaining deep neural network (DNN) inference
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NetDistiller: Empowering Tiny Deep Learning via In Situ Distillation IEEE Micro (IF 3.6) Pub Date : 2023-10-17 Shunyao Zhang, Yonggan Fu, Shang Wu, Jyotikrishna Dass, Haoran You, Yingyan Lin
Boosting the task accuracy of tiny neural networks (TNNs) has become a fundamental challenge for enabling the deployment of TNNs on edge devices, which are constrained by strict limitations in terms of memory, computation, bandwidth, and power supply. To this end, we propose a framework called NetDistiller to boost the achievable accuracy of TNNs by treating them as subnetworks of a weight-sharing
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Exploring Memory-Oriented Design Optimization of Edge AI Hardware for Extended Reality Applications IEEE Micro (IF 3.6) Pub Date : 2023-10-02 Vivek Parmar, Syed Shakib Sarwar, Ziyun Li, Hsien-Hsin S. Lee, Barbara De Salvo, Manan Suri
Low-power edge AI capabilities are essential for on-device extended reality (XR) applications to support the vision of the metaverse. In this work, we investigate two representative XR workloads, 1) hand detection and 2) eye segmentation, for hardware design space exploration. For both applications, we train deep neural networks and analyze the impact of quantization and hardware-specific bottlenecks
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MetaE2RL: Toward Meta-Reasoning for Energy-Efficient Multigoal Reinforcement Learning With Squeezed-Edge You Only Look Once IEEE Micro (IF 3.6) Pub Date : 2023-09-25 Mozhgan Navardi, Edward Humes, Tejaswini Manjunath, Tinoosh Mohsenin
Meta-reasoning shows promise in efficiently using the computational resources of tiny edge devices while performing highly computationally intensive reinforcement learning (RL) algorithms. We propose meta-reasoning for energy efficiency of multigoal RL, a hardware-aware framework that incorporates low-power preprocessing solutions and meta-reasoning to enable deployment of multigoal RL on tiny autonomous
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On-Device Tiny Machine Learning for Anomaly Detection Based on the Extreme Values Theory IEEE Micro (IF 3.6) Pub Date : 2023-09-22 Eduardo S. Pereira, Leonardo S. Marcondes, Josemar M. Silva
The significance of anomaly detection is particularly pronounced in Industry 4.0 applications. For instance, in manufacturing, the timely detection of equipment malfunctions can prevent costly downtime and maintain production efficiency. In energy systems, spotting anomalies in power consumption patterns can enhance resource allocation and optimize energy usage. Equally noteworthy is the ascendancy
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Hardware–Software Co-Design for Real-Time Latency–Accuracy Navigation in Tiny Machine Learning Applications IEEE Micro (IF 3.6) Pub Date : 2023-09-20 Payman Behnam, Jianming Tong, Alind Khare, Yangyu Chen, Yue Pan, Pranav Gadikar, Abhimanyu Bambhaniya, Tushar Krishna, Alexey Tumanov
Tiny machine learning (TinyML) applications increasingly operate in dynamically changing deployment scenarios, requiring optimization for both accuracy and latency. Existing methods mainly target a single point in the accuracy/latency tradeoff space, which is insufficient as no single static point can be optimal under variable conditions. We draw on a recently proposed weight-shared SuperNet mechanism
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Making Machine Learning More Energy Efficient by Bringing It Closer to the Sensor IEEE Micro (IF 3.6) Pub Date : 2023-09-19 Marius Brehler, Lucas Camphausen, Benjamin Heidebroek, Dennis Krön, Henri Gründer, Simon Camphausen
Processing data close to the sensor on a low-cost, low-power embedded device has the potential to unlock new areas for machine learning (ML). Whether it is possible to deploy such ML applications or not depends on the energy efficiency of the solution. One way to realize lower energy consumption is to bring the application as close as possible to the sensor. We demonstrate the concept of transforming
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A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum IEEE Micro (IF 3.6) Pub Date : 2023-09-18 Atsutake Kosuge, Yao-Chung Hsu, Rei Sumikawa, Mototsugu Hamada, Tadahiro Kuroda, Tomoe Ishikawa
A neuromorphic architecture is suitable for low-power tiny-machine learning processors. However, the large number of synapses utilized in recent deep neural networks require multichip implementation, resulting in large power consumption due to chip-to-chip interfaces. Here, we present a 10.7-µJ/frame single-chip neuromorphic field-programmable gate array (FPGA) processor. To reduce the required hardware
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Reg-TuneV2: A Hardware-Aware and Multiobjective Regression-Based Fine-Tuning Approach for Deep Neural Networks on Embedded Platforms IEEE Micro (IF 3.6) Pub Date : 2023-09-18 Arnab Neelim Mazumder, Tinoosh Mohsenin
Fine-tuning deep neural networks (DNNs) for deployment has traditionally relied on computationally intensive methods such as grid searches and neural architecture searches, which may not consider hardware-aware metrics. Moreover, it is essential to consider multiple objectives to develop a range of solutions for tiny machine learning hardware deployment with real-time latency and low power constraints
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Hardware Security and Privacy: Threats and Opportunities IEEE Micro (IF 3.6) Pub Date : 2023-09-12 Lizy Kurian John
Welcome to the 2023 September/October issue of IEEE Micro! This month, we bring the Special Issue on Security and Privacy-Preserving Execution Environments and the Special Issue on Commercial Products 2023 to IEEE Micro’s readers.
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Special Issue on Security and Privacy-Preserving Execution Environments IEEE Micro (IF 3.6) Pub Date : 2023-09-12 Guru Venkataramani
This Special Issue on Security and Privacy-Preserving Execution Environments highlights emerging security and privacy challenges and explores the novel computer architectures that effectively address these issues. The articles cover a wide-ranging set of topics, including security of neural networks, nonvolatile and persistent memory technologies, acceleration of postquantum cryptography (PQC) and
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Interview With Ronnie Chatterji, Coordinator for the Creating Helpful Incentives to Produce Semiconductors and Science Act IEEE Micro (IF 3.6) Pub Date : 2023-09-12 Shane Greenstein
This short article prints an interview with Ronnie Chatterji, the CHIPS and Science Act coordinator. It reviews the Act's main provisions, which will shape the work experience of many IEEE members. The interview concentrates on its anticipated impact on the semiconductor industry and the principal economic policy challenges.
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Addressing the Gap Between Training Data and Deployed Environment by On-Device Learning IEEE Micro (IF 3.6) Pub Date : 2023-09-14 Kazuki Sunaga, Masaaki Kondo, Hiroki Matsutani
The accuracy of tiny machine learning applications is often affected by various environmental factors, such as noises, location/calibration of sensors, and time-related changes. This article introduces a neural network based on-device learning (ODL) approach to address this issue by retraining in deployed environments. Our approach relies on semisupervised sequential training of multiple neural networks
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On-Device Customization of Tiny Deep Learning Models for Keyword Spotting With Few Examples IEEE Micro (IF 3.6) Pub Date : 2023-09-06 Manuele Rusci, Tinne Tuytelaars
Designing a customized keyword spotting (KWS) deep neural network (DNN) for tiny sensors is a time-consuming process, demanding training a new model on a remote server with a dataset of collected keywords. This article investigates the effectiveness of a DNN-based KWS classifier that can be initialized on-device simply by recording a few examples of the target commands. At runtime, the classifier computes
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Acceleration of a Classic McEliece Postquantum Cryptosystem With Cache Processing IEEE Micro (IF 3.6) Pub Date : 2023-08-15 Cyrius Nugier, Vincent Migliore
The National Institute of Standards and Technology’s postquantum cryptography standardization process is in its fourth round, with a first key encapsulation mechanism standard based on learning with errors and three candidates based on error-correcting codes. These primitives’ implementation are designed to be optimal on classical hardware architecture targets. However, emerging architectures with
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A Golden-Free Approach to Detect Trojans in COTS Multi-PCB Systems IEEE Micro (IF 3.6) Pub Date : 2023-08-03 Animesh Basak Chowdhury, Anushree Mahapatra, Yang Liu, Prashanth Krishnamurthy, Farshad Khorrami, Ramesh Karri
Untrusted third parties in commercial-off-the-shelf (COTS) printed circuit board (PCB) supply chains may poison PCBs with hardware, firmware, and software implants. Hence, we focus on detection of malicious implants in PCBs. State-of-the-art hardware Trojan detection methods require a golden PCB system/model to detect malicious implants and do not scale to large-scale COTS PCB systems. We map a COTS
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The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor IEEE Micro (IF 3.6) Pub Date : 2023-07-20 Sriram Aananthakrishnan, Shamsul Abedin, Vincent Cavé, Fabio Checconi, Kristof Du Bois, Stijn Eyerman, Joshua B. Fryman, Wim Heirman, Jason Howard, Ibrahim Hur, Samkit Jain, Marek M. Landowski, Kevin Ma, Jarrod A. Nelson, Robert Pawlowski, Fabrizio Petrini, Sebastian Szkoda, Sanjaya Tayal, Jesmin Jahan Tithi, Yves Vandriessche
High-performance large-scale graph analytics are essential to timely analyze relationships in big datasets. Conventional processor architectures suffer from inefficient resource usage and bad scaling on those workloads. To enable efficient and scalable graph analysis, Intel developed the Programmable Integrated Unified Memory Architecture (PIUMA) as a part of the DARPA Hierarchical Identify Verify
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E-Booster: A Field-Programmable Gate Array-Based Accelerator for Secure Tree Boosting Using Additively Homomorphic Encryption IEEE Micro (IF 3.6) Pub Date : 2023-07-11 Guiming Wu, Qianwen He, Jiali Jiang, Zhenxiang Zhang, Yunfeng Shi, Xin Long, Linquan Jiang, Shuangchen Li, Yuan Xie, Changzheng Wei, Yuan Zhao, Ying Yan, Hui Zhang, Yinchao Zou
Tree boosting is a widely used machine learning model in many financial fields. Additively homomorphic encryption is an important cryptographic tool used for secure tree boosting in the setting of federated learning. However, homomorphic encryption includes computationally expensive operations. Current frameworks for secure tree boosting are extremely slow. In this article, we propose E-Booster, a
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Top Picks From Computer Architecture Conferences! IEEE Micro (IF 3.6) Pub Date : 2023-06-27 Lizy Kurian John
In this issue, IEEE Micro is presenting to you the Top Picks issue with 12 selected papers from all of the computer architecture conference papers of 2022. The Top Picks articles belong to five themes: 1) security, 2) memory systems, 3) data center and cloud computing, 4) building real systems, and 5) sustainability.
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Special Issue on Top Picks From the 2022 Computer Architecture Conferences IEEE Micro (IF 3.6) Pub Date : 2023-06-27 Christopher Batten, Jae W. Lee
Every year, IEEE Micro publishes a special issue that recognizes the most significant research outcomes in computer architecture in terms of novelty and potential for long-term impact. Continuing this tradition, the 2022 selection committee identified 12 articles as top picks from the 2022 computer architecture conferences and another 12 articles as honorable mentions. The articles in this special
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Revizor: Testing Black-Box CPUs Against Speculation Contracts IEEE Micro (IF 3.6) Pub Date : 2023-06-27 Oleksii Oleksenko, Christof Fetzer, Boris Köpf, Mark Silberstein
Speculative execution attacks such as Spectre and Meltdown exploit microarchitectural optimizations to leak information across security domains. These vulnerabilities often stay undetected for years because we lack the tools for systematic analysis of CPUs to find them. In this article, we introduce such a tool, called Revizor, which automatically detects microarchitectural leakage in black-box CPUs
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Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies—Part VI: Relationship Between Prosecution Time and Claims IEEE Micro (IF 3.6) Pub Date : 2023-06-27 Joshua J. Yi
A previous article in this series showed that the average patent prosecution time varies for different companies and depending on the year the patent application was filed. This article analyzes the relationship between the prosecution time and the number of claims.
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A Compressed Spiking Neural Network Onto a Memcapacitive In-Memory Computing Array IEEE Micro (IF 3.6) Pub Date : 2023-06-19 Reon Oshio, Takuya Sugahara, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima
Spiking neural networks (SNNs) enable the execution of deep learning-compatible tasks and approximation algorithms with low latency and low power consumption by operating on a neuromorphic system. Adopting analog in-memory computing (AiMC) in a neuromorphic system can build a system that has an advantage in memory density over a pure digital implementation. However, sensing the AiMC output with simple
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Adversarial Attacks Against Machine Learning-Based Resource Provisioning Systems IEEE Micro (IF 3.6) Pub Date : 2023-06-19 Najmeh Nazari, Hosein Mohammadi Makrani, Chongzhou Fang, Behnam Omidi, Setareh Rafatirad, Hossein Sayadi, Khaled N. Khasawneh, Houman Homayoun
Microarchitectural attacks, such as side-channel, exploit shared resources to leak sensitive information. Performing microarchitectural attacks on the cloud is possible once the attacker’s virtual machine (VM) is co-located with the victim’s VM. Hence, the co-location requirement with the victim limits the practicality of microarchitectural attacks on the cloud. In this work, we demonstrate that resource
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IOCost: Block Input–Output Control for Containers in Datacenters IEEE Micro (IF 3.6) Pub Date : 2023-05-25 Tejun Heo, Dan Schatzberg, Andrew Newell, Song Liu, Saravanan Dhakshinamurthy, Iyswarya Narayanan, Josef Bacik, Chris Mason, Chunqiang Tang, Dimitrios Skarlatos
Resource isolation is a requirement in datacenter environments. However, our production experience in Meta’s large-scale datacenters shows that existing input–output (IO) control mechanisms for block storage are inadequate in containerized environments. This article presents IOCost, an IO control solution designed for containerized environments that provides scalable, work-conserving, and low-overhead
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Hot Chips 34 and More! IEEE Micro (IF 3.6) Pub Date : 2023-05-11 Lizy Kurian John
This article presents an overview of the special issue that contains papers from the 2022 Hot Chips Symposium. The IEEE Micro Editor-in-Chief also congratulates the 2022 Turing Award winner Dr. Robert Metcalfe and reprints a few quotes from his 1976 paper on Ethernet.
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Special Issue on Hot Chips 34 IEEE Micro (IF 3.6) Pub Date : 2023-05-11 Ron Diamant, Krste Asanovic
The Hot Chips conference has served as a leading venue for presenting architectural details of new chips and chip-related technologies, from established industry leaders, startups, and academia. This article presents an introduction to the seven articles that are chosen to be in the IEEE Micro HotChips Special Issue of 2023.
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Cerebras Architecture Deep Dive: First Look Inside the Hardware/Software Co-Design for Deep Learning IEEE Micro (IF 3.6) Pub Date : 2023-05-11 Sean Lie
The compute and memory demands for deep learning and machine learning (ML) have increased by several orders of magnitude in just the last couple of years, and there is no end in sight. Traditional improvements in processor performance alone struggle to keep up with the exponential demand. A new chip architecture co-designed with the ML algorithms can be better equipped to satisfy this unprecedented
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The Arm Morello Evaluation Platform—Validating CHERI-Based Security in a High-Performance System IEEE Micro (IF 3.6) Pub Date : 2023-05-11 Richard Grisenthwaite, Graeme Barnes, Robert N. M. Watson, Simon W. Moore, Peter Sewell, Jonathan Woodruff
Memory safety issues are a persistent source of security vulnerabilities, with conventional architectures and the C/C++ codebase chronically prone to exploitable errors. The Capability Hardware Enhanced RISC Instructions (CHERI) research project has explored a novel architectural approach to ameliorate such issues using unforgeable hardware capabilities to implement pointers. Morello is an Arm experimental