Today's field-programmable gate arrays (FPGAs) offer not only programmable acceleration capabilities but also include advanced features that are on-par with a mainstream processor platform. However, rather than being deployed as autonomous acceleration nodes, they are generally deployed as second-class citizens under the control of a standard processor platform. The configurable network protocol accelerator

In distributed deep learning (DL), collective communication algorithms, such as Allreduce, used to share training results between graphical processing units (GPUs) are an inevitable bottleneck. We hypothesize that a cache access latency occurred at every Allreduce is a significant bottleneck in the current computational systems with high-bandwidth interconnects for distributed DL. To reduce this frequency

PCI Express (PCIe) specification has been doubling the data rate every generation in a backward compatible manner every two to three years. PCIe 6.0 specification will adopt PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach of prior generations. A forward error correction (FEC) mechanism will offset the high BER of PAM-4. We propose a new flit-based approach with a lightweight, low-latency

Chiplet technology can significantly reduce the cost and time needed to develop custom high-performance silicon products. To realize a chiplet-based product, a die-to-die (D2D) network to interconnect the chiplets is required. Almost all of today's chiplet-based products use proprietary D2D interfaces. Industry has primarily paid attention to D2D PHYs. A design also requires logical information flow

The performance of lossy data-center networks (DCNs) may degrade due to packet dropping (and possible retransmission) under congestion. In this article, we propose and evaluate a solution to deal with congestion in lossy DCNs, based on the same approach as the dynamic virtual lanes technique, previously proposed for lossless DCNs. This approach consists of isolating congesting flows in special queues

Reliability and time-efficiency are two key elements to consider in network design. Commonly, each is measured per service—availability probability of a specific service, the latency of a specific service, and overall—system average reliability and average latency, considering the demand for every service. Intuitively, minimizing latency requires minimizing the number of network elements a service

Bunch of wires (BoW) is a new open die-to-die (D2D) interface that aims to gracefully tradeoff performance for design and packaging complexity across a wide range of process nodes. BoW performance can range from 320 Gb/s/mm with a simple design and packaging to 1+ Tb/s/mm with complex design and/or packaging. BoW directly enables heterogeneous integration, a primary advantage of chiplets. We discuss

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This special issue of IEEE Micro aimed at publishing some of the most significant research that can highlight the trends in IC design in 2020 and provide directions for the future IC design era.

Machine learning applications, especially deep neural networks (DNNs) have seen ubiquitous use in computer vision, speech recognition, and robotics. However, the growing complexity of DNN models have necessitated efficient hardware implementations. The key compute primitives of DNNs are matrix vector multiplications, which lead to significant data movement between memory and processing units in today's

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Recent advancements in machine learning provide an opportunity to transform chip design workflows. We review recent research applying techniques such as deep convolutional neural networks and graph-based neural networks in the areas of automatic design space exploration, power analysis, VLSI physical design, and analog design. We also present a future vision of an AI-assisted automated chip design

The future data-centric world demands edge intelligence (EI) - the ability to analyze data locally and to decide on a course of action autonomously. Challenges with Moore's Law scaling and limitations of von Neumann computing architectures are limiting the performance and energy efficiency of conventional electronics. Promising new discoveries of advanced CMOS-compatible HfO2-based ferroelectric devices

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This special issue is a result of the enthusiastic response to the initiation of a new industry paper track at the 2020 International Symposium on Computer Architecture, as we could not accept all the great submissions to that track.1 We are excited to share our interest in commercial products with many industry colleagues who answered our call for papers.

IBM Z is both the oldest and among the most modern of computing platforms. Launched as S/360 in 1964, the mainframe became synonymous with large-scale computing for business and remains the workhorse of enterprise computing for businesses worldwide. Most of the world's largest banks, insurers, retailers, airlines, and enterprises from many other industries have IBM Z at the center of their IT infrastructure

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Reports on anti-trust issues that are likely to impact Facebook, Google/Alphabet, Apple, and Amazon.

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Deep neural networks (DNNs) frequently contain far more weights, represented at a higher precision, than are required for the specific task, which they are trained to perform. Consequently, they can often be compressed using techniques such as weight pruning and quantization that reduce both the model size and inference time without appreciable loss in accuracy. However, finding the best compression

Deep Quantization (below eight bits) can significantly reduce the DNN computation and storage by decreasing the bitwidth of network encodings. However, without arduous manual effort, this deep quantization can lead to significant accuracy loss, leaving it in a position of questionable utility. We propose a systematic approach to tackle this problem, by automating the process of discovering the bitwidths

Genome analysis fundamentally starts with a process known as read mapping, where sequenced fragments of an organism's genome are compared against a reference genome. Read mapping is currently a major bottleneck in the entire genome analysis pipeline, because state-of-the-art genome sequencing technologies are able to sequence a genome much faster than the computational techniques employed to analyze

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The six papers in this special section focus on machine learning for computer systems. Specialized computer systems have driven the performance and capability of deep learning over the past decade.1 However, as machine learning models and systems improve, there is a growing opportunity to also use these models to improve how we design, architect, optimize, and automate computer systems and software

Machine learning has the potential to significantly improve systems, but only under certain conditions. We describe a taxonomy to help identify whether or not machine learning should be applied to particular systems problems, and which approaches are most promising. We believe that this taxonomy can help practitioners and researchers decide how to most effectively use machine learning in their systems

With increasingly complex neural network architectures and heterogeneous device characteristics, finding a reasonable graph partitioning and device placement strategy is challenging. There have been prior attempts at learned approaches for solving device placement, these approaches are computationally expensive, unable to handle large graphs consisting over 50000 nodes, and do not generalize well to

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The two articles in this special section focus on the intersection of systems and biology. Biological systems carry out computation and store information with efficiency levels and complexity that far exceeds those of synthetic computer systems. Consider, for example, that biological neural networks are estimated to offer at least four orders of magnitude with better ops/Joule than synthetic neural

Molecular manipulation and analysis are the cornerstone of life sciences. With the recent advances in molecular data storage and computing, it has become an increasingly exciting and viable alternative for the post-CMOS scaling era. Widespread use of molecular manipulation/analysis and data storage/computing requires a scalable and low-cost platform for hybrid molecular-electronics systems. This enables

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Amazon Web Services (AWS) took a fresh look at the network to provide consistently low latency required for supercomputing applications, while keeping the benefits of public cloud: scalability, elastic on-demand capacity, cost effectiveness, and fast adoption of newer CPUs and GPUs. We built a new network transport protocol, scalable reliable datagram (SRD), designed to utilize modern commodity multitenant

Among its various improvements over prior NVIDIA GPUs, the NVIDIA Turing GPU boasts of four key performance enhancements to effectively counter memory load-to-use stalls. First, reduced latency on L1 hits for global memory loads helps lower average memory lookup latency. Next, the ability to dynamically configure the L1 data RAM between cacheable memory and scratchpad or shared memory, enables driver

The increased variability renders nanometer devices prone to timing errors. Recent work focused on the development of error prediction models for either evaluating the effects of timing errors on applications or guiding the voltage/frequency settings. Such models may have considered the data-dependent excitation of paths, but they have neglected the impact of all the concurrently executed instructions

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The thirteen articles in this special section focus on agile and open source hardware. These papers cover variety of research topics related to fast, agile, and open hardware design, including methodologies, languages, abstractions, and simulators. As the benefits f traditional technology scaling, like Dennard Scaling and Moore’s Law, slow significantly, computer architecture is poised to enter a golden

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Continued improvement in computing efficiency requires functional specialization of hardware designs. Agile hardware design methodologies have been proposed to alleviate the increased design costs of custom silicon architectures, but their practice thus far has been accompanied with challenges in integration and validation of complex systems-on-a-chip (SoCs). We present the Chipyard framework, an integrated

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For five years, OpenPiton has provided hardware designs, build and verification scripts, and other infrastructure to enable efficient, detailed research into manycores and systems-on-chip. It enables open-source hardware development through its open design and support of a plethora of open simulators and CAD tools. OpenPiton was first designed to perform cutting-edge computer architecture research