样式: 排序: IF: - GO 导出 标记为已读
-
FPGA-Accelerated Range-Limited Molecular Dynamics IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-14 Chunshu Wu, Chen Yang, Sahan Bandara, Tong Geng, Anqi Guo, Pouya Haghi, Ang Li, Martin Herbordt
-
Un-IOV: Achieving Bare-metal Level I/O Virtualization Performance for Cloud Usage with Migratability, Scalability and Transparency IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-14 Zongpu Zhang, Chenbo Xia, Cunming Liang, Jian Li, Chen Yu, Tiwei Bie, Roberts Martin, Daly Dan, Xiao Wang, Yong Liu, Haibing Guan
-
AdaptMD: Balancing Space and Performance in NUMA Architectures with Adaptive Memory Deduplication IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-14 Lulu Yao, Yongkun Li, Patrick P. C. Lee, Xiaoyang Wang, Yinlong Xu
-
ElasticDNN: On-device Neural Network Remodeling for Adapting Evolving Vision Domains at Edge IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-14 Qinglong Zhang, Rui Han, Chi Harold Liu, Guoren Wang, Lydia Y. Chen
-
Randomize the running function when it is disclosed IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-04 YongGang Li, Yu Bao, Yeh-Ching Chung
-
Improved Fault Analysis on Subterranean 2.0 IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-04 Sandip Kumar Mondal, Prakash Dey, Himadry Sekhar Roy, Avishek Adhikari, Subhamoy Maitra
-
A Computing-in-Memory-based One-Class Hyperdimensional Computing Model for Outlier Detection IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-03-01 Ruixuan Wang, Sabrina Hassan Moon, X. Sharon Hu, Xun Jiao, Dayane Reis
-
Monotonicity of Multi-Term Floating-Point Adders IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-29 Mantas Mikaitis
-
On the Security of Quotient Filters: Attacks and Potential Countermeasures IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-29 Pedro Reviriego, Miguel González, Niv Dayan, Gabriel Huecas, Shanshan Liu, Fabrizio Lombardi
-
GAS: General-Purpose In-Memory-Computing Accelerator for Sparse Matrix Multiplication IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-29 Xiaoyu Zhang, Zerun Li, Rui Liu, Xiaoming Chen, Yinhe Han
-
O(n) Key–value Sort with Active Compute Memory IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-29 Pouya Esmaili-Dokht, Miquel Guiot, Petar Radojković, Xavier Martorell, Eduard Ayguadé, Jesus Labarta, Jason Adlard, Paolo Amato, Marco Sforzin
-
UniSched: A Unified Scheduler for Deep Learning Training Jobs with Different User Demands IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-29 Wei Gao, Zhisheng Ye, Peng Sun, Tianwei Zhang, Yonggang Wen
-
Single-Domain Generalized Predictor for Neural Architecture Search System IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-15 Lianbo Ma, Haidong Kang, Guo Yu, Qing Li, Qiang He
-
NDRec: A Near-Data Processing System for Training Large-Scale Recommendation Models IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-15 Shiyu Li, Yitu Wang, Edward Hanson, Andrew Chang, Yang Seok Ki, Hai Helen Li, Yiran Chen
-
GateKeeper-GPU: Fast and Accurate Pre-Alignment Filtering in Short Read Mapping IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Zülal Bingöl, Mohammed Alser, Onur Mutlu, Ozcan Ozturk, Can Alkan
-
Accelerating Sparse DNNs Based on Tiled GEMM IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Cong Guo, Fengchen Xue, Jingwen Leng, Yuxian Qiu, Yue Guan, Weihao Cui, Quan Chen, Minyi Guo
-
NDSTRNG: Non-deterministic Sampling-based True Random Number Generator on SoC FPGA Systems IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Yucong Chen, Yanshan Tian, Rui Zhou, Diego Martínez Castro, Deke Guo, Qingguo Zhou
-
TetriX: Flexible Architecture and Optimal Mapping for Tensorized Neural Network Processing IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Jie-Fang Zhang, Cheng-Hsun Lu, Zhengya Zhang
-
A Detailed Historical and Statistical Analysis of the Influence of Hardware Artifacts on SPEC Integer Benchmark Performance IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Yueyao Wang, Samuel Furman, Nicolas Hardy, Margaret Ellis, Godmar Back, Yili Hong, Kirk Cameron
-
Efficient deadlock avoidance for 2D mesh NoCs that use OQ or VOQ routers IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Philippos Papaphilippou, Thiem Van Chu
-
Efficient Execution of Arbitrarily Complex Cross-shard Contracts for Blockchain Sharding IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Jianting Zhang, Wuhui Chen, Zicong Hong, Gang Xiao, Linlin Du, Zibin Zheng
-
TIE: Fast Experiment-driven ML-based Configuration Tuning for In-memory Data Analytics IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Chao Chen, Jinhan Xin, Zhibin Yu
-
I/O Causality Based In-line Data Deduplication for Non-Volatile Memory Enabled Storage Systems IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Haikun Liu, Xiaozhong Jin, Chencheng Ye, Xiaofei Liao, Hai Jin, Yu Zhang
-
BFT-DSN: A Byzantine Fault Tolerant Decentralized Storage Network IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Hechuan Guo, Minghui Xu, Jiahao Zhang, Chunchi Liu, Rajiv Ranjan, Dongxiao Yu, Xiuzhen Cheng
-
Breaking the DECT Standard Cipher with Lower Time Cost IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-14 Lin Ding, Zhengting Li, Ziyu Guan, Xinhai Wang, Zheng Wu
-
The Design of a Lossless Deduplication Scheme to Eliminate Fine-grained Redundancy for JPEG Image Storage Systems IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-07 Cai Deng, Xiangyu Zou, Qi Chen, Bo Tang, Wen Xia
-
Optimizing CNN Computation Using RISC-V Custom Instruction Sets for Edge Platforms IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-02-05 Shihang Wang, Xingbo Wang, Zhiyuan Xu, Bingzhen Chen, Chenxi Feng, Qi Wang, Terry Tao Ye
-
Achieving DRAM-Like PCM by Trading Off Capacity for Latency IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-26 Irina Alam, Puneet Gupta
Phase Change Memory (PCM) is considered one of the most promising scalable non-volatile main memory alternatives to DRAM. It provides $\sim$ 4x-5x cost per bit advantage over DRAM, thus enabling cost-effective dense main memory solution. However, PCM accesses are slower than DRAM, which leads to significantly poorer overall system performance (upto 80% higher execution time for memory intensive applications
-
Towards Secure Runtime Customizable Trusted Execution Environment on FPGA-SoC IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-22 Yanling Wang, Xiaolin Chang, Haoran Zhu, Jianhua Wang, Yanwei Gong, Lin Li
Processing sensitive data and deploying well-designed Intellectual Property (IP) cores on remote Field Programmable Gate Array (FPGA) are prone to private data leakage and IP theft. One effective solution is constructing Trusted Execution Environment (TEE) and its secure boot process on FPGA-SoC (FPGA System on Chip). This paper aims to establish Secure Runtime Customizable TEE (SrcTEE) on FPGA-SoC
-
Blockchain-Based Portable Authenticated Data Transmission for Mobile Edge Computing: A Universally Composable Secure Solution IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-22 Shiyu Li, Yuan Zhang, Yaqing Song, Nan Cheng, Kan Yang, Hongwei Li
In mobile edge computing (MEC) systems, data is frequently transmitted between MEC servers and users holding mobile devices for supporting related services. However, critical threats towards data confidentiality and authenticity are raised: adversaries always attempt to extract data content from the transmission and impersonate others to spread malicious data for profits. Furthermore, users have to
-
Distributed Program Deployment for Resource-aware Programmable Switches IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-18 Fuliang Li, Songlin Chen, Xingxin Jia, Chengxi Gao, Pengfei Wang, Xingwei Wang, Jiannong Cao
-
Distributed Multihop Task Offloading in Massive Heterogeneous IoT Systems IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-18 Wenjie Huang, Zhiwei Zhao, Geyong Min, Jiajun Chen
Edge computing is an emerging technology to satisfy time-varying demands of computation-intensive applications of Internet of Things (IoT) devices. Multi-hop task offloading is one of the key techniques to provide edge services to areas with poor server coverage via multi-hop task forwarding. However, the existing multi-hop offloading approaches have primarily assumed that complete information can
-
Value of Information: A Comprehensive Metric for Client Selection in Federated Edge Learning IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-18 Yifei Zou, Shikun Shen, Mengbai Xiao, Peng Li, Dongxiao Yu, Xiuzhen Cheng
Federated edge learning (FEEL) is a novel paradigm that enables privacy-preserving and distributed machine learning on end devices. However, FEEL faces challenges from data/system heterogeneity among the participating clients and resource constraints of edge networks, which affect the efficiency and accuracy of the learning process. In this paper, we propose a comprehensive framework for client selection
-
Distributed Learning for Large-Scale Models at Edge With Privacy Protection IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-18 Yuan Yuan, Shuzhen Chen, Dongxiao Yu, Zengrui Zhao, Yifei Zou, Lizhen Cui, Xiuzhen Cheng
Big data and strong computing power have promoted artificial intelligence to the era of big models. In particular, ChatGPT's debut heralded the vigorous development of large models. It is an urgent problem to train large models with trillion-level parameters efficiently. Traditional single-machine training stores all data and model parameters in memory. However, due to the limitation of memory and
-
Game-Based Adaptive FLOPs and Partition Point Decision Mechanism With Latency and Energy-Efficient Tradeoff for Edge Intelligence IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-15 Xin Niu, Yajing Huang, Zhiwei Wang, Chen Yu, Hai Jin
As the product of the combination of edge computing and artificial intelligence, edge intelligence (EI) not only solves the problem of insufficient computing capacity of the end device, but also can provide users with various types of intelligent services. However, offline and online model partitioning methods respectively have problems of poor adaptability to the real computing environment and delayed
-
FedRFQ: Prototype-Based Federated Learning With Reduced Redundancy, Minimal Failure, and Enhanced Quality IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-12 Biwei Yan, Hongliang Zhang, Minghui Xu, Dongxiao Yu, Xiuzhen Cheng
Federated learning is a powerful technique that enables collaborative learning among different clients. Prototype-based federated learning is a specific approach that improves the performance of local models by integrating class prototypes. However, prototype-based federated learning faces several challenges, such as prototype redundancy and prototype failure, which can limit its accuracy. In addition
-
FaaSBatch: Boosting Serverless Efficiency With In-Container Parallelism and Resource Multiplexing IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-11 Zhaorui Wu, Yuhui Deng, Yi Zhou, Jie Li, Shujie Pang, Xiao Qin
With high scalability and flexibility, serverless computing is becoming the most promising computing model. Existing serverless computing platforms initiate a container for each function invocation, which leads to a huge waste of computing resources. Our examinations reveal that (i) executing invocations concurrently within a single container can provide comparable performance to that provided by multiple
-
Automated Test Cases Generator for IEC 61131-3 Structured Text Based Dynamic Symbolic Execution IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-08 Jianqi Shi, Yinghao Chen, Qin Li, Yanhong Huang, Yang Yang, Mengyan Zhao
Programmable Logic Controllers (PLCs) are specialized computers extensively utilized in industrial control fields. Since they control industrial equipment, software faults in PLCs can result in significant losses. However, current testing for PLC programs is mainly manual, and there are very few automatic testing tools. Structured Text (ST) is one of the five PLC programming languages stipulated by
-
Randomizing Set-Associative Caches Against Conflict-Based Cache Side-Channel Attacks IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-08 Wei Song, Zihan Xue, Jinchi Han, Zhenzhen Li, Peng Liu
Conflict-based cache side-channel attacks against the last-level cache (LLC) is a widely exploited method for information leaking. Cache randomization has recently been accepted as a promising defense. Most of recent designs randomize skewed caches rather than classic set-associative caches; however, skewed caches incur substantial performance overhead both in area and runtime. We cautiously argue
-
GFBE: A Generalized and Fine-Grained Blockchain Evaluation Framework IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-08 Liyuan Ma, Xiulong Liu, Yuhan Li, Chenyu Zhang, Gaowei Shi, Keqiu Li
Multi-dimensional performance evaluation is crucial for blockchain systems as it enables appropriate blockchain choosing for a given scenario and helps to pinpoint the bottleneck module of a blockchain system to optimize its performance. However, the existing evaluation frameworks for blockchain suffer from low system generality, inefficient workload execution, and incomprehensible evaluation metrics
-
Edge Generation Scheduling for DAG Tasks Using Deep Reinforcement Learning IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-05 Binqi Sun, Mirco Theile, Ziyuan Qin, Daniele Bernardini, Debayan Roy, Andrea Bastoni, Marco Caccamo
Directed acyclic graph (DAG) tasks are currently adopted in the real-time domain to model complex applications from the automotive, avionics, and industrial domains that implement their functionalities through chains of intercommunicating tasks. This paper studies the problem of scheduling real-time DAG tasks by presenting a novel schedulability test based on the concept of trivial schedulability
-
Research and Application of General Information Measures Based on a Unified Model IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-05 Jianfeng Xu
To enable comparisons among various information systems, it is necessary to establish general measures based on a unified model. This paper sets out four concise postulates about information, from which a unified information model is derived using axiomatic methods, which provide a theoretical foundation for developing a series of general information measures. By using volume , the most commonly used
-
Optimal Compression for Encrypted Key-Value Store in Cloud Systems IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-05 Chen Zhang, Qingyuan Xie, Mingyue Wang, Yu Guo, Xiaohua Jia
Key-value store is adopted by many applications due to its high performance in processing big data workloads. With the increasing concern for privacy, some privacy-preserving key-value storage systems have been proposed. A remarkable solution is to group key-value pairs into packs and then compress and encrypt each pack separately. The selection of pack size is important for key-value storage systems
-
Enhancing Graph Random Walk Acceleration via Efficient Dataflow and Hybrid Memory Architecture IEEE Trans. Comput. (IF 3.7) Pub Date : 2024-01-03 Yingxue Gao, Teng Wang, Lei Gong, Chao Wang, Yiqing Hu, Yi Yang, Zhongming Liu, Xi Li, Xuehai Zhou
Graph random walk sampling is becoming increasingly important with the widespread popularity of graph applications. It aims to capture the desirable graph properties by launching multiple walkers to collect feature paths. However, previous research suffers long sampling latency and severe memory access bottlenecks due to intrinsic data dependency and skewed vertex distribution. Thus, in this paper
-
Joint Virtual Network Function Placement and Flow Routing in Edge-Cloud Continuum IEEE Trans. Comput. (IF 3.7) Pub Date : 2023-12-28 Yingling Mao, Xiaojun Shang, Yu Liu, Yuanyuan Yang
Network Function Virtualization (NFV) is becoming one of the most popular paradigms for providing cost-efficient, flexible, and easily-managed network services by migrating network functions from dedicated hardware to commercial general-purpose servers. Despite the benefits of NFV, it remains a challenge to deploy Service Function Chains (SFCs), placing virtual network functions (VNFs) and routing
-
Gem5Tune: A Parameter Auto-Tuning Framework for Gem5 Simulator to Reduce Errors IEEE Trans. Comput. (IF 3.7) Pub Date : 2023-12-27 Yudi Qiu, Tao Huang, Yuxin Tang, Yanwei Liu, Yang Kong, Xulin Yu, Xiaoyang Zeng, Yibo Fan
Computer architecture simulators are widely used to explore new architectures, e.g., the gem5 simulator. However, gem5 has significant performance errors that may lead to misleading research results. Researchers typically reduce errors with the target machine by manual calibration methods, which are time-consuming and require significant expertise. This paper presents gem5Tune, a parameter auto-tuning
-
Learning the Error Features of Approximate Multipliers for Neural Network Applications IEEE Trans. Comput. (IF 3.7) Pub Date : 2023-12-22 Hai Mo, Yong Wu, Honglan Jiang, Zining Ma, Fabrizio Lombardi, Jie Han, Leibo Liu
Approximate multipliers (AMs) have widely been investigated to pursue high-performance and energy-efficient hardware designs for error-tolerant applications, such as neural networks (NNs). The computing accuracy of an AM has been evaluated by using statistical error features; however, it is difficult to estimate the quality of a specific application using AMs. Thus, it is a great challenge to select
-
Multidomain Fault Models Covering the Analog Side of a Smart or Cyber–Physical System IEEE Trans. Comput. (IF 3.7) Pub Date : 2023-12-21 Francesco Tosoni, Nicola Dall’Ora, Enrico Fraccaroli, Sara Vinco, Franco Fummi
Over the last decade, the industrial world has been involved in a massive revolution guided by the adoption of digital technologies. In this context, complex systems like cyber-physical systems play a fundamental role since they were designed and realized by composing heterogeneous components. The combined simulation of the behavioral models of these components allows to reproduce the nominal behavior
-
Honeycomb: Ordered Key-Value Store Acceleration on an FPGA-Based SmartNIC IEEE Trans. Comput. (IF 3.7) Pub Date : 2023-12-20 Junyi Liu, Aleksandar Dragojević, Shane Fleming, Antonios Katsarakis, Dario Korolija, Igor Zablotchi, Ho-Cheung Ng, Anuj Kalia, Miguel Castro
In-memory ordered key-value stores are an important building block in modern distributed applications. We present Honeycomb, a hybrid software-hardware system for accelerating read-dominated workloads on ordered key-value stores that provides linearizability for all operations including scans. Honeycomb stores a B-Tree in host memory. It executes put , update and delete on a CPU. At the same time,
-
GreedW: A Flexible and Efficient Decentralized Framework for Distributed Machine Learning IEEE Trans. Comput. (IF 3.7) Pub Date : 2023-12-18 Ting Wang, Xin Jiang, Qin Li, Haibin Cai
With the ever-increasing demand for computing power in deep learning, distributed training techniques have proven to be effective in meeting these demands. However, current existing state-of-the-art distributed training frameworks, such as Parameter Server (PS), Ring-All-Reduce, and their varieties, still face significant challenges. In particular, the existence of communication bottlenecks can severely
-
An Occlusion and Noise-Aware Stereo Framework Based on Light Field Imaging for Robust Disparity Estimation IEEE Trans. Comput. (IF 3.7) Pub Date : 2023-12-14 Da Yang, Zhenglong Cui, Hao Sheng, Rongshan Chen, Ruixuan Cong, Shuai Wang, Zhang Xiong
Stereo vision is widely studied for depth information extraction. However, occlusion and noise pose significant challenges to traditional methods due to failure in photo consistency. In this paper, an occlusion and noise-aware stereo framework named ONAF is proposed to get a robust depth estimation by integrating the advantages of correspondence cues and refocusing cues from light field (LF). ONAF
-
A Lightweight and Chip-Level Reconfigurable Architecture for Next-Generation IoT End Devices IEEE Trans. Comput. (IF 3.7) Pub Date : 2023-12-14 Chong Zhang, Songfan Li, Yihang Song, Qianhe Meng, Li Lu, Hongzi Zhu, Xin Wang
The rapid development of IoT applications calls for re-configurable IoT devices that can easily extend new functionality on demand. However, in the current architecture, updating chip functions on the end device is highly coupled with the local microprocessor in both hardware and software aspects, leading to inadequate flexibility. In this paper, we propose LEGO, a lightweight architecture with chip-level
-
HiBid: A Cross-Channel Constrained Bidding System With Budget Allocation by Hierarchical Offline Deep Reinforcement Learning IEEE Trans. Comput. (IF 3.7) Pub Date : 2023-12-14 Hao Wang, Bo Tang, Chi Harold Liu, Shangqin Mao, Jiahong Zhou, Zipeng Dai, Yaqi Sun, Qianlong Xie, Xingxing Wang, Dong Wang
Online display advertising platforms service numerous advertisers by providing real-time bidding (RTB) for the scale of billions of ad requests every day. The bidding strategy handles ad requests cross multiple channels to maximize the number of clicks under the set financial constraints, i.e., total budget and cost-per-click (CPC), etc. Different from existing works mainly focusing on single channel
-
Decoder Reduction Approximation Scheme for Booth Multipliers IEEE Trans. Comput. (IF 3.7) Pub Date : 2023-12-14 Muhammad Hamis Haider, Hao Zhang, Seok-Bum Ko
Existing approximate Booth multipliers fail to keep up with modern approximate multipliers such as truncation-based approximate logarithmic multipliers. This paper introduces a new approximation scheme for Booth multipliers that can operate with negligible error rates using only $N/4$ Booth decoders, instead of the traditional $N/2$ Booth decoders. The proposed 16-bit BD16.4 approximate Booth multiplier
-
Blockchain-Based Distributed Multiagent Reinforcement Learning for Collaborative Multiobject Tracking Framework IEEE Trans. Comput. (IF 3.7) Pub Date : 2023-12-14 Jiahao Shen, Hao Sheng, Shuai Wang, Ruixuan Cong, Da Yang, Yang Zhang
With the development of smart cities, video surveillance has become more prevalent in urban areas. The rapid growth of data brings challenges to video processing and analysis. Multi-object tracking (MOT), one of the most fundamental tasks in computer vision, has a wide range of applications and development prospects. MOT aims to locate multiple objects and maintain their unique identities by analyzing
-
A GPU-Enabled Real-Time Framework for Compressing and Rendering Volumetric Videos IEEE Trans. Comput. (IF 3.7) Pub Date : 2023-12-14 Dongxiao Yu, Ruopeng Chen, Xin Li, Mengbai Xiao, Guanghui Zhang, Yao Liu
Nowadays, volumetric videos have emerged as an attractive multimedia application providing highly immersive watching experiences since viewers could adjust their viewports at 6 degrees-of-freedom. However, the point cloud frames composing the video are prohibitively large, and effective compression techniques should be developed. There are two classes of compression methods. One suggests exploiting
-
Branch Predictor Design for Energy Harvesting Powered Nonvolatile Processors IEEE Trans. Comput. (IF 3.7) Pub Date : 2023-12-13 Mengying Zhao, Shuo Xu, Lihao Dong, Chun Jason Xue, Dongxiao Yu, Xiaojun Cai, Zhiping Jia
Non-volatile processors are proposed for ambient energy harvesting systems to enable accumulative computing across power failures. They employ nonvolatile memory for processor status backup before power outage and resume the system after power recovers. A straightforward backup policy is to back up all volatile data in processors, but it induces high backup cost. In this paper, we focus on branch predictor
-
A Practical Adversarial Attack Against Sequence-Based Deep Learning Malware Classifiers IEEE Trans. Comput. (IF 3.7) Pub Date : 2023-12-08 Kai Tan, Dongyang Zhan, Lin Ye, Hongli Zhang, Binxing Fang
Sequence-based deep learning models (e.g., RNNs), can detect malware by analyzing its behavioral sequences. Meanwhile, these models are susceptible to adversarial attacks. Attackers can create adversarial samples that alter the sequence characteristics of behavior sequences to deceive malware classifiers. The existing methods for generating adversarial samples typically involve deleting or replacing
-
CDS: Coupled Data Storage to Enhance Read Performance of 3D TLC NAND Flash Memory IEEE Trans. Comput. (IF 3.7) Pub Date : 2023-12-07 Wan-Ling Wu, Jen-Wei Hsieh, Hao-Yu Ku
Due to the strong demand of massive storage capacity, the density of flash memory has been improved in terms of technology node scaling, multi-bit per cell technique, and 3D stacking. However, these techniques also degrade read performance and reliability. The long read latency comes from increased data sensing time and time-consuming ECC decoding time. Storing multiple bits per cell results in more
-
Wrong-Path-Aware Entangling Instruction Prefetcher IEEE Trans. Comput. (IF 3.7) Pub Date : 2023-12-01 Alberto Ros, Alexandra Jimborean
Instruction prefetching is instrumental for guaranteeing a high flow of instructions through the processor front end for applications whose working set does not fit in the lower-level caches. Examples of such applications are server workloads, whose instruction footprints are constantly growing. There are two main techniques to mitigate this problem: fetch directed prefetching (or decoupled front end)