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MiniFloats on RISC-V Cores: ISA Extensions with Mixed-Precision Short Dot Products IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2024-02-19 Luca Bertaccini, Gianna Paulin, Matheus Cavalcante, Tim Fischer, Stefan Mach, Luca Benini
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A Design Framework for Hardware-Efficient Logarithmic Floating-Point Multipliers IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2024-02-19 Tingting Zhang, Zijing Niu, Jie Han
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Adaptive Task Migration in Multiplex Networked Industrial Chains IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2024-02-16 Kai Di, Fulin Chen, Yuanshuang Jiang, Pan Li, Tianyi Liu, Yichuan Jiang
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Engravings, Secrets, and Interpretability of Neural Networks IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2024-01-31 Nathaniel Hobbs, Periklis A. Papakonstantinou, Jaideep Vaidya
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Personalized Privacy-Preserving Framework for Cross-Silo Federated Learning IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2024-01-31 Van-Tuan Tran, Huy-Hieu Pham, Kok-Seng Wong
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Unsupervised Domain Adaptation Via Contrastive Adversarial Domain Mixup: A Case Study on COVID-19 IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2024-01-26 Huimin Zeng, Zhenrui Yue, Lanyu Shang, Yang Zhang, Dong Wang
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Hardware-Aware DNN Compression via Diverse Pruning and Mixed-Precision Quantization IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2024-01-03 Konstantinos Balaskas, Andreas Karatzas, Christos Sad, Kostas Siozios, Iraklis Anagnostopoulos, Georgios Zervakis, J¨org Henkel
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MFDS-STGCN: Predicting the Behaviors of College Students With Fine-Grained Spatial-Temporal Activities Data IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2024-01-01 Dongbo Zhou, Hongwei Yu, Jie Yu, Shuai Zhao, Wenhui Xu, Qianqian Li, Fengyin Cai
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Combining Trust Graphs and Keystroke Dynamics to Counter Fake Identities in Social Networks IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2024-01-01 Francesco Buccafurri, Gianluca Lax, Denis Migdal, Lorenzo Musarella, Christophe Rosenberger
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Scheduling Coflows by Online Identification in Data Center Network IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-09-29 Chang Ruan, Jianxin Wang, Wanchun Jiang, Tao Zhang
Recently, many scheduling schemes leverage coflows to improve the communication performance of jobs in distributed application frameworks deployed in data center networks, such as MapReduce and Spark. Most of them require application modification to obtain the coflow information such as the coflow ID. The latest work CODA suggests non-intrusively extracting coflow information via an identification
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Quadtree-Based Adaptive Spatial Decomposition for Range Queries Under Local Differential Privacy IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-09-26 Huiwei Wang, Yaqian Huang, Huaqing Li
Nowadays, researchers have shown significant interest in geographic location-based spatial data analysis due to its wide range of application scenarios. However, the accuracy of the grid-based quadtree range query (GT-R) algorithm, which utilizes the uniform grid method to divide the data space, is compromised by the excessive noise introduced in the divided area. In addition, the private adaptive
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Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-09-25 Aibin Yan, Aoran Cao, Zhengfeng Huang, Jie Cui, Tianming Ni, Patrick Girard, Xiaoqing Wen, Jiliang Zhang
The continuous advancement of complementary metal-oxide-semiconductor technologies makes flip-flops (FFs) vulnerable to soft errors. Single-node upsets (SNUs), as well as double-node upsets (DNUs), are typical soft errors. This article proposes two radiation-hardened FF designs, namely DNU-tolerant FF (DUT-FF) and DNU-recoverable FF (DUR-FF). First, the DUT-FF which mainly consists of four dual-in
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Adversarial Attacks Assessment of Salient Object Detection via Symbolic Learning IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-09-22 Gustavo Olague, Roberto Pineda, Gerardo Ibarra-Vazquez, Matthieu Olague, Axel Martinez, Sambit Bakshi, Jonathan Vargas, Isnardo Reducindo
Machine learning is at the center of mainstream technology and outperforms classical approaches to handcrafted feature design. Aside from its learning process for artificial feature extraction, it has an end-to-end paradigm from input to output, reaching outstandingly accurate results. However, security concerns about its robustness to malicious and imperceptible perturbations have drawn attention
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Always on Voting: A Framework for Repetitive Voting on the Blockchain IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-09-22 Sarad Venugopalan, Ivana Stančíková, Ivan Homoliak
Elections repeat commonly after a fixed time interval, ranging from months to years. This results in limitations on governance since elected candidates or policies are difficult to remove before the next elections, if needed, and allowed by the corresponding law. Participants may decide (through a public deliberation) to change their choices but have no opportunity to vote for these choices before
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Deadline-Aware and Energy-Efficient Dynamic Task Mapping and Scheduling for Multicore Systems Based on Wireless Network-on-Chip IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-09-20 Abbas Dehghani, Sadegh Fadaei, Bahman Ravaei, Keyvan RahimiZadeh
Hybrid Wireless Network-on-Chip (HWNoC) architecture has been introduced as a promising communication infrastructure for multicore systems. HWNoC-based multicore systems encounter extremely dynamic application workloads that are submitted at run-time. Mapping and scheduling of these applications are critical for system performance, especially for real-time applications. The existing resource allocation
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Guest Editorial Special Section on Applied Software Aging and Rejuvenation IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-09-05 Michael Grottke, Alberto Avritzer, Hironori Washizaki, Kishor Trivedi
Since the publication of the first paper on software aging and rejuvenation by Huang et al. in 1995 [1], considerable research has been devoted to this topic. It deals with the phenomenon that continuously-running software systems may show an increasing failure rate and/or a degrading performance, either because error conditions accumulate inside the running system or because the rate at which faults
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Noise-Shaping Binary-to-Stochastic Converters for Reduced-Length Bit-Streams IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-08-01 Kleanthis Papachatzopoulos, Vassilis Paliouras
Stochastic computations have attracted significant attention for applications with moderate fixed-point accuracy requirements, as they offer minimal complexity. In these systems, a stochastic bit-stream encodes a data sample. The derived bit-stream is used for processing. The bit-stream length determines the computation latency for bit-serial implementations and hardware complexity for bit-parallel
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An Edge-Cloud Collaboration Framework for Graph Processing in Smart Society IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-07-24 Jun Zhou, Masaaki Kondo
Due to the limitations of cloud computing on latency, bandwidth and data confidentiality, edge computing has emerged as a novel location-aware way to provide the capacity-constrained portable terminals with more processing capacity to improve the computing performance and quality of service (QoS) in several typical domains of the human activity in smart society, such as social networks, medical diagnosis
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Privacy-Preserving Authentication Protocols for IoT Devices Using the SiRF PUF IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-07-20 Jim Plusquellic, Eirini Eleni Tsiropoulou, Cyrus Minwalla
Authentication between IoT devices is important for maintaining security, trust and data integrity in an edge device ecosystem. The low-power, reduced computing capacity of the IoT device makes public-private, certificate-based forms of authentication impractical, while other lighter-weight, symmetric cryptography-based approaches, such as message authentication codes, are easy to spoof in unsupervised
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New Construction of Balanced Codes Based on Weights of Data for DNA Storage IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-07-13 Xiaozhou Lu, Sunghwan Kim
As maintaining a proper balanced GC content is crucial for minimizing errors in DNA storage, constructing GC-balanced DNA codes has become an important research topic. In this article, we propose a novel code construction method based on the weight distribution of the data, which enables us to construct GC-balanced DNA codes. Additionally, we introduce a specific encoding process for both balanced
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A Graph-Incorporated Latent Factor Analysis Model for High-Dimensional and Sparse Data IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-07-11 Di Wu, Yi He, Xin Luo
A High-dimensional and s parse (HiDS) matrix is frequently encountered in Big Data-related applications such as e-commerce systems or wireless sensor networks. It is of great significance to perform highly accurate representation learning on an HiDS matrix due to the great desires of extracting latent knowledge from it. L atent f actor a nalysis (LFA), which represents an HiDS matrix by learning the
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FINISH: Efficient and Scalable NMF-Based Federated Learning for Detecting Malware Activities IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-07-11 Yu-Wei Chang, Hong-Yen Chen, Chansu Han, Tomohiro Morikawa, Takeshi Takahashi, Tsung-Nan Lin
5G networks with the vast number of devices pose security threats. Manual analysis of such extensive security data is complex. Dark-NMF can detect malware activities by monitoring unused IP address space, i.e., the darknet. However, the challenges of cooperative training for Dark-NMF are immense computational complexity with Big Data, communication overhead, and privacy concern with darknet sensor
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Resource Allocation Optimization by Quantum Computing for Shared Use of Standalone IRS IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-07-11 Takahiro Ohyama, Yuichi Kawamoto, Nei Kato
Intelligent reflecting surfaces (IRSs) have attracted attention as a technology that can considerably improve the energy utilization efficiency of sixth-generation (6G) mobile communication systems. IRSs enable control of propagation characteristics by adjusting the phase shift of each reflective element. However, designing the phase shift requires the acquisition of channel information for each reflective
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PISA: A Non-Volatile Processing-in-Sensor Accelerator for Imaging Systems IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-07-11 Shaahin Angizi, Sepehr Tabrizchi, David Z. Pan, Arman Roohi
This work proposes a Processing-In-Sensor Accelerator, namely PISA, as a flexible, energy-efficient, and high-performance solution for real-time and smart image processing in AI devices. PISA intrinsically implements a coarse-grained convolution operation in Binarized-Weight Neural Networks (BWNNs) leveraging a novel compute-pixel with non-volatile weight storage at the sensor side. This remarkably
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CANNON: Communication-Aware Sparse Neural Network Optimization IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-06-30 A. Alper Goksoy, Guihong Li, Sumit K. Mandal, Umit Y. Ogras, Radu Marculescu
Sparse deep neural networks (DNNs) have the potential to deliver compelling performance and energy efficiency without significant accuracy loss. However, their benefits can quickly diminish if their training is oblivious to the target hardware. For example, fewer critical connections can have a significant overhead if they translate into long-distance communication on the target hardware. Therefore
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Rei: A Reconfigurable Interconnection Unit for Array-Based CNN Accelerators IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-06-30 Paria Darbani, Hakem Beitollahi, Pejman Lotfi-Kamran
Convolutional Neural Network (CNN) is used in many real-world applications due to its high accuracy. The rapid growth of modern applications based on learning algorithms has increased the importance of efficient implementation of CNNs. The array-type architecture is a well-known platform for the efficient implementation of CNN models, which takes advantage of parallel computation and data reuse. However
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Guest Editorial: IEEE Transactions on Emerging Topics in Computing Thematic Section on Memory- Centric Designs: Processing-in-Memory, In-Memory Computing, and Near-Memory Computing for Real-World Applications IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-06-06 Yuan-Hao Chang, Vincenzo Piuri
The von Neumann architecture has been the status quo since the dawn of modern computing. Computers built on the von Neumann architecture are composed of an intelligent master processor (e.g., CPU) and dumb memory/storage devices incapable of computation (e.g., memory and disk). However, the skyrocketing data volume in modern computing is calling such status quo into question. The excessive amounts
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Construction of a Spike-Based Memory Using Neural-Like Logic Gates Based on Spiking Neural Networks on SpiNNaker IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-06-05 Alvaro Ayuso-Martinez, Daniel Casanueva-Morato, J. P. Dominguez-Morales, Angel Jimenez-Fernandez, Gabriel Jimenez-Moreno
Neuromorphic engineering concentrates the efforts of a large number of researchers due to its great potential as a field of research, in a search for the exploitation of the advantages of the biological nervous system and the brain as a whole for the design of more efficient and real-time capable applications. For the development of applications as close to biology as possible, Spiking Neural Networks
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An Optimized Hardware Implementation of Modular Multiplication of Binary Ring LWE IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-06-01 Karim Shahbazi, Seok-Bum Ko
Providing end-to-end security is vital for most networks. Emerging quantum computers make it necessary to design secure crypto-systems against quantum attacks. Binary Ring Learning With Error (Ring-Bin LWE) is a Lattice-based cryptography that is hard to solve by quantum computers. Also, this algorithm does not have costly operations in terms of area, making Ring-Bin LWE a suitable algorithm for resource-constraint
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An Energy-Efficient Generic Accuracy Configurable Multiplier Based on Block-Level Voltage Overscaling IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-05-30 Ali Akbar Bahoo, Omid Akbari, Muhammad Shafique
Voltage Overscaling (VOS) is one of the well-known techniques to increase the energy efficiency of arithmetic units. Also, it can provide significant lifetime improvements, while still meeting the accuracy requirements of inherently error-resilient applications. This paper proposes a generic accuracy-configurable multiplier that employs the VOS at a coarse-grained level (block-level) to reduce the
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Predicting Aging-Related Bugs Using Network Analysis on Aging-Related Dependency Networks IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-05-30 Fangyun Qin, Zheng Zheng, Xiaohui Wan, Zhihao Liu, Zhiping Shi
Software aging, a phenomenon that exhibits an increasing failure rate or progressive performance degradation in long-running software systems, has caused serious cost damage or even loss of human lives. To aid aging-related bug (ARB, whose activation can result in software aging) detection and removal before software release, ARB prediction was proposed. Based on the prediction results, software teams
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A Low-Cost Wireless Body Area Network for Human Activity Recognition in Healthy Life and Medical Applications IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-05-12 Florenc Demrozi, Cristian Turetta, Philipp H. Kindt, Fabio Chiarani, Ruggero Angelo Bacchin, Nicola Valè, Francesco Pascucci, Paola Cesari, Nicola Smania, Stefano Tamburin, Graziano Pravadelli
Moved by the necessity, also related to the ongoing COVID-19 pandemic, of the design of innovative solutions in the context of digital health, and digital medicine, Wireless Body Area Networks (WBANs) are more and more emerging as a central system for the implementation of solutions for well-being and healthcare. In fact, by elaborating the data collected by a WBAN, advanced classification models can
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A Large Scale Characterization of Device Uptimes IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-05-03 Mateus Nogueira, Erica da Cunha Ferreira, Pedro Tubenchlak Boechat, Felipe Assis, Estevão Rabello, Rafael Nascimento, Daniel Sadoc Menasché, Geraldo Xexéo, Abhishek Ramchandran, Katinka Wolter
Devices ages, also referred to as uptimes, convey information about systems, and are instrumental for patching and rejuvenation purposes. Knowing that a device is up for a long time suggests that it may be at risk or that degradation due to bugs may be in place. Nonetheless, there has been no systematic study of devices uptimes so far. The goal of this paper is to provide a large scale characterization
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Algorithm-Hardware Co-Design of Split-Radix Discrete Galois Transformation for KyberKEM IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-05-02 Guangyan Li, Donglong Chen, Gaoyu Mao, Wangchen Dai, Abdurrashid Ibrahim Sanka, Ray C.C. Cheung
KyberKEM is one of the final round key encapsulation mechanisms in the NIST post-quantum cryptography competition. Number theoretic transform (NTT), as the computing bottleneck of KyberKEM, has been widely studied. Discrete Galois Transformation (DGT) is a variant of NTT that reduces transform length into half but requires more multiplication operations than the latest NTT algorithm in theoretical
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A Low Latency Approximate Adder Design Based on Dual Sub-Adders With Error Recovery IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-05-02 Hyoju Seo, Yongtae Kim
This paper presents a novel dual sub-adder based approximate adder that splits a precise adder into two to significantly reduce the latency. The proposed error recovery and reduction technique effectively compensates for the catastrophic accuracy degradation incurred by the split. Implemented in a 65- $nm$ CMOS technology, our design reduces the delay and energy consumption by up to 68% and 78%, respectively
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Computation Efficiency Maximization in Multi-UAV-Enabled Mobile Edge Computing Systems Based on 3D Deployment Optimization IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-04-24 Xiaoheng Deng, Jiahao Zhao, Zhufang Kuang, Xuechen Chen, Qi Guo, Fengxiao Tang
Unmanned aerial vehicles (UAVs) have been widely devoted to mobile edge computing (MEC) systems that have limited resources to provide high-quality computing and communication services for Internet of Things (IoT) terminals. Energy-efficient computation and resource allocation are key issues for the sustainable operation of the above-mentioned systems. The 3D deployment optimization of multi-UAVs is
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BIC Codes: Bit Insertion-Based Constrained Codes With Error Correction for DNA Storage IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-04-24 Seong-Joon Park, Hosung Park, Hee-Youl Kwak, Jong-Seon No
In this article, we propose a new coding algorithm for DNA storage over both error-free and error channels. For the error-free case, we propose a constrained code called bit insertion-based constrained (BIC) code. BIC codes convert a binary data sequence to multiple oligo sequences satisfying the maximum homopolymer run (i.e., run-length (RL)) constraint by inserting dummy bits. We show that the BIC
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Multitask Particle Swarm Optimization With Dynamic Transformation IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-04-21 Honggui Han, Xing Bai, Hongyan Yang, Ying Hou, Junfei Qiao
Multitask optimization (MTO) mainly utilizes knowledge transfer among tasks to address multiple optimization problems in parallel. However, the decision space dimensions of different tasks often differ, which leads to the failure of knowledge transfer. Therefore, it is a challenging problem to transfer knowledge among tasks with different dimensions to achieve parallel optimization of multiple tasks
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Runtime System Support for CPS Software Rejuvenation IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-04-21 Raffaele Romagnoli, Bruce H. Krogh, Dionisio de Niz, Anton D. Hristozov, Bruno Sinopoli
Software rejuvenation, which was originally introduced to deal with performance degradation due to software aging, has recently been proposed as a mechanism to provide protection against run-time cyber attacks in cyber-physical systems (CPSs). Experiments have demonstrated that CPSs can be protected from attacks that corrupt run-time code and data by periodically restoring the run-time system with
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AritPIM: High-Throughput In-Memory Arithmetic IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-04-21 Orian Leitersdorf, Dean Leitersdorf, Jonathan Gal, Mor Dahan, Ronny Ronen, Shahar Kvatinsky
Digital processing-in-memory (PIM) architectures are rapidly emerging to overcome the memory-wall bottleneck by integrating logic within memory elements. Such architectures provide vast computational power within the memory itself in the form of parallel bitwise logic operations. We develop novel algorithmic techniques for PIM that, combined with new perspectives on computer arithmetic, extend this
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A Flexible and Reliable RRAM-Based In-Memory Computing Architecture for Data-Intensive Applications IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-04-21 Nima Eslami, Mohammad Hossein Moaiyeri
This article proposes a practical, flexible, and reliable in-memory computing architecture for resistive-memory-based logic designs. Our design uses a new RRAM-based polymorphic in-memory logic gate implementing all 2-input Boolean logic functions to handle real-time applications like search engines. This design reduces the proposed architecture's power-delay product (PDP) compared to competing designs
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Resource-Aware Knowledge Distillation for Federated Learning IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-03-31 Zheyi Chen, Pu Tian, Weixian Liao, Xuhui Chen, Guobin Xu, Wei Yu
The rise of deep learning and the Internet of Things (IoT) has driven a number of smart-world applications, which are mostly deployed in distributed environments. Federated learning, a privacy-preserving collaborative learning paradigm, has shown considerable potential to leverage the rich distributed data at network edges. Nonetheless, the heterogeneity of IoT devices and their connected network environment
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DT2CAM: A Decision Tree to Content Addressable Memory Framework IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-03-29 Mariam Rakka, Mohammed E. Fouda, Rouwaida Kanj, Fadi Kurdahi
Decision trees are powerful tools for data classification. Accelerating the decision tree search is crucial for on-the-edge applications with limited power and latency budget. In this article, we propose a content-addressable memory compiler for decision tree inference acceleration. We propose a novel ”adaptive-precision” scheme that results in a compact implementation and enables an efficient bijective
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Software Aging Prediction for Cloud Services Using a Gate Recurrent Unit Neural Network Model Based on Time Series Decomposition IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-03-22 Kai Jia, Xiao Yu, Chen Zhang, Wenhua Hu, Dongdong Zhao, Jianwen Xiang
Software aging, which is caused by the accumulation of errors in the system and the consumption of computing resources, tends to occur in long-running cloud service software systems. In practice, software aging prediction has proven to be useful in planning the time to trigger rejuvenation because it provides a prior estimate of future resource consumption. However, aging indicators (e.g., physical
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Path-Based Delay Variation Models for Parallel-Prefix Adders IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-02-09 Kleanthis Papachatzopoulos, Vassilis Paliouras
State-of-the-art static timing analysis algorithms can evaluate worst-case delay in statistical terms. In this paper, a modeling framework is introduced for the evaluation of the maximum-delay Cumulative Density Function (CDF) of an ensemble of parallel-prefix adder topologies. For moderate variations and close-to-nominal supply voltages, the maximum delay of parallel-prefix adders is practically determined
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A Binary-Activation, Multi-Level Weight RNN and Training Algorithm for ADC-/DAC-Free and Noise-Resilient Processing-in-Memory Inference With eNVM IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-02-08 Siming Ma, David Brooks, Gu-Yeon Wei
We propose a new algorithm for training neural networks with binary activations and multi-level weights, which enables efficient processing-in-memory circuits with embedded nonvolatile memories (eNVM). Binary activations obviate costly DACs and ADCs. Multi-level weights leverage multi-level eNVM cells. Compared to existing algorithms, our method not only works for feed-forward networks (e.g., fully-connected
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An Energy-Efficient Computing-in-Memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-01-27 Bi Wu, Haonan Zhu, Dayane Reis, Zhaohao Wang, Ying Wang, Ke Chen, Weiqiang Liu, Fabrizio Lombardi, Xiaobo Sharon Hu
The separation of memory and computing units in the von Neumann architecture leads to undesirable energy consumption due to data movement and insufficient memory bandwidth. Energy-efficient in-memory computing platforms have the potential to address such issues. Due to its non-volatility and advantageous features over CMOS (such as low power, near-zero leakage current and high integration density)
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Numerical Model for 32-Bit Magnonic Ripple Carry Adder IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-01-26 Umberto Garlando, Qi Wang, Oleksandr V. Dobrovolskiy, Andrii V. Chumak, Fabrizio Riente
In CMOS-based electronics, the most straightforward way to implement a summation operation is to use the ripple carry adder (RCA). Magnonics, the field of science concerned with data processing by spin waves and their quanta magnons, recently proposed a magnonic half-adder that can be considered as the simplest magnonic integrated circuit. Here, we develop a computation model for the magnonic basic
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NeuSB: A Scalable Interconnect Architecture for Spiking Neuromorphic Hardware IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-01-26 Adarsha Balaji, Phu Khanh Huynh, Francky Catthoor, Nikil D. Dutt, Jeffrey L. Krichmar, Anup Das
Neuromorphic systems are typically designed as a tile-based architecture where inter-tile data communication is facilitated using a shared global interconnect. Congestion on this interconnect can increase both interconnect energy, which increases the total energy consumption of the hardware and latency, which impacts the performance e.g., accuracy of the application that is being executed on the hardware
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BNN An Ideal Architecture for Acceleration With Resistive in Memory Computation IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-01-23 Andrew Ding, Ye Qiao, Nader Bagherzadeh
Binary Neural Networks (BNN) have binarized (-1 and 1) weights and feature maps. Achieving smaller model sizes and computational simplicity, they are well suited for edge-AI systems with power and hardware constraints. Recently, memristive crossbar arrays have gained considerable attention from researchers to perform analog in-memory vector-matrix multiplications in machine learning accelerators, with
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Bit-Line Computing for CNN Accelerators Co-Design in Edge AI Inference IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2023-01-23 Marco Rios, Flavio Ponzina, Alexandre Levisse, Giovanni Ansaloni, David Atienza
By supporting the access of multiple memory words at the same time, Bit-line Computing (BC) architectures allow the parallel execution of bit-wise operations in-memory. At the array periphery, arithmetic operations are then derived with little additional overhead. Such a paradigm opens novel opportunities for Artificial Intelligence (AI) at the edge, thanks to the massive parallelism inherent in memory
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ROSETTA: A Resource and Energy-Efficient Inference Processor for Recurrent Neural Networks Based on Programmable Data Formats and Fine Activation Pruning IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2022-12-27 Jiho Kim, Tae-Hwan Kim
Recurrent neural networks (RNNs) are extensively employed to perform inference based on the temporal features of the input data. However, their computational workload and power consumption involved in inference are prohibitively high in practice, which may be problematic to achieve a high-speed inference in devices with tight limitations in the available silicon resources and power supply. This paper
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AdvParams: An Active DNN Intellectual Property Protection Technique via Adversarial Perturbation Based Parameter Encryption IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2022-12-27 Mingfu Xue, Zhiyu Wu, Yushu Zhang, Jian Wang, Weiqiang Liu
The construction of Deep Neural Network (DNN) models requires high cost, thus a well-trained DNN model can be considered as intellectual property (IP) of the model owner. To date, many DNN IP protection methods have been proposed, but most of them are watermarking based verification methods where model owners can only verify their ownership passively after the copyright of DNN models has been infringed
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Revealing an Inherently Limiting Factor in Human Mobility Prediction IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2022-12-19 Licia Amichi, Aline Viana Carneiro, Mark Crovella, Antonio Loureiro
Predicting how humans move within space and time is a central topic in many scientific domains such as epidemic propagation, urban planning, and ride-sharing. However, current studies neglect individuals’ preferences to explore and discover new areas. Yet, neglecting novelty-seeking activities at first glance appears to be inconsequential on the ability to understand and predict individuals’ trajectories
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ALP: Alleviating CPU-Memory Data Movement Overheads in Memory-Centric Systems IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2022-12-19 Nika Mansouri Ghiasi, Nandita Vijaykumar, Geraldo F. Oliveira, Lois Orosa, Ivan Fernandez, Mohammad Sadrosadati, Konstantinos Kanellopoulos, Nastaran Hajinazar, Juan Gómez Luna, Onur Mutlu
Partitioning applications between near-data processing (NDP) and host CPU cores causes inter-segment data movement overhead, which is caused by moving data generated by one segment (e.g., instructions, functions) and used in other consecutive segments. Prior works take two approaches to this problem. The first approach maps segments to NDP or host cores based on the properties of each segment, neglecting
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TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-Based FPGAs IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2022-12-19 Weikang Qiao, Licheng Guo, Zhenman Fang, Mau-Chung Frank Chang, Jason Cong
The emergence of high-bandwidth memory (HBM) brings new opportunities to boost the performance of sorting acceleration on FPGAs, which was conventionally bounded by the available off-chip memory bandwidth. However, it is nontrivial for designers to fully utilize this immense bandwidth. First, the existing sorter designs cannot be directly scaled at the increasing rate of available off-chip bandwidth
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Leveraging Journaling File System for Prompt Secure Deletion on Interlaced Recording Drives IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2022-12-08 Shuo-Han Chen, Kuo-Hao Huang
With the growing awareness of secure computation, more and more users want to make their digital footprints securely deleted and irrecoverable after updating or removing files on storage devices. To achieve the effect of secure deletion, overwritten-based secure deletion techniques have been proposed to overwrite invalidated storage space with scrambled data content. Nevertheless, overwritten-based
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A Segmented-Edit Error-Correcting Code With Re-Synchronization Function for DNA-Based Storage Systems IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2022-12-05 Zihui Yan, Cong Liang, Huaming Wu
As a powerful tool for storing digital information in chemically synthesized molecules, DNA-based data storage has undergone continuous development and received increasingly more attention. Efficiently recovering information from large-scale DNA strands that suffer from insertions, deletions, and substitution errors (collectively referred to as edit errors), is one of the major bottlenecks in DNA-based
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ReaLPrune: ReRAM Crossbar-Aware Lottery Ticket Pruning for CNNs IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2022-11-28 Biresh Kumar Joardar, Janardhan Rao Doppa, Hai Li, Krishnendu Chakrabarty, Partha Pratim Pande
Training machine learning (ML) models at the edge (on-chip training on end user devices) can address many pressing challenges including data privacy/security, increase the accessibility of ML applications to different parts of the world by reducing the dependence on the communication fabric and the cloud infrastructure, and meet the real-time requirements of AR/VR applications. However, existing edge
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Bitwise Signature Comparison: Enabling More Efficient Similarity Estimation IEEE Trans. Emerg. Top. Comput. (IF 5.9) Pub Date : 2022-11-17 Pedro Reviriego, Salvatore Pontarelli, Jorge Martínez
Estimating the similarity of sets of data is a common operation in computing. Minhash is widely used to estimate similarity by computing a signature for each set and then comparing their signatures. Therefore, signature comparison is an important part of similarity estimation. To make the comparison efficient, the size of the signature components is commonly set to the word size of the processor or