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Pioneering Fast and Safe Low-k Silicon Dioxide Synthesis for Modern Integrated Circuits IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2024-03-07 Yu-Ting Chow, Shou-Yen Chao, Pei-Cheng Jiang, Chung-Tzu Chang, Mei-Yuan Zheng, Mu-Chun Wang, Cheng-Hsun-Tony Chang, Chii-Ruey Lin, Chia-Fu Chen, Kuo-Wei Liu
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Experts in the Loop: Conditional Variable Selection Based on Deep Learning for Accelerating Post-Silicon Validation IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2024-03-06 Yiwen Liao, Raphaël Latty, Bin Yang
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Fabrication of the Highly Ordered Silicon Nanocone Array With Sub-5 nm Tip Apex by Tapered Silicon Oxide Mask IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2024-03-04 Aixi Pan, Chenxu Zhu, Zheng Yan, Xiaoli Zhu, Zhongyi Liu, Bo Cui
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A Lightweight Chip-Scale Chemical Mechanical Polishing Model Based On Polynomial Network IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2024-02-26 Ruian Ji, Rong Chen, Lan Chen
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Eco-Friendly Dry-Cleaning and Diagnostics of Silicon Dioxide Deposition Chamber IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2024-02-14 Surin An, Jeong Eun Choi, Ju Eun Kang, Jiseok Lee, Sang Jeen Hong
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Editorial IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2024-02-05 Reha Uzsoy
As we enter a New Year, we can look back on another year of solid accomplishment at IEEE Transactions on Semiconductor Manufacturing. I am happy to report that our impact factor remains steady at 2.70, and our mean time to first decision remains competitive at 8.3 weeks. Our Editorial Board remains as strong as ever, with the addition of Dr. Jun-Haeng Lee in the area of machine learning and data science
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Curvilinear Standard Cell Design for Semiconductor Manufacturing IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2024-02-06 Ryoung-han Kim, Soobin Hwang, Apoorva Oak, Yasser Shirazi, Hsinlan Chang, Kiho Yang, Gioele Mirabelli
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IEEE Transactions on Semiconductor Manufacturing Information for Authors IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2024-02-05
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IEEE Transactions on Semiconductor Manufacturing Publication Information IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2024-02-05
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Call for Papers for IEEE Transactions on Materials for Electron Devices IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2024-02-05
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Editorial IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2024-02-05 Jeanne P. Bickford, Dragan Djurdjanovic, Mahadeva Iyer Natarajan
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SnS₂ and ZnO Nanocomposite Prepared by Dispersion Method for Photodetector Application IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-12-27 Ajay Kumar Dwivedi, Satyabrata Jit, Shweta Tripathi
This letter reports a SnS2 and ZnO nanocomposite (NC) prepared by dispersion method. The nanocomposite shows promising characteristics for optoelectronic application. SnS2:ZnO NC shows a wide absorption spectrum covering ultraviolet (UV)-visible-near infrared (NIR) regions. Hence, using the proposed nanocomposite a broadband photodetector with a structure comprising Al/ SnS2:ZnO/PEDOT:PSS/ Indium Tin
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Integrated Scheduling of Jobs, Tools, Machines, and Two Different Set of Transbots IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-12-15 Andy Ham, Myoung-Ju Park, John Fowler
This paper studies simultaneous scheduling of production and material transfer that arises in the semiconductor photolithography area. In particular, the right reticle and right job both need to be present to process the job. Jobs are transferred by a material handling system that employees a fleet of vehicles. Reticles serving as an auxiliary resource are also transferred from one place to another
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A Unified Machine Learning Through Focus Resist 3-D Structure Model IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-12-06 Mingyang Xia, Yan Yan, Chen Li, Xuelong Shi
To ensure post OPC data quality, examination based on estimated resist contours at resist bottom alone is insufficient, reliable prediction of lithography performance within process window must rely on complete information of on-wafer resist 3D structures. In this regard, resist 3D structure model, in particular, the through focus resist 3D structure model, with full chip capability will be the ultimate
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A Model Averaging Prediction of Two-Way Functional Data in Semiconductor Manufacturing IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-12-06 Soobin Kim, Youngwook Kwon, Joonpyo Kim, Kiwook Bae, Hee-Seok Oh
This paper proposes a linear regression model for scalar-valued responses and two-way functional (bivariate) predictors. Our motivation stems from the quality evaluation of products based on optical emission spectroscopy data from virtual metrology of semiconductor manufacturing. We focus on multivariate cases where the smoothness and shapes of the data vary significantly across variables. We propose
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Machine Learning on Multiplexed Optical Metrology Pattern Shift Response Targets to Predict Electrical Properties IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-12-05 Thomas J. Ashby, Vincent Truffert, Dorin Cerbu, Kit Ausschnitt, Anne-Laure Charley, Wilfried Verachtert, Roel Wuyts
Doing high throughput high accuracy metrology in small geometries is challenging. One approach is to build easily measurable proxy targets onto dies and make a predictive model based on those signals. We use optical Pattern Shift Response (PSR) proxy targets to build predictive models of the electrical characteristics of devices in the Back End Of Line (BEOL). Given the wide choice of PSR targets,
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Coherent Fourier Scatterometry for Detection of Killer Defects on Silicon Carbide Samples IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-11-29 Jila Rafighdoost, Dmytro Kolenov, Silvania F. Pereira
It has been a widely growing interest in using silicon carbide (SiC) in high-power electronic devices. Yet, SiC wafers may contain killer defects that could reduce fabrication yield and make the device fall into unexpected failures. To prevent these failures from happening, it is very important to develop inspection tools that can detect, characterize and locate these defects in a non-invasive way
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Practical Reinforcement Learning for Adaptive Photolithography Scheduler in Mass Production IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-11-28 Eungjin Kim, Taehyung Kim, Dongcheol Lee, Hyeongook Kim, Sehwan Kim, Jaewon Kim, Woosub Kim, Eunzi Kim, Younggil Jin, Tae-Eog Lee
This work introduces a practical reinforcement learning (RL) techniques to address the complex scheduling challenges in producing Active Matrix Organic Light Emitting Diode displays. Specifically, we focus on autonomous optimization of the photolithography process, a critical bottleneck in the fabrication. This provides an outperforming scheduling method compared with the existing rule-based approach
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Single-Mask Fabrication of Sharp SiOx Nanocones IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-11-28 Eric Herrmann, Xi Wang
The patterning of silicon and silicon oxide nanocones onto the surfaces of devices introduces interesting phenomena such as anti-reflection and super-transmissivity. While silicon nanocone formation is well-documented, current techniques to fabricate silicon oxide nanocones either involve complex fabrication procedures, non-deterministic placement, or poor uniformity. Here, we introduce a single-mask
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GAGAN: Global Attention Generative Adversarial Networks for Semiconductor Advanced Process Control IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-11-15 Hsiu-Hui Hsiao, Kung-Jeng Wang
This paper addresses the quality control of the photolithography process in the semiconductor industry. Overlay errors in the process seriously affect the wafer yield, and cause the wafer to be forced to rework and affect the production efficiency of the equipment. We examine the current state of its process control, develop a novel overlay predict model, and verify the prediction results. This study
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Guest Editorial Special Section on Production-Level Artificial Intelligence Applications in Semiconductor Manufacturing IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-10-30 John W. Fowler, Karl Kempf, Lars Mönch
The increasing availability of data, advances in computational and storage capacities of IT systems, and algorithmic advances in Artificial Intelligence (AI), especially Machine Learning (ML) combine to enable significant improvements in the efficiency, operations and throughput of manufacturing systems at the production level. The semiconductor industry is one of the most data-intensive industries
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Guest Editorial Special section on the 2022 International Symposium on Semiconductor Manufacturing IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-10-30 Tsuyoshi Moriya
Since its beginning in 1992 in Japan, International Symposium on Semiconductor Manufacturing (ISSM) has provided unique opportunities to share the best practices of semiconductor manufacturing technologies for professionals. At the symposiums, semiconductor manufacturing professionals discussed the technologies developed to meet the worldwide requirements for advanced manufacturing. It is becoming
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A Novel Multiscale Residual Aggregation Network-Based Image Super-Resolution Algorithm for Semiconductor Defect Inspection IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-10-26 Yang Liu, Lilei Hu, Bin Sun, Can Ma, Jingxuan Shen, Chang Chen
Single-image super-resolution (SISR) techniques have found wide applications in semiconductor defect inspection. Enhancing image resolution to improve inspection sensitivity and accuracy holds great significance. A novel SISR algorithm, called cross-convolutional residual network (CCRN), is proposed in this study. CCRN comprises a cross-convolutional module (CCM), which incorporates a cross-sharing
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Hotspot Prediction: SEM Image Generation With Potential Lithography Hotspots IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-10-26 Jaehoon Kim, Jaekyung Lim, Jinho Lee, Tae-Yeon Kim, Yunhyoung Nam, Kihyun Kim, Do-Nyun Kim
Since the invention of transistors and integrated circuits, the development of semiconductor processes has advanced rapidly. Current microchips contain hundreds of millions of transistors. The remarkable development of semiconductors thus far has also led to difficulties in designing tightly packed lithography patterns without unwanted defects called hotspots in the manufacturing process. Therefore
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Learning Priority Indices for Energy-Aware Scheduling of Jobs on Batch Processing Machines IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-10-24 Daniel Sascha Schorn, Lars Mönch
A scheduling problem for parallel batch processing machines (BPMs) with jobs having unequal ready times in semiconductor wafer fabrication facilities (wafer fabs) is studied in this paper. A blended objective function combining the total weighted tardiness (TWT) and the total electricity cost (TEC) under a time-of-use (TOU) tariff is considered. A genetic programming (GP) procedure is designed to automatically
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Gas-Delivery Fluid-Mechanical Timescales in Semiconductor Manufacturing IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-10-24 E. Gonzalez-Juez
Semiconductor manufacturing demands a fast delivery of multiple gases to the tool. Hence this document provides formulas for the fluid-mechanical timescales of this delivery. This is done with a simple but realistic model of a gas-supply system, together with theory and computational-fluid-dynamic (CFD) simulations, and for representative but not comprehensive conditions relevant to etch. This timescale
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Production-Level Artificial Intelligence Applications in Semiconductor Supply Chains IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-10-13 Chen-Fu Chien, Hans Ehm, John W. Fowler, Karl G. Kempf, Lars Mönch, Cheng-Hung Wu
This is a panel paper that discusses the use of Artificial Intelligence (AI) technologies to address production and supply chain level problems in semiconductor manufacturing. We have gathered a group of expert semiconductor researchers and practitioners from around the world who have developed AI solutions for various semiconductor problems. This paper aims to provide their answers to an initial set
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Multi-Scale and Multi-Branch Transformer Network for Remaining Useful Life Prediction in Ion Mill Etching Process IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-10-12 Zengwei Yuan, Rui Wang
Accurate prediction of the remaining useful life (RUL) of an ion mill is vital for optimizing the overall performance of the ion mill etching (IME) process. However, due to the uneven distribution of important information, and the poorly understood failure mechanisms, fault prognosis in this process presents significant challenges. Deep neural networks have shown promising results for extracting, without
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Semantic Context Information Modeling With Neural Networks in Customer Order Behavior Classification IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-10-06 Philipp Ulrich, Nour Ramzy, Marco Ratusny
Demand planning in the semiconductor industry can be complicated due to challenges such as extended cycle times, rapid innovation cycles, and the Bullwhip Effect. Approaches that provide a deeper understanding of customer orders and their associated demand are crucial to enhance demand planning accuracy. Previous studies have employed convolutional neural networks (CNNs) on heat map representations
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Equipment Condition Monitoring of Multiple Oxide-Nitride Stack Layer Deposition Process IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-09-28 Min Ho Kim, Sang Jeen Hong
For the 3D NAND memory, the higher oxide/nitride (ON) stacked dielectric is preferred to enhance the storage capacity, and multi-layer dielectric requirements, such as thickness uniformity and interfacial smoothness between films, gathers more interest for the performance of 3D NAND flash memory. Unsatisfactory thickness uniformity between layers is a challenge not only for the device performance but
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Stochastic Scheduling for Batch Processes With Downstream Queue Time Constraints IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-09-20 Wen-Chi Chien, Ywh-Leh Chou, Cheng-Hung Wu
This research studies the problems of stochastic dynamic scheduling in production systems with batch processes and process queue time (PQT) constraints. The production systems consist of upstream batch processing machines and downstream single processing machines. Under the PQT constraint, waiting time in the downstream queue is constrained by an upper limit and violating this constraint causes scraps
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Leveraging Machine Learning for Capacity and Cost on a Complex Toolset: A Case Study IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-09-12 Adar A. Kalir, Sin Kit Lo, Gavan Goldberg, Irena Zingerman-Koladko, Aviv Ohana, Yossi Revah, Tsvi Ben Chimol, Gavriel Honig
In this case study, we introduce two ML techniques, Long Short-Term Memory (LSTM) and an optimized Random Forest (RF), to address challenges related to capacity and cost, by addressing problems of unscheduled downtime and Process Time (PT) variation in the case of a complex chamber processing tool. We show that by using these ML techniques, traditional methods of Predictive Maintenance (PdM) and PT
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Impact of Annealing Temperature on MnO2 Thin Films: Morphological, Structural, and Electrical Properties IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-09-04 Stacy A. Lynrah, Lim Ying Ying, P. Chinnamuthu
Deposition of the manganese dioxide (MnO2) Thin Film (TF) was carried out by Electron beam (E-beam) evaporation technique. Structural, optical, and electrical characteristics reveal that MnO2 undergoes a phase transformation due to annealing temperature. Photoluminescence (PL) emission reveals the highest intensities at 500°C, indicating the least density of defects present in the sample. Moreover
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Defect Localization Approach for Wafer-to-Wafer Hybrid Bonding Interconnects IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-09-04 Kristof J. P. Jacobs, Eric Beyne
A high-resolution frontside fault isolation methodology for the analysis of wafer-to-wafer (W2W) hybrid bonding interconnects in three-dimensional integration is reported. The approach utilizes the visible light optical beam induced resistance change (VL-OBIRCH) method and incorporates a localized substrate removal technique, eliminating the need for a costly backside approach that requires a solid
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Fast Optical Proximity Correction Using Graph Convolutional Network With Autoencoders IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-08-21 Gangmin Cho, Taeyoung Kim, Youngsoo Shin
OPC is a very time consuming process for mask synthesis. Quick and accurate OPC using GCN with layout encoder and mask decoder is proposed. (1) GCN performs a series of aggregation with MLP for correction process. A feature of a particular polygon is aggregated with weighted features of neighbor polygons; this is a key motivation of using GCN since one polygon should be corrected while its neighbors
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Discrete Active Disturbance Rejection Control for Semiconductor Manufacturing Processes With Dynamic Models IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-08-14 Haiyan Wang, Tianhong Pan, Guochu Chen
The carry-over effect is a common phenomenon in the semiconductor manufacturing process, giving the process a dynamic nature. Dynamic models are more accurate but with a consequent increase in uncertainty. Therefore, it is very important to eliminate the uncertainty and disturbance at the same time. To this end, a run-to-run (RtR) control scheme based on discrete active disturbance rejection control
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Scheduling a Real-World Photolithography Area With Constraint Programming IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-08-11 Patrick Deenen, Wim Nuijten, Alp Akcay
This paper studies the problem of scheduling machines in the photolithography area of a semiconductor manufacturing facility. The scheduling problem is characterized as an unrelated parallel machine scheduling problem with machine eligibilities, sequence- and machine-dependent setup times, auxiliary resources and transfer times for the auxiliary resources. Each job requires two auxiliary resources:
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Guest Editorial Special Section on the 2022 SEMI Advanced Semiconductor Manufacturing Conference IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-08-04 Jeanne Paulette Bickford, Oliver D. Patterson, Delphine Le Cunff, Ralf Buengener, Stefan Radloff, Paul Werbaneth
The 2022 ASMC, our 33rd, returned to Saratoga Springs, NY as an in-person conference after 2 years as a virtual conference. While we are all grateful for the digital world’s enhancements that allowed this conference to be held remotely, attendees were happy to return to an in-person event where networking is much easier.
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Thermal and Electrical Analysis of the Electrostatic Chuck for the Etch Equipment IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-08-02 Tae Woong Yoon, Minsuk Choi, Sang Jeen Hong
One of the most important parts of semiconductor etch tools is the electrostatic chuck (ESC), which ensures secure wafer holding during fabrication and uniform temperature distribution from center to perimeter of the wafer during plasma etching. In this study, we investigated the thermal and electrical analysis of the ESC to ensure the temperature uniformity of the wafer via analytical multi-physics
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Improvement of Plasma Etching Endpoint Detection With Data-Driven Wavelength Selection and Gaussian Mixture Model IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-07-14 Chae Sun Kim, Hye Ji Lee, Hae Rang Roh, Taekyoon Park, Yongseok Lee, Jewoo Han, Sungun Kwon, Chanmin Lee, Jongwoo Sun, Kukhan Yoon, Jong Min Lee
The signal-to-noise ratio of optical emission spectroscopy (OES) data has decreased as the plasma etching process has advanced. As a result, not only the advanced endpoint detection method was required, but also the selection of more informative wavelengths. This paper proposes an improved endpoint detection algorithm by combining data-driven wavelength selection and a Gaussian mixture model (GMM)
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Spatial and Channel-Wise Co-Attention-Based Twin Network System for Inspecting Integrated Circuit Substrate IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-06-26 Eunjeong Choi, Jeongtae Kim
We propose a deep learning-based reference comparison system based on a twin network (also known as a Siamese network) for high-performance inspection of integrated circuit (IC) substrates. However, reference comparison-based inspection methods may suffer from false positives when inspecting image pairs with variations, such as mis-registration and color changes. To address these problems, we also
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Advanced Process Control System for Trench Shape of Power Devices IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-06-14 Takumi Ito, Wang Xueting, Yasuhisa Oomuro, Kazutaka Nagashima
In the semiconductor manufacturing, the manufacturing equipment is managed via the quality control (QC) in which the shape of the processed feature is checked whether it meets the specification. If the shape is out of the specification, some recipe parameters are modified so that the shape meets the specification. The calculation method of the recipe parameters depends on the know-how of the individual
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Effect of SiO2 Interfacial Layer Reduction on MFSFET With 5 nm-Thick Ferroelectric Nondoped HfO2 by Deposition Rate Control IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-06-12 Shun-ichiro Ohmi, Masakazu Tanuma, Joong-Won Shin
In this research, deposition rate dependence of 5 nm-thick ferroelectric nondoped HfO2 (FeND-HfO2) formed on Si(100) substrate was investigated. The equivalent oxide thickness (EOT) was decreased from 3.2 nm to 2.8 nm by increasing deposition rate of HfO2 from 5.0 nm/min to 6.0 nm/min. The subthreshold swing (SS) of 107 mV/dec. and saturation mobility $(\mu _{\mathrm{ sat}})$ of 150 cm 2/(Vs) were
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Virtual Metrology Modeling for Wafer Edges via Graph Attention Networks IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-06-12 Jaehyeon Joo, Keun Woo Yang, Yeoung Je Choi, Byungwook Min, Chang Ouk Kim
Quality monitoring is an essential element of defect detection in semiconductor manufacturing processes, but semiconductor companies use virtual metrology (VM) in addition to actual metrology to prevent productivity degradation due to the time and costs required to obtain measurements. Past VM studies aimed to predict average wafer measurement values via equipment sensor data and focused on achieving
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Novel Control Method and Applications for Negative Mode E-Beam Inspection IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-06-09 Oliver D. Patterson, Datong Zhang, Ralf Buengener, Guanchen He, Yufei Duan, Joy Chu, Brian Sheumaker
E-beam voltage contrast inspection is a very common method for in-line detection of many key defect types for rapid yield learning during technology development. Generally, the wafer surface is charged positive, but sometimes charging the wafer surface negative makes more sense. This paper reviews four advantages that negative charging may provide. Switching from positive to negative charging is typically
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Yield Methodology and Heater Process Variation in Phase Change Memory (PCM) Technology for Analog Computing IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-06-08 Victor Chan, A. Gasasira, R. Pujari, W.-T. Tseng, T. Gordon, R. Southwick, I. Ok, S. Choi, C. Silvestre, H. Utomo, K. Brew, T. Philip, G. W. Burr, N. Saulnier, S. Teehan, I. Ahsan
We discuss inline electrical testing to monitor the baseline of Analog Computing hardware using Phase Change Memory (PCM) technology. Tightening the PCM resistance distribution is necessary to meet analog computation requirement. A new yield methodology is introduced. A study of heater process variation, which will affect the heater height and the PCM resistance, will be discussed.
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Wafer-to-Wafer Bonding Fabrication Process-Induced Wafer Warpage IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-06-08 Wei Feng, Haruo Shimamoto, Tsuyoshi Kawagoe, Ichirou Honma, Masato Yamasaki, Fumitake Okutsu, Takatoshi Masuda, Katsuya Kikuchi
Wafer warpage affects the resolution of photolithography, process alignment, and wafer bonding, which leads to the degradation of the device’s yield, performance, and reliability. With the development of devices, the increase of metal layers in the stack direction will worsen the warpage problem. We investigate the Wafer-to-Wafer (W2W) bonding process-induced warpage issue with experiments and a full
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Prediction of Highly Imbalanced Semiconductor Chip-Level Defects in Module Tests Using Multimodal Fusion and Logit Adjustment IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-06-05 Hunsung Cho, Wonmo Koo, Heeyoung Kim
The memory module is a semiconductor product fabricated by mounting several memory chips on a printed circuit board. In the module test, which is the final step in the memory module manufacturing process, the memory module is tested if it properly functions in the end-user system environment. Then, the chips in the memory module are individually checked for defects to guarantee that the quality matches
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Optimization of RF Frequencies in Dual-Frequency Capacitively Coupled Plasma Apparatus Using Genetic Algorithm (GA) and Plasma Simulation IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-06-02 Shigeyuki Takagi, Makoto Sekine, Tatsuhiro Nakaegawa, Shih-Nan Hsiao
As a method to optimize the power frequency of dual-frequency plasma, we propose an optimization method that combines genetic algorithm and plasma simulation. A two-dimensional plasma simulation model of Ar plasma was constructed with a fluid model. Combining this simulation model with a genetic algorithm, 300 cases of plasma conditions with high plasma density and small variation in electron density
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Automatic Classification of C-SAM Voids for Root Cause Identification of Bonding Yield Degradation IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-06-02 Julien Baderot, Solange Garrais, Sergio Martinez, Johann Foucher, Ryuji Eto, Kazumasa Tanida, Takatoshi Yasui, Tomoya Tanaka
Wafer-level direct bonding technology is a key process for the production of backside illuminated (BSI) CMOS image sensor (CIS). Usually, constant-depth mode scanning acoustic microscope (C-SAM) 300mm wafer images are acquired and defect size distribution is provided to monitor defects that degrade bonding yield. This acquisition technique is used as it is nondestructive and is able to capture the
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Supply Chain Planning for IC Design House Back-End Production Network With Turnkey Service IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-05-30 James C. Chen, Tzu-Li Chen, Wei-Chen Huang, Peter Peng, Tony Lin
Owing to global competition, integrated circuit (IC) design houses are facing challenges in the optimal use of capacity and resources to fulfill customer demands and maximize profit. A hybrid make-to-stock (MTS) and make-to-order (MTO) model is generally used. Wafer procurement is made according to customers’ long-term demand forecast based on MTS. Limited wafer fab resources and back-end capacity
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Automated Visual Inspection of Defects in Transparent Display Layers Using Light-Field 3-D Imaging IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-05-30 Hyeonjoong Jang, Sanghoon Cho, Daniel S. Jeon, Dahyun Kang, Myeongho Song, Changhyun Park, Jaewon Kim, Min H. Kim
Since a display panel comprises multiple layered components, defects may occur within different layers through manufacturing processes. Traditional visual inspection systems with a 2D camera cannot identify the occurrence location among layers. Several 3D imaging technologies, such as CT, TSOM, and MRI, suffer from slow performance and a large form factor. In this work, we propose a novel visual inspection
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SWaCo: Safe Wafer Bin Map Classification With Self-Supervised Contrastive Learning IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-05-29 Min Gu Kwak, Young Jae Lee, Seoung Bum Kim
Defect patterns exhibited in wafer bin maps (WBMs) can provide essential clues about critical process failures to field engineers. In modern manufacturing processes, the automatic WBM defect pattern classification is critical for yield improvement. Although it is difficult to collect sufficient labels while a lot of unlabeled data is given, most existing studies have mainly used only labeled WBM data
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Automatic Defect Classification Using Semi-Supervised Learning With Defect Localization IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-05-19 Yusung Kim, Jin-Seop Lee, Jee-Hyong Lee
Automatic defect classification (ADC) systems automatically classify defects that inevitably occur during semiconductor manufacturing processes. ADC is the beginning of defect management that increases the yield of semiconductor chip production, and prevents accidents in the process. It takes a lot of engineer’s labor to classify defects, but ADC can be the answer to classify all defects at low cost
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Data-Driven Production Planning Models for Wafer Fabs: An Exploratory Study IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-05-17 Tobias Völker, Lars Mönch
Cycle time, which is of order of ten weeks for most products in semiconductor wafer fabrication facilities (wafer fabs), must be explicitly considered in production planning models. Cycle times depend nonlinearly on the resource workload in a wafer fab. Different data-driven (DD) production planning formulations are studied in this paper. Such formulations are based on a set of system states representing
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Self-Assured Deep Learning With Minimum Pre-Labeled Data for Wafer Pattern Classification IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-05-16 Shu-Kai S. Fan, Du-Ming Tsai, Ya-Fang Shih
Data quality plays an important role during the training stage of machine/deep learning models. The annotation hinges on the experiences of domain experts. To acquire the expert’s knowledge in the context of machine learning, manual data labeling, a tedious and time-consuming task in supervised learning, should be given a top priority. However, the domain experts in the line of plentiful manual annotation
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Enabling the Use of High-Precision Glass Wafers in a Conventional Si Fab IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-05-15 Jay Zhang, Chee-Hau Ng, Sebastien Kouassi
Glass has unique properties that make it attractive for many applications. Combining glass with Si fabrication process would create new possibilities not only in device performance and form factor, but also scale economies. Key challenges in using glass wafers in a Si fab include lack of opacity and electrical conductivity as well as metallic and particle contamination. These challenges can be overcome
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Defect 3-D Profile Estimation Using SEM Images IEEE Trans. Semicond. Manuf. (IF 2.7) Pub Date : 2023-05-12 Shashank S. Agashe, Gaurav Kumar, Sathyanarayanan Kulasekaran, Yunje Cho
In semiconductor wafer manufacturing process, the height of random defects provides an important physical parameter to understand their impact and root cause. In this work, we demonstrate a novel method of defect height estimation based on SEM images without using ground truth or any external reference data of target defect types. Our method is applicable in conditions such as absence of shadows, self-obstruction