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Dear readers—We hope this editorial finds you and your family safe as we and the world battle—or, hopefully at the time of this publication, recover from—perhaps the greatest world-wide health crisis in the last century, COVID-19. Fortunately, the contributions of our semiconductor manufacturing industry over the last 40 years have put us in a much more comfortable position than those who faced past

For a recent replacement metal gate (RMG) FINFET technology using an SOI substrate, an inhomogeneous polish post Tungsten fill of the RMG was discovered. For particular wide-gate structures, the Tungsten polish within the reticle field and across the wafer varied widely despite being in control using the established kerf metrology structure. This was discovered after the technology had been ramped

Overlay metrology is crucial to process control in manufacturing semiconductor devices. Diffraction-based overlay (DBO) is an effective overlay measurement approach because it exhibits multiple advantages. This study analyzed measurement errors caused by sidewalls in the bottom gratings of DBO targets. Accordingly, improvement was proposed using a neural network. First, rigorous coupled wave analysis

In thin-film transistor liquid crystal display (TFT-LCD) manufacturing, the automatic recognition and classification of defects can help manufacturers monitor abnormalities, identify potential process problems, and swiftly respond to these process problems. Thus, yield loss can be reduced. However, capturing the content displayed on screen using cameras is challenging because it is often contaminated

To improve overlay and focus errors in lithographic applications, an active wafer clamp (AWC) concept is proposed. Using this concept, mechanical actuators deform the wafer to compensate thermally induced deformations. In [1] a localized feedforward (FF) control algorithm for the AWC concept was introduced. In this paper we aim to improve this algorithm and discuss practical implications for the design

The chemical mechanical polishing (CMP) process usually suffers from drift and shift in the Run-to-Run material removal process due to the wear and replacement of the polishing pad, lacking of in-suit measurements of the product quality of interest and other environment variations. This paper proposed a deep reinforcement learning (DRL)-based run-to-run (R2R) controller for the CMP process. Firstly

In semiconductor manufacturing, several measurement data called wafer maps are obtained in the metrology steps, and the variations in the process are detected by analyzing the wafer map data. Hidden processes or equipment affecting the process quality variations can be found by comparing the process tracking history and clustered groups of similar wafer maps; thus, clustering analysis is very important

Multi-cluster tools are widely used in semiconductor manufacturing. When the lot size of wafers tends to be quite small, a cyclic scheduling strategy is not suitable. However, the noncyclic scheduling of multi-cluster tools is much more challenging due to multi-robot coordination and the increasing number of chambers. This paper focuses on the noncyclic scheduling problem of multi-cluster tools with

With reduction in the die sizes it is very critical to control the Critical Dimension (CD) within a very precise window. In this work we present a root cause analysis and solution to a bimodal CD distribution seen from the center of the wafer. The CD bimodality displays a sharp cliff at the center of the wafer, wherein one side of the wafer has the higher CD and the other side has lower CD with respect

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In this paper, we present a system for the detection and classification of defects in semiconductor units. The proposed system consists of three stages: proposal generation stage, defect detection stage and refinement stage. In the proposal generation stage, changes on the target unit are detected using a novel change detection approach. In the second stage, a deep neural network is used to classify

Quality inspection in semiconductor manufacturing is of great importance in the modern industries. In the recent years, intelligent data-driven condition monitoring methods have been successfully developed and applied in the industrial applications. However, despite the promising condition monitoring performance, the existing methods generally assume the training and testing data are from the same

Wafer maps contain information about various defect patterns on the wafer surface and automatic classification of these defects plays a vital role to find their root causes. Semiconductor engineers apply various methods for wafer defect classification such as manual visual inspection or machine learning-based algorithms by manually extracting useful features. However, these methods are unreliable,

With the rapidly increasing test time of semiconductor testing, the trend is currently toward improving test parallelism by exploiting multi-site testing. However, excessive test I/O channels and test power consumption lead to the degradation of multi-site testing efficiency owing to the limited number of tester I/Os and power capacity. In this paper, we present an advanced low pin count test architecture

Demand for products of dynamic random-access memory (DRAM) has dramatically increased since 2019. To satisfy the soaring demand, many companies have increased their supply for DRAM products. The DRAM CoSi 2 resistance significantly affects the quality of a DRAM product. The case company under this study suffered from deviations of the CoSi 2 resistances of its DRAM products from a target value of 11

The spatial failure patterns in wafer defect maps can be related to problems in the manufacturing and test process. Therefore, failure pattern recognition can be used for root cause analysis, which is very important for defect diagnosis resolution improvement and yield learning. However, previous studies show that wafers with recognizable failure patterns only account for a small part of all defective

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The world is a rather different place now than it was last November, when I wrote the last of these editorials. As we deal with the worldwide economic slowdown, social distancing and the other consequences of the Covid-19 pandemic, I am grateful to all members of the TSM community who continue to work under trying conditions to keep the journal’s business going.

As a guest Editor for the special section on the 2017, 2018, and 2019 International Conference on Microelectronic Test Structures (ICMTS), I am gratified to be able to present our IEEE Transactions on Semiconductor Manufacturing readers with a selection of papers based on work presented at the 2017, 2018, and 2019 conferences.

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Ti, Co, Pt, and Ni salicide processes optimized for a range of CMOS technology nodes down to 90nm were fabricated using 0.35 $\mu {\mathrm{ m}}$ SiGe BiCMOS. On-wafer circuitry was used to program discrete eFuse elements to compare their pre and post programmed resistances as well as their behavior during programming between each salicide process employed, with TEM analysis to confirm successful electromigration

We show how a CD-TEM (Critical Dimension-Transmission Electron Microscope) can be used to acquire EDS (Energy Dispersive X-ray Spectroscopy) tomograms, which allow chemical mapping in 3D for most elements in the sample. This is achieved by developing a recipe using ordinary commands also used in CD-TEM programming. In addition, we demonstrate how detector shadowing can be reduced significantly by using

This paper reports results of a study on copper voids seen in a back end of line (BEOL) module. The experiment was designed to study the effect of multiple parameters that can influence the occurrence of voids and their process margins. This work also reports the effect of changes in copper seed thickness on the product’s lifetime and reliability.

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We study the performance of production planning models for wafer fabs in a rolling horizon setting under stochastic demand modeled using the Martingale Model of Forecast Evolution (MMFE). The models differ in how they incorporate lead times and safety stocks. The number of frozen periods is considered as an experimental factor to study the nervousness of the resulting plans. Our simulation experiments

Recently, the transportation capability of the automated material handling system (AMHS) has emerged as a major barrier to the semiconductor fabrication facility (FAB), because it can limit the FAB production capacity. In this study, we propose a prediction method for a machine allocation problem of production scheduling in consideration with the AMHS's constraints. The proposed method dynamically

As extreme ultraviolet (EUV) lithography enters high volume manufacturing (HVM) to enable the sub-7nm scaling roadmap, characterizing and monitoring defects that print at wafer level are of critical importance to yield. This is especially true for defects coming from the EUV mask, due to multi-layer defects or added particles or growth on mask during its use, and for defects coming from the pattern

One of the main issues of EUV lithography is Line Edge Roughness (LER) on photo-resists, which significantly impacts yield at sub-30 nm pitches. In this work, an analytical model of LER is presented and analyzed for yield loss induced by open/short failures, cut mask defects, enhanced time dependent dielectrics breakdown (TDDB) failures for metal wires with different geometries, electro-migration (EM)

Process windows based on Mean CD (“Critical Dimension”) have been an analysis workhorse for estimating and comparing the robustness of semiconductor microlithography processes for more than 30 years. While tolerances for variation of CD are decreasing in step with the target CD, the acceptable number of printed defects has remained flat (Hint: Zero) even as the number of features increases quadratically

Overlay modeling, which predicts and corrects the overlay errors of wafers in the photolithography process, is emerging as a key technology for yield improvement. An overlay error is defined as a misalignment between the circuit images of the current and preceding exposure layers. Overlay modeling is classified into wafer-level modeling, which creates a single regression equation to correct the overlay

Wafer map analysis provides critical information for quality control and yield improvement tasks in semiconductor manufacturing. In particular, wafer patterns of gross failing areas (GFA) are important clues to identify the causes of relevant failures during the manufacturing process. In this work, a semi-supervised classification framework is proposed for wafer map analysis, and its application to

Manual classification of particle defects on semiconductor wafers is labor-intensive, which leads to slow solutions and longer learning curves on product failures while being prone to human error. This work explores the promise of deep learning for the classification of the chemical composition of these defects to reduce analysis time and inconsistencies due to human error, which in turn can result

For reasons of productivity and throughput maximization, semiconductor equipment suppliers provide multiple-chamber machines to allow the split of production runs over parallel chambers. These latter are expected to perform identically and fabricate similar product quality, which is not usually the case given the low margin of error allowed in the complex manufacturing environment. The difficulty lies

This paper deals with the modeling and control of thermo-mechanical deformations of a wafer, resulting from absorbed exposure power, in EUV lithography. To achieve correction of the induced deformations, an active wafer clamp concept is proposed. In this concept, between 1,000 and 30,000 actuators are incorporated into the electrostatic wafer clamp, such that forces can be applied directly onto the

Ultra-low-resistivity-silicon (ULRS) coaxial through-silicon-vias (TSVs) employ silicon pillar as the central conductor, which simplifies the fabrication process and exhibits good electrical characteristics. However, microcracks that may appear on silicon pillars degrade the reliability and electrical properties. In this work, the main cause of microcracks is investigated experimentally and an optimized

Second harmonic generation (SHG) characteristics of single and multilayer field-effect passivation (FEP) structures were investigated for CMOS image sensor application. By compensating the internal multiple reflection effect, the SHG characteristics of single and multilayer FEP structures were compared under equivalent conditions. Analysis of the time-dependent SHG intensity confirmed that the multilayer

Heat effects on femtosecond laser annealing to crystallize doped amorphous Si films are studied. The structural, optical and electronic properties of phosphorus-doped amorphous Si films before and after femtosecond laser treatment are characterized. As the temperature increases from room temperature to 200 °C controlled by a hot-stage, the grain size and number of crystalline Si on the films are gradually

This study used reduced graphene oxide (rGO) applied to a platinum (Pt) counter electrode to improve light conversion efficiency. The study also used an Al-doped Zinc Oxide (AZO) nanosheet/TiO 2 photoanode for the dye-sensitized solar cell (DSSC). Photovoltaic characteristics, electrochemical impedance spectroscopy (EIS), field-emission scanning electron microscopy (FE-SEM) and Raman spectroscopy were

The current market demands for thin-film transistor (TFT) liquid crystal display (LCD) is high; however, the LCD televisions still have contrast ratio-related issues. To resolve this, researchers conventionally use trial and error methods for parameter optimization and adjustment. However, this method is slow and can delay the development of new products. Therefore, this study focused on the high contrast

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This work presents a test structure targeted to measure MOSFET mismatches with a fast method. It relies on two single-spot voltage measurements in order to extract $\Delta V_{TH}$ and $\Delta \beta / \beta $ separately. The new methodology gives a theoretical increase in the measurement speed of 30x (23.17x in practice). The coefficient of determination ( $R^{2}$ ) of the linear regression analysis

With their capacity for real time monitoring and spatial mapping, implantable sensors are becoming an increasingly important aspect of next generation precision healthcare. Microfabricated sensor systems are a popular choice, owing to their capacity for miniaturisation, repeatable mass manufacture, and numerous pre-existing sensor archetypes. Despite the drive for development, packaging these sensors

The lifetime of organic thin-film transistors (OTFTs) is known to be significantly shorter than that of silicon MOSFETs. It is therefore important to be able to predict their degradation early in the design phase. In this paper, OTFT current characteristic variation is studied in measurements of fabricated devices. In addition, we propose a drain-current simulation model that incorporates temporal

In order to ensure safe and fast transportation of wafers in 300 mm semiconductor factories, overhead transport systems (OHT) are primarily used. These systems consist of a rail network and vehicles. To avoid congestion and delays in production, high availability of individual rail sections is essential. In order to ensure this extensive preventive maintenance is required. In this paper, we focus on

In this study, the zinc oxide (ZnO)-titanium dioxide (TiO 2 ) composite nanofiber (NF) is prepared and used as an additional layer between TiO 2 layer and electrolyte on the photoanode of dye-sensitized solar cells (DSSC) to improve the power conversion efficiency ( ${\eta }$ ). The various weight ratios of ZnO/TiO 2 in ZnO-TiO 2 NF are manufactured by electrospinning technique. The photovoltaic parameters

In this study, we investigate low frequency noise under the reverse body bias conditions from sub-threshold to moderate inversion regime, in order to experimentally extract the impact of depletion capacitance with the reverse body bias. From 1/ ${f}$ noise measurement for small-area conventional ${n}$ MOSFETs, the reverse body bias is not influenced on the coulomb scattering process, even though the

Nafion is a solid electrolyte polymer that can be used as a sensor membrane in microfabricated electrochemical oxygen sensors. It allows ions to be transported between the sensor electrodes and removes the need for a liquid electrolyte. Here we used a series of small square Nafion test structures, fabricated on a variety of materials using standard thin-film patterning techniques, to optimize the design

A high-speed measurement method has been developed to electrically determine the potential voltage of the permanent charge or electret formed in a MEMS (microelectromechanical systems) vibrational energy harvester. While the conventional admittance method requires long time to observe the waveforms of the output power in time domain that diminishes when the built-in electret potential is compensated

An on-chip micro-mechanical test structure is presented to investigate the tribological behavior of deep reactive ion etching (DRIE) sidewall surfaces of microelectromechanical systems (MEMS) devices. The proposed test structure is fabricated on silicon on insulator (SOI) wafer using a standard surface micromachine process. Test structure consists of two orthogonally placed electrostatic comb-drive