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The world is a rather different place now than it was last November, when I wrote the last of these editorials. As we deal with the worldwide economic slowdown, social distancing and the other consequences of the Covid-19 pandemic, I am grateful to all members of the TSM community who continue to work under trying conditions to keep the journal’s business going.

As a guest Editor for the special section on the 2017, 2018, and 2019 International Conference on Microelectronic Test Structures (ICMTS), I am gratified to be able to present our IEEE Transactions on Semiconductor Manufacturing readers with a selection of papers based on work presented at the 2017, 2018, and 2019 conferences.

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We study the performance of production planning models for wafer fabs in a rolling horizon setting under stochastic demand modeled using the Martingale Model of Forecast Evolution (MMFE). The models differ in how they incorporate lead times and safety stocks. The number of frozen periods is considered as an experimental factor to study the nervousness of the resulting plans. Our simulation experiments

Recently, the transportation capability of the automated material handling system (AMHS) has emerged as a major barrier to the semiconductor fabrication facility (FAB), because it can limit the FAB production capacity. In this study, we propose a prediction method for a machine allocation problem of production scheduling in consideration with the AMHS's constraints. The proposed method dynamically

As extreme ultraviolet (EUV) lithography enters high volume manufacturing (HVM) to enable the sub-7nm scaling roadmap, characterizing and monitoring defects that print at wafer level are of critical importance to yield. This is especially true for defects coming from the EUV mask, due to multi-layer defects or added particles or growth on mask during its use, and for defects coming from the pattern

One of the main issues of EUV lithography is Line Edge Roughness (LER) on photo-resists, which significantly impacts yield at sub-30 nm pitches. In this work, an analytical model of LER is presented and analyzed for yield loss induced by open/short failures, cut mask defects, enhanced time dependent dielectrics breakdown (TDDB) failures for metal wires with different geometries, electro-migration (EM)

Process windows based on Mean CD (“Critical Dimension”) have been an analysis workhorse for estimating and comparing the robustness of semiconductor microlithography processes for more than 30 years. While tolerances for variation of CD are decreasing in step with the target CD, the acceptable number of printed defects has remained flat (Hint: Zero) even as the number of features increases quadratically

Overlay modeling, which predicts and corrects the overlay errors of wafers in the photolithography process, is emerging as a key technology for yield improvement. An overlay error is defined as a misalignment between the circuit images of the current and preceding exposure layers. Overlay modeling is classified into wafer-level modeling, which creates a single regression equation to correct the overlay

Wafer map analysis provides critical information for quality control and yield improvement tasks in semiconductor manufacturing. In particular, wafer patterns of gross failing areas (GFA) are important clues to identify the causes of relevant failures during the manufacturing process. In this work, a semi-supervised classification framework is proposed for wafer map analysis, and its application to

Manual classification of particle defects on semiconductor wafers is labor-intensive, which leads to slow solutions and longer learning curves on product failures while being prone to human error. This work explores the promise of deep learning for the classification of the chemical composition of these defects to reduce analysis time and inconsistencies due to human error, which in turn can result

For reasons of productivity and throughput maximization, semiconductor equipment suppliers provide multiple-chamber machines to allow the split of production runs over parallel chambers. These latter are expected to perform identically and fabricate similar product quality, which is not usually the case given the low margin of error allowed in the complex manufacturing environment. The difficulty lies

This paper deals with the modeling and control of thermo-mechanical deformations of a wafer, resulting from absorbed exposure power, in EUV lithography. To achieve correction of the induced deformations, an active wafer clamp concept is proposed. In this concept, between 1,000 and 30,000 actuators are incorporated into the electrostatic wafer clamp, such that forces can be applied directly onto the

Ultra-low-resistivity-silicon (ULRS) coaxial through-silicon-vias (TSVs) employ silicon pillar as the central conductor, which simplifies the fabrication process and exhibits good electrical characteristics. However, microcracks that may appear on silicon pillars degrade the reliability and electrical properties. In this work, the main cause of microcracks is investigated experimentally and an optimized

Second harmonic generation (SHG) characteristics of single and multilayer field-effect passivation (FEP) structures were investigated for CMOS image sensor application. By compensating the internal multiple reflection effect, the SHG characteristics of single and multilayer FEP structures were compared under equivalent conditions. Analysis of the time-dependent SHG intensity confirmed that the multilayer

Heat effects on femtosecond laser annealing to crystallize doped amorphous Si films are studied. The structural, optical and electronic properties of phosphorus-doped amorphous Si films before and after femtosecond laser treatment are characterized. As the temperature increases from room temperature to 200 °C controlled by a hot-stage, the grain size and number of crystalline Si on the films are gradually

This study used reduced graphene oxide (rGO) applied to a platinum (Pt) counter electrode to improve light conversion efficiency. The study also used an Al-doped Zinc Oxide (AZO) nanosheet/TiO 2 photoanode for the dye-sensitized solar cell (DSSC). Photovoltaic characteristics, electrochemical impedance spectroscopy (EIS), field-emission scanning electron microscopy (FE-SEM) and Raman spectroscopy were

The current market demands for thin-film transistor (TFT) liquid crystal display (LCD) is high; however, the LCD televisions still have contrast ratio-related issues. To resolve this, researchers conventionally use trial and error methods for parameter optimization and adjustment. However, this method is slow and can delay the development of new products. Therefore, this study focused on the high contrast

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This work presents a test structure targeted to measure MOSFET mismatches with a fast method. It relies on two single-spot voltage measurements in order to extract $\Delta V_{TH}$ and $\Delta \beta / \beta $ separately. The new methodology gives a theoretical increase in the measurement speed of 30x (23.17x in practice). The coefficient of determination ( $R^{2}$ ) of the linear regression analysis

With their capacity for real time monitoring and spatial mapping, implantable sensors are becoming an increasingly important aspect of next generation precision healthcare. Microfabricated sensor systems are a popular choice, owing to their capacity for miniaturisation, repeatable mass manufacture, and numerous pre-existing sensor archetypes. Despite the drive for development, packaging these sensors

The lifetime of organic thin-film transistors (OTFTs) is known to be significantly shorter than that of silicon MOSFETs. It is therefore important to be able to predict their degradation early in the design phase. In this paper, OTFT current characteristic variation is studied in measurements of fabricated devices. In addition, we propose a drain-current simulation model that incorporates temporal

In this study, the zinc oxide (ZnO)-titanium dioxide (TiO 2 ) composite nanofiber (NF) is prepared and used as an additional layer between TiO 2 layer and electrolyte on the photoanode of dye-sensitized solar cells (DSSC) to improve the power conversion efficiency ( ${\eta }$ ). The various weight ratios of ZnO/TiO 2 in ZnO-TiO 2 NF are manufactured by electrospinning technique. The photovoltaic parameters

In this study, we investigate low frequency noise under the reverse body bias conditions from sub-threshold to moderate inversion regime, in order to experimentally extract the impact of depletion capacitance with the reverse body bias. From 1/ ${f}$ noise measurement for small-area conventional ${n}$ MOSFETs, the reverse body bias is not influenced on the coulomb scattering process, even though the

Nafion is a solid electrolyte polymer that can be used as a sensor membrane in microfabricated electrochemical oxygen sensors. It allows ions to be transported between the sensor electrodes and removes the need for a liquid electrolyte. Here we used a series of small square Nafion test structures, fabricated on a variety of materials using standard thin-film patterning techniques, to optimize the design

A high-speed measurement method has been developed to electrically determine the potential voltage of the permanent charge or electret formed in a MEMS (microelectromechanical systems) vibrational energy harvester. While the conventional admittance method requires long time to observe the waveforms of the output power in time domain that diminishes when the built-in electret potential is compensated

An on-chip micro-mechanical test structure is presented to investigate the tribological behavior of deep reactive ion etching (DRIE) sidewall surfaces of microelectromechanical systems (MEMS) devices. The proposed test structure is fabricated on silicon on insulator (SOI) wafer using a standard surface micromachine process. Test structure consists of two orthogonally placed electrostatic comb-drive

A resistance measurement platform for the statistical evaluation of emerging memory materials is presented. We developed two types of platforms, depending on the resistance range of memory materials. The high resistance (HR) measurement typemeasures the resistance of 490,000 cells in the range of 2.85 $\text{k}{\Omega }- 10\,\,\text{M}{\Omega }$ within 497 ms. The low resistance (LR)measurement type

Measuring bias temperature instability (BTI) by ring oscillators (ROs) is frequently used. However, the performance of a semiconductor chip is fluctuated dynamically due to bias, temperature and etc. BTI-sensitive and -insensitive ROs are implemented in order to extract BTI-induced degradation without temporal fluctuation factors. A test chip including those 840 ROs was fabricated in a 65 nm process

A set of comprehensive test patterns is important for a number of lithography applications. Pattern diversity is, however, hard to achieve either from parametric patterns or from actual patterns even though they are carefully extracted and classified. Automatic layout pattern synthesis is proposed in this paper. A generative adversarial network (GAN) is employed to generate a new set of discrete cosine

The measurement of the contact resistance ( $R_{C}$ ) in semiconductor devices relies on the well–established Transfer Length Method (TLM). However, an in–depth investigation on its applicability to characterize the metal–graphene contacts is still missing. In this work, a dependability analysis on the $R_{C}$ values extracted from several metal–graphene stacks is performed, also devising strategies

We consider the problem of determining an optimal release schedule for a production facility as it transitions from producing an older product to a newer one. We use simple queueing ideas to model the impact of the new product introduction on the throughput rate and cycle time of both products. We then incorporate the learning gained from accumulated experience in producing the new product to formulate

A highly effective moisture removal technique for front opening unified pods (FOUPs) can significantly improve the production yield of semiconductor manufacturing industries by minimizing the number of faulty dies rejected due to humidity related defects in silicon wafers. In this study, FOUP purging using clean dry air (CDA) was applied using conventional and diffuser purge method. An innovative laminar

Ultra-thin tungsten films were prepared using hotwire assisted atomic layer deposition. The film thickness ranged from 2.5 to 10 nm, as determined by spectroscopic ellipsometry and verified by scanning electron microscopy. The films were implemented in conventional Van der Pauw and circular transmission line method (CTLM) test structures, to explore the effect of film thickness on the sheet and contact

A support vector machine (SVM) is an important method in the detection and classification of the color difference on a polysilicon wafer. However, the accuracy of a SVM is affected by its feature vector and parameters. Owing to the complex color information and random texture features on the wafer surface, the feature design is extremely complicated. Meanwhile, a SVM optimized using a popular intelligent

In an advanced complementary metal-oxide-semiconductor (CMOS) technology node, small nano-scopic defects tend to have a significant impact on the yield and reliability of the final product. As the technology advances in fin field-effect-transistors (FinFETs), it has become increasingly challenging to control the extent of defects while also ensuring that the desired processing parameters are in place

In this paper, we propose a new statistical model parameter extraction method for compact power device models. While existing parameter extraction methods are only applicable for the parameters that follow normal distributions, the proposed method can simultaneously incorporate the model parameters that follow lognormal distributions. In addition, a set of dominant model parameters, which largely contributes

Wafer maps provide important information for engineers for detecting root causes of failure in a semiconductor manufacturing process. Thus, there has been active research into the automation of wafer map pattern classification. With recent advances in deep learning, a convolutional neural network (CNN) has yielded state-of-the-art performance in wafer map pattern classification. Because a large amount

In this study, the Gaussian mixture model (GMM) was modified and implemented to determine the real-time endpoint of SiO 2 plasma etching using optical emission spectrum analysis. Optical emission spectroscopy (OES) signals were collected from the SiO 2 plasma etching processes, and the modified GMM was applied to SiO 2 etching with relative areas of 8.0, 4.0, and 1.0 %. Consequently, the sensitivity

Vertical PNP bipolar transistor test structures were fabricated and measured, attempting to electrically obtain information on carrier lifetime in the voltage-supporting base region of Insulated Gate Bipolar Transistors (IGBTs). Owing to the structural similarity, the test structures and functional IGBTs can be integrated on the same wafers, making it possible to directly correlate lifetime data and

In order to reduce the interconnect resistance and capacitance (RC) time delay of a semiconductor integrated circuit, a more porous dielectric material is used in recent interconnection for lower dielectric constant. However, it is difficult to use highly porous low-k dielectric materials at the narrow pitch because it is easily damaged during the plasma etching processes. In this study, as one of