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Front cover IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-10-29
Presents the front cover for this issue of the publication.
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IEEE Transactions on Semiconductor Manufacturing publication information IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-10-29
Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
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Table of contents IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-10-29
Presents the table of contents for this issue of the publication.
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Guest Editorial Special Section—Papers From the 2019 MASM/WSC Conference IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-10-29 John W. Fowler; Lars Mönch; Tae-Eog Lee
The 2019 International Conference on Modeling and Analysis of Semiconductor Manufacturing (MASM 2019) was part of the 2019 Winter Simulation Conference (WSC) that was held December 8–11 in National Harbor, MD, USA. The MASM conferences provide a forum for the exchange of ideas and industrial innovations between researchers and practitioners from around the world involved in modeling and analysis of
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A Sequential Search Method of Dispatching Rules for Scheduling of LCD Manufacturing Systems IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-10-06 Je-Hun Lee; Young Kim; Yun Bae Kim; Byung-Hee Kim; Gu-Hwan Jung; Hyun-Jung Kim
A combination of dispatching rules to determine a sequence of jobs is often used for the scheduling of liquid crystal display or semiconductor manufacturing systems. Fab engineers determine weights ranging between 0 and 1 for dispatching rules, and the dispatching rules assign a value from 0 to 1 for each job. Then the weight given by the engineers and the value from each dispatching rule are multiplied
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Guest Editorial Special Section on the 2020 International Conference on Compound Semiconductor Manufacturing Technology (CS-MANTECH) IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-10-29 Patrick Fay
It is a special pleasure to be able to present IEEE T ransactions on S emiconductor M anufacturing readers with a selection of papers from the 2020 International Conference on Compound Semiconductor Manufacturing Technology (CS-MANTECH). This has been an extraordinarily challenging year by almost any measure, with personal and business disruptions on a dramatic scale worldwide. However, progress in
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Development of a World Class Silicon Carbide Substrate Manufacturing Capability IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-09-30 J. D. Blevins
Silicon carbide (SiC) semiconductor substrates provide the foundation for revolutionary improvements in the cost, size, weight and performance of a broad range of military and commercial radio frequency (RF) and power switching devices. Due to the lack of a viable, native gallium nitride (GaN) substrate, semi-insulating (SI) SiC substrates are the substrate of choice for high power AlGaN/GaN High Electron
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A Study on the Impact of Mid-Gap Defects on Vertical GaN Diodes IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-08-24 Mona A. Ebrish; Travis J. Anderson; Andrew D. Koehler; Geoffrey M. Foster; James C. Gallagher; Robert J. Kaplar; Brendan P. Gunning; Karl D. Hobart
GaN is a favorable martial for future efficient high voltage power switches. GaN has not dominated the power electronics market due to immature substrate, homoepitaxial growth, and immature processing technology. Understanding the impact of the substrate and homoepitaxial growth on the device performance is crucial for boosting the performance of GaN. In this work, we studied vertical GaN PiN diodes
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Impact of Water Content in NMP on Ohmic Contacts in GaN HEMT Technologies IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-10-02 Alexander Hugger; Aleksandra Dlugolecka; Hermann Stieglauer; Raphael Ehrbrecht; Michael Hosch
Wet chemical lift off in N-Methyl-2-pyrrolidone (NMP) is widely used in GaN HEMT Front End manufacturing. In case of a Ti-Al-Ni-Au based metal stack for ohmic contacts, the quality of the lift-off process is a strong function of the water content in the solvent NMP. In this article, it will be shown that the metal stack can be attacked during lift off in NMP when its water content is exceeding 5%.
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Qualitative and Quantitative Analysis of Multi-Pattern Wafer Bin Maps IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-09-08 Yuting Kong; Dong Ni
Wafer map analysis is one of the most critical steps for monitoring wafer quality and tracking failures in the semiconductor manufacturing process. Defective dies on wafer bin maps (WBMs) usually cluster into specific spatial patterns, which contain critical information for cause identification and yield improvement. Failures frequently arise due to the high complexity of production processes. Multiple
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Deformable Convolutional Networks for Efficient Mixed-Type Wafer Defect Pattern Recognition IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-09-02 Junliang Wang; Chuqiao Xu; Zhengliang Yang; Jie Zhang; Xiaoou Li
Defect pattern recognition (DPR) of wafer maps is critical for determining the root cause of production defects, which can provide insights for the yield improvement in wafer foundries. During wafer fabrication, several types of defects can be coupled together in a piece of wafer, it is called mixed-type defects DPR. To detect mixed-type defects is much more complicated because the combination of defects
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CNN-Based Layout Segment Classification for Analysis of Layout-Induced Failures IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-10-06 Yoshikazu Nagamura; Takashi Ide; Masayuki Arai; Satoshi Fukumoto
Physical failure analysis (PFA) specifies layout designs that affect large-scale integration (LSI) failure. Because of their capability and cost-effectiveness, convolutional neural networks (CNNs) have been applied to LSI layout analysis. However, the information on failure for root cause analyses is generally limited. Moreover, information over a large area, which includes many geometries, is required
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A Novel Method to Quantify Conditioner-to-Conditioner Variation and Predict Conditioner Lifetime and Process Failure Mode in Chemical Mechanical Planarization (CMP) Environment IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-10-08 Akshay Gowda; Satish Rai; Yun Zhuang; Wei Fan
In this study, we have developed a method to quantify inherent conditioner-to-conditioner variation using a mathematical model. Quantification of the lifetime of pad and conditioner in a chemical mechanical planarization (CMP) process using the model is also elucidated. Three conditioner types are selected based on their aggressiveness, and conditioning experiments are performed with five different
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Data-Driven Framework for Tool Health Monitoring and Maintenance Strategy for Smart Manufacturing IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-09-15 Chen-Fu Chien; Chia-Cheng Chen
Tool health monitoring and maintenance scheduling are crucial to empower smart manufacturing. Focusing on realistic needs, this study aims to develop a data-driven framework that integrates partial least squares and exponentially weighted moving-average for feature selection and model construction to monitor and predict tool health via analyzing status data collected from the sensors and thus derive
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Semi-Supervised Multi-Label Learning for Classification of Wafer Bin Maps With Mixed-Type Defect Patterns IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-09-29 Hyuck Lee; Heeyoung Kim
After wafer fabrication, individual chips on the wafer are checked for defects by using multiple electrical tests. The test results can be represented by binary values for all individual chips, which form a spatial map called a wafer bin map (WBM). Different defect patterns in WBMs are related to different causes of process faults. Thus, it is important to classify WBMs according to their defect patterns
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Call for Papers for a Special Issue of IEEE Transactions on Electron Devices on New simulation methodologies for next-generation TCAD tools IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-10-29
Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
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Low Temperature Processing of Electronic Materials for Cuttung Edge Devices IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-10-29
Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
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IEEE Transactions on Semiconductor Manufacturing information for authors IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-10-29
These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
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Blank page IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-10-29
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Process Optimization and Microwave Model of GaAs Photodiodes for 50 Gb/s Optical Links IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-08-19 Dufei Wu; Yu-Ting Peng; Xin Yu; Milton Feng
GaAs photodiode is a critical O/E receiver component for high-speed optical link in data centers and HPC. In this work, GaAs P-i-N photodiodes with four different aperture diameters are developed for 50 Gb/s data detection. Device layer structure and the fabrication process are optimized to achieve low dark current, high responsivity and high bandwidth. An O/E microwave model based on the device physics
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Integration of 650 V GaN Power ICs on 200 mm Engineered Substrates IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-08-18 Xiangdong Li; Karen Geens; Dirk Wellekens; Ming Zhao; Alessandro Magnani; Nooshin Amirifar; Benoit Bakeroot; Shuzhen You; Dirk Fahle; Herwig Hahn; Michael Heuken; Vlad Odnoblyudov; Ozgur Aktas; Cem Basceri; Denis Marcon; Guido Groeseneken; Stefaan Decoutere
GaN power ICs on engineered substrates of Qromis substrate technology (QST) are promising for future power applications, thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, and high mechanical yield in combination with thick GaN buffer layers. In this article, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations
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Front cover IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-08-04
Presents the front cover for this issue of the publication.
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IEEE Transactions on Semiconductor Manufacturing publication information IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-08-04
Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
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Table of contents IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-08-04
Presents the table of contents for this issue of the publication.
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Guest Editorial Special Section on the 2019 SEMI Advanced Semiconductor Manufacturing Conference IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-08-05 Jeanne Paulette Bickford; Oliver D. Patterson; Stefan Radloff; Paul Werbaneth
Dear readers—We hope this editorial finds you and your family safe as we and the world battle—or, hopefully at the time of this publication, recover from—perhaps the greatest world-wide health crisis in the last century, COVID-19. Fortunately, the contributions of our semiconductor manufacturing industry over the last 40 years have put us in a much more comfortable position than those who faced past
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Electron Beam Inspection in Physical Mode: Overpolish Monitoring of RMG CMP IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-06-10 Richard F Hafer; Hong Lin; Andrew Stamper; Brian Yueh-Ling Hsieh; Jerry Hsieh
For a recent replacement metal gate (RMG) FINFET technology using an SOI substrate, an inhomogeneous polish post Tungsten fill of the RMG was discovered. For particular wide-gate structures, the Tungsten polish within the reticle field and across the wafer varied widely despite being in control using the established kerf metrology structure. This was discovered after the technology had been ramped
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Enhancement of Diffraction-Based Overlay Model for Overlay Target With Asymmetric Sidewall IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-06-22 Chun-Han Su; Zi-Han Lin; Yu-Shin Lin; Hung-Fei Kuo
Overlay metrology is crucial to process control in manufacturing semiconductor devices. Diffraction-based overlay (DBO) is an effective overlay measurement approach because it exhibits multiple advantages. This study analyzed measurement errors caused by sidewalls in the bottom gratings of DBO targets. Accordingly, improvement was proposed using a neural network. First, rigorous coupled wave analysis
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Combination of Convolutional and Generative Adversarial Networks for Defect Image Demoiréing of Thin-Film Transistor Liquid-Crystal Display Image IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-06-26 Hsueh-Ping Lu; Chao-Ton Su; Shi-Yong Yang; Yen-Po Lin
In thin-film transistor liquid crystal display (TFT-LCD) manufacturing, the automatic recognition and classification of defects can help manufacturers monitor abnormalities, identify potential process problems, and swiftly respond to these process problems. Thus, yield loss can be reduced. However, capturing the content displayed on screen using cameras is challenging because it is often contaminated
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Performance-Based Active Wafer Clamp Design for Wafer Heating Effects in EUV Lithography IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-06-04 David van den Hurk; Siep Weiland; Koos van Berkel
To improve overlay and focus errors in lithographic applications, an active wafer clamp (AWC) concept is proposed. Using this concept, mechanical actuators deform the wafer to compensate thermally induced deformations. In [1] a localized feedforward (FF) control algorithm for the AWC concept was introduced. In this paper we aim to improve this algorithm and discuss practical implications for the design
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Run-to-Run Control of Chemical Mechanical Polishing Process Based on Deep Reinforcement Learning IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-06-16 Jianbo Yu; Peng Guo
The chemical mechanical polishing (CMP) process usually suffers from drift and shift in the Run-to-Run material removal process due to the wear and replacement of the polishing pad, lacking of in-suit measurements of the product quality of interest and other environment variations. This paper proposed a deep reinforcement learning (DRL)-based run-to-run (R2R) controller for the CMP process. Firstly
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Variational Deep Clustering of Wafer Map Patterns IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-06-23 Jonghyun Hwang; Heeyoung Kim
In semiconductor manufacturing, several measurement data called wafer maps are obtained in the metrology steps, and the variations in the process are detected by analyzing the wafer map data. Hidden processes or equipment affecting the process quality variations can be found by comparing the process tracking history and clustered groups of similar wafer maps; thus, clustering analysis is very important
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Noncyclic Scheduling of Multi-Cluster Tools With Residency Constraints Based on Pareto Optimization IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-06-08 Yuanyuan Yan; Huangang Wang; Qinghua Tao; Wenhui Fan; Tingyu Lin; Yingying Xiao
Multi-cluster tools are widely used in semiconductor manufacturing. When the lot size of wafers tends to be quite small, a cyclic scheduling strategy is not suitable. However, the noncyclic scheduling of multi-cluster tools is much more challenging due to multi-robot coordination and the increasing number of chambers. This paper focuses on the noncyclic scheduling problem of multi-cluster tools with
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Critical Dimension Bimodality Both Within Wafer and Within Die IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-06-24 Talapady Srivatsa Bhat; Gagan Aggarwal; Ganesh Yerubandi; David Bolton
With reduction in the die sizes it is very critical to control the Critical Dimension (CD) within a very precise window. In this work we present a root cause analysis and solution to a bimodal CD distribution seen from the center of the wafer. The CD bimodality displays a sharp cliff at the center of the wafer, wherein one side of the wafer has the higher CD and the other side has lower CD with respect
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Call for Papers 5th IEEE Electron Devices Technology and Manufacturing (EDTM) Conference, 2021 IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-08-04
Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.
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IEEE Transactions on Semiconductor Manufacturing information for authors IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-08-04
These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
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Blank page IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-08-04
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A Light-Weight Neural Network for Wafer Map Classification Based on Data Augmentation IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-07-30 Tsung-Han Tsai; Yu-Chen Lee
In the semiconductor industry, the testing section has always played an important role. The testing section often requires engineers to judge the defect, which wastes a lot of time and cost. The accurate classification can provide useful information for engineers through neural networks. In this paper, we present a method for wafer map data augmentation and defect classification. Data augmentation
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Support Weighted Ensemble Model for Open Set Recognition of Wafer Map Defects IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-07-27 Jaeyeon Jang; Minkyung Seo; Chang Ouk Kim
Wafer defect maps have different generation mechanisms according to the defect pattern, and automatic classification of wafer maps is therefore critical to reveal the root cause of the defects. In this paper, we examine the open set recognition problem, in which not only must wafer maps be classified using major defect patterns that are already known but also unknown defect patterns must also be detected
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Memory-Augmented Convolutional Neural Networks With Triplet Loss for Imbalanced Wafer Defect Pattern Classification IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-07-21 Yunseung Hyun; Heeyoung Kim
A wafer bin map (WBM) represents the wafer testing results for individual dies on a wafer using a binary value that represents pass or fail. WBMs often have specific defect patterns, which occur because of assignable causes. Therefore, the identification of defect patterns in WBMs aids in understanding the root causes of process failure. Previous studies on the classification of WBM defect patterns
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Advanced Quality Control (AQC) of Silicon Wafer Specifications for Yield Enhancement for Smart Manufacturing IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-07-17 Chen-Fu Chien; Yin-Hung Chen; Mei-Fang Lo
Silicon wafers are critical raw materials for semiconductor fabrication. Wafer characteristics and specifications will affect the yield of integrated circuits fabricated on the wafer. As critical dimensions for semiconductor manufacturing are shrinking, defining wafer characteristics and specifications for the corresponding semiconductor devices is crucial for yield enhancement and smart manufacturing
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Development of Diaphragm and Microtunnel Structures for MEMS Piezoelectric Sensors IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-07-16 Ashish Kumar; Mahanth Prasad; Vijay Janyani; R. P. Yadav
This paper reports a novel method for fabrication of diaphragm along with microtunnels for various applications. Micromasking, grass formation, uniformity over the process wafer, notching, growth of thick silicon oxide masking layer, protection of microtunnel during diaphragm fabrication etc. are the major challenges in deep reactive ion etching (DRIE) of the existing silicon bulk micromachining process
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Elimination of Metal Fencing by Optimizing Evaporator Dome Alignment IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-07-10 Kezia Cheng
Successful metal liftoff requires a retrograde photoresist profile, or one created using a bi-layer process. Coupled with an evaporator setup for liftoff deposition, these ensure a discontinuity in metal coverage so that the unwanted field metal can be lifted off cleanly, without tearing or defects. An evaporator with an optimized liftoff configuration necessitates precise source-to-substrate alignment
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SMT2020—A Semiconductor Manufacturing Testbed IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-06-12 Denny Kopp; Michael Hassoun; Adar Kalir; Lars Mönch
We present a new set of simulation models, organized in a testbed. The aim of the testbed consists in providing researchers with a platform able to credibly represent the complexity of modern semiconductor manufacturing. The testbed is open to public use, and include so far four models. A high-volume/low-mix model and a low-volume/high-mix model constitutes the foundation of the testbed. Two additional
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Matheuristics for Qualification Management Decisions in Wafer Fabs IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-06-01 Denny Kopp; Lars Mönch
In this paper, a qualification management problem arising in semiconductor wafer fabrication facilities (wafer fabs) is studied. The stepper machines, a common bottleneck in many wafer fabs, must be qualified to process lots of different families. A qualification time window is associated with each stepper and family. It can be reinitialized as needed and can be extended by on-time processing of lots
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Locally Adaptive Statistical Background Modeling With Deep Learning-Based False Positive Rejection for Defect Detection in Semiconductor Units IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-05-28 Bashar M. Haddad; Samuel F. Dodge; Lina J. Karam; Nital S. Patel; Martin W. Braun
In this paper, we present a system for the detection and classification of defects in semiconductor units. The proposed system consists of three stages: proposal generation stage, defect detection stage and refinement stage. In the proposal generation stage, changes on the target unit are detected using a novel change detection approach. In the second stage, a deep neural network is used to classify
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Deep Learning-Based Domain Adaptation Method for Fault Diagnosis in Semiconductor Manufacturing IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-05-19 Moslem Azamfar; Xiang Li; Jay Lee
Quality inspection in semiconductor manufacturing is of great importance in the modern industries. In the recent years, intelligent data-driven condition monitoring methods have been successfully developed and applied in the industrial applications. However, despite the promising condition monitoring performance, the existing methods generally assume the training and testing data are from the same
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A Deep Convolutional Neural Network for Wafer Defect Identification on an Imbalanced Dataset in Semiconductor Manufacturing Processes IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-05-14 Muhammad Saqlain; Qasim Abbas; Jong Yun Lee
Wafer maps contain information about various defect patterns on the wafer surface and automatic classification of these defects plays a vital role to find their root causes. Semiconductor engineers apply various methods for wafer defect classification such as manual visual inspection or machine learning-based algorithms by manually extracting useful features. However, these methods are unreliable,
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Advanced Low Pin Count Test Architecture for Efficient Multi-Site Testing IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-05-12 Sungyoul Seo; Young-Woo Lee; Hyeonchan Lim; Sungho Kang
With the rapidly increasing test time of semiconductor testing, the trend is currently toward improving test parallelism by exploiting multi-site testing. However, excessive test I/O channels and test power consumption lead to the degradation of multi-site testing efficiency owing to the limited number of tester I/Os and power capacity. In this paper, we present an advanced low pin count test architecture
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Applying Taguchi’s Method, Artificial Neural Network and Genetic Algorithm to Reduce the CoSi₂ Resistance Deviation of DRAM Products IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-05-12 Chia-Ming Lin; Yungho Leu
Demand for products of dynamic random-access memory (DRAM) has dramatically increased since 2019. To satisfy the soaring demand, many companies have increased their supply for DRAM products. The DRAM CoSi 2 resistance significantly affects the quality of a DRAM product. The case company under this study suffered from deviations of the CoSi 2 resistances of its DRAM products from a target value of 11
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TestDNA: Novel Wafer Defect Signature for Diagnosis and Pattern Recognition IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-05-07 Katherine Shu-Min Li; Nova Cheng-Yen Tsai; Ken Chau-Cheung Cheng; Xu-Hao Jiang; Peter Yi-Yu Liao; Sying-Jyan Wang; Andrew Yi-Ann Huang; Leon Chou; Chen-Shiun Lee
The spatial failure patterns in wafer defect maps can be related to problems in the manufacturing and test process. Therefore, failure pattern recognition can be used for root cause analysis, which is very important for defect diagnosis resolution improvement and yield learning. However, previous studies show that wafers with recognizable failure patterns only account for a small part of all defective
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Which Spare Parts Service Measure to Choose for a Front-End Wafer Fab? IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-05-06 Douniel Lamghari-Idrissi; Rob Basten; Nico Dellaert; Geert-Jan van Houtum
We are interested in the influence of spare part service measures on the performance of the front-end wafer fabrication process. This process is characterized by re-entrant flows due to the multiple layers present on chips. This exacerbates the effects of flow variability. We focus on the bottleneck resource. We consider three different service measures. The traditional aggregate fill rate and downtime
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Front cover IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-05-06
Presents the front cover for this issue of the publication.
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IEEE Transactions on Semiconductor Manufacturing publication information IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-05-06
Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
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Table of contents IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-05-06
Presents the table of contents for this issue of the publication.
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Editorial IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-05-06 Reha Uzsoy
The world is a rather different place now than it was last November, when I wrote the last of these editorials. As we deal with the worldwide economic slowdown, social distancing and the other consequences of the Covid-19 pandemic, I am grateful to all members of the TSM community who continue to work under trying conditions to keep the journal’s business going.
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Guest Editorial Special Section on the International Conference on Microelectronic Test Structures (ICMTS) IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-05-06 Tsuyoshi Sekitani
As a guest Editor for the special section on the 2017, 2018, and 2019 International Conference on Microelectronic Test Structures (ICMTS), I am gratified to be able to present our IEEE Transactions on Semiconductor Manufacturing readers with a selection of papers based on work presented at the 2017, 2018, and 2019 conferences.
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2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-05-06
Presents information on the 2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium.
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IEEE Transactions on Semiconductor Manufacturing information for authors IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-05-06
These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
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Blank page IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-05-06
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Characterization of eFuse Programming for Varying RF BiCMOS Technology Silicides IEEE Trans. Semicond. Manuf. (IF 1.977) Pub Date : 2020-04-29 E. Gebreselasie; Y. Ngu; A. Loiseau; I. McCallum-Cook
Ti, Co, Pt, and Ni salicide processes optimized for a range of CMOS technology nodes down to 90nm were fabricated using 0.35 $\mu {\mathrm{ m}}$ SiGe BiCMOS. On-wafer circuitry was used to program discrete eFuse elements to compare their pre and post programmed resistances as well as their behavior during programming between each salicide process employed, with TEM analysis to confirm successful electromigration