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The 2019 International Conference on Modeling and Analysis of Semiconductor Manufacturing (MASM 2019) was part of the 2019 Winter Simulation Conference (WSC) that was held December 8–11 in National Harbor, MD, USA. The MASM conferences provide a forum for the exchange of ideas and industrial innovations between researchers and practitioners from around the world involved in modeling and analysis of

A combination of dispatching rules to determine a sequence of jobs is often used for the scheduling of liquid crystal display or semiconductor manufacturing systems. Fab engineers determine weights ranging between 0 and 1 for dispatching rules, and the dispatching rules assign a value from 0 to 1 for each job. Then the weight given by the engineers and the value from each dispatching rule are multiplied

It is a special pleasure to be able to present IEEE T ransactions on S emiconductor M anufacturing readers with a selection of papers from the 2020 International Conference on Compound Semiconductor Manufacturing Technology (CS-MANTECH). This has been an extraordinarily challenging year by almost any measure, with personal and business disruptions on a dramatic scale worldwide. However, progress in

Silicon carbide (SiC) semiconductor substrates provide the foundation for revolutionary improvements in the cost, size, weight and performance of a broad range of military and commercial radio frequency (RF) and power switching devices. Due to the lack of a viable, native gallium nitride (GaN) substrate, semi-insulating (SI) SiC substrates are the substrate of choice for high power AlGaN/GaN High Electron

GaN is a favorable martial for future efficient high voltage power switches. GaN has not dominated the power electronics market due to immature substrate, homoepitaxial growth, and immature processing technology. Understanding the impact of the substrate and homoepitaxial growth on the device performance is crucial for boosting the performance of GaN. In this work, we studied vertical GaN PiN diodes

Wet chemical lift off in N-Methyl-2-pyrrolidone (NMP) is widely used in GaN HEMT Front End manufacturing. In case of a Ti-Al-Ni-Au based metal stack for ohmic contacts, the quality of the lift-off process is a strong function of the water content in the solvent NMP. In this article, it will be shown that the metal stack can be attacked during lift off in NMP when its water content is exceeding 5%.

Wafer map analysis is one of the most critical steps for monitoring wafer quality and tracking failures in the semiconductor manufacturing process. Defective dies on wafer bin maps (WBMs) usually cluster into specific spatial patterns, which contain critical information for cause identification and yield improvement. Failures frequently arise due to the high complexity of production processes. Multiple

Defect pattern recognition (DPR) of wafer maps is critical for determining the root cause of production defects, which can provide insights for the yield improvement in wafer foundries. During wafer fabrication, several types of defects can be coupled together in a piece of wafer, it is called mixed-type defects DPR. To detect mixed-type defects is much more complicated because the combination of defects

Physical failure analysis (PFA) specifies layout designs that affect large-scale integration (LSI) failure. Because of their capability and cost-effectiveness, convolutional neural networks (CNNs) have been applied to LSI layout analysis. However, the information on failure for root cause analyses is generally limited. Moreover, information over a large area, which includes many geometries, is required

In this study, we have developed a method to quantify inherent conditioner-to-conditioner variation using a mathematical model. Quantification of the lifetime of pad and conditioner in a chemical mechanical planarization (CMP) process using the model is also elucidated. Three conditioner types are selected based on their aggressiveness, and conditioning experiments are performed with five different

Tool health monitoring and maintenance scheduling are crucial to empower smart manufacturing. Focusing on realistic needs, this study aims to develop a data-driven framework that integrates partial least squares and exponentially weighted moving-average for feature selection and model construction to monitor and predict tool health via analyzing status data collected from the sensors and thus derive

After wafer fabrication, individual chips on the wafer are checked for defects by using multiple electrical tests. The test results can be represented by binary values for all individual chips, which form a spatial map called a wafer bin map (WBM). Different defect patterns in WBMs are related to different causes of process faults. Thus, it is important to classify WBMs according to their defect patterns

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GaAs photodiode is a critical O/E receiver component for high-speed optical link in data centers and HPC. In this work, GaAs P-i-N photodiodes with four different aperture diameters are developed for 50 Gb/s data detection. Device layer structure and the fabrication process are optimized to achieve low dark current, high responsivity and high bandwidth. An O/E microwave model based on the device physics

GaN power ICs on engineered substrates of Qromis substrate technology (QST) are promising for future power applications, thanks to the reduced parasitics, thermally matched substrate of poly-AlN, high thermal conductivity, and high mechanical yield in combination with thick GaN buffer layers. In this article, we will elaborate in detail on epitaxy, integration, and trench isolation. Electrical characterizations

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Dear readers—We hope this editorial finds you and your family safe as we and the world battle—or, hopefully at the time of this publication, recover from—perhaps the greatest world-wide health crisis in the last century, COVID-19. Fortunately, the contributions of our semiconductor manufacturing industry over the last 40 years have put us in a much more comfortable position than those who faced past

For a recent replacement metal gate (RMG) FINFET technology using an SOI substrate, an inhomogeneous polish post Tungsten fill of the RMG was discovered. For particular wide-gate structures, the Tungsten polish within the reticle field and across the wafer varied widely despite being in control using the established kerf metrology structure. This was discovered after the technology had been ramped

Overlay metrology is crucial to process control in manufacturing semiconductor devices. Diffraction-based overlay (DBO) is an effective overlay measurement approach because it exhibits multiple advantages. This study analyzed measurement errors caused by sidewalls in the bottom gratings of DBO targets. Accordingly, improvement was proposed using a neural network. First, rigorous coupled wave analysis

In thin-film transistor liquid crystal display (TFT-LCD) manufacturing, the automatic recognition and classification of defects can help manufacturers monitor abnormalities, identify potential process problems, and swiftly respond to these process problems. Thus, yield loss can be reduced. However, capturing the content displayed on screen using cameras is challenging because it is often contaminated

To improve overlay and focus errors in lithographic applications, an active wafer clamp (AWC) concept is proposed. Using this concept, mechanical actuators deform the wafer to compensate thermally induced deformations. In [1] a localized feedforward (FF) control algorithm for the AWC concept was introduced. In this paper we aim to improve this algorithm and discuss practical implications for the design

The chemical mechanical polishing (CMP) process usually suffers from drift and shift in the Run-to-Run material removal process due to the wear and replacement of the polishing pad, lacking of in-suit measurements of the product quality of interest and other environment variations. This paper proposed a deep reinforcement learning (DRL)-based run-to-run (R2R) controller for the CMP process. Firstly

In semiconductor manufacturing, several measurement data called wafer maps are obtained in the metrology steps, and the variations in the process are detected by analyzing the wafer map data. Hidden processes or equipment affecting the process quality variations can be found by comparing the process tracking history and clustered groups of similar wafer maps; thus, clustering analysis is very important

Multi-cluster tools are widely used in semiconductor manufacturing. When the lot size of wafers tends to be quite small, a cyclic scheduling strategy is not suitable. However, the noncyclic scheduling of multi-cluster tools is much more challenging due to multi-robot coordination and the increasing number of chambers. This paper focuses on the noncyclic scheduling problem of multi-cluster tools with

With reduction in the die sizes it is very critical to control the Critical Dimension (CD) within a very precise window. In this work we present a root cause analysis and solution to a bimodal CD distribution seen from the center of the wafer. The CD bimodality displays a sharp cliff at the center of the wafer, wherein one side of the wafer has the higher CD and the other side has lower CD with respect

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In the semiconductor industry, the testing section has always played an important role. The testing section often requires engineers to judge the defect, which wastes a lot of time and cost. The accurate classification can provide useful information for engineers through neural networks. In this paper, we present a method for wafer map data augmentation and defect classification. Data augmentation

Wafer defect maps have different generation mechanisms according to the defect pattern, and automatic classification of wafer maps is therefore critical to reveal the root cause of the defects. In this paper, we examine the open set recognition problem, in which not only must wafer maps be classified using major defect patterns that are already known but also unknown defect patterns must also be detected

A wafer bin map (WBM) represents the wafer testing results for individual dies on a wafer using a binary value that represents pass or fail. WBMs often have specific defect patterns, which occur because of assignable causes. Therefore, the identification of defect patterns in WBMs aids in understanding the root causes of process failure. Previous studies on the classification of WBM defect patterns

Silicon wafers are critical raw materials for semiconductor fabrication. Wafer characteristics and specifications will affect the yield of integrated circuits fabricated on the wafer. As critical dimensions for semiconductor manufacturing are shrinking, defining wafer characteristics and specifications for the corresponding semiconductor devices is crucial for yield enhancement and smart manufacturing

This paper reports a novel method for fabrication of diaphragm along with microtunnels for various applications. Micromasking, grass formation, uniformity over the process wafer, notching, growth of thick silicon oxide masking layer, protection of microtunnel during diaphragm fabrication etc. are the major challenges in deep reactive ion etching (DRIE) of the existing silicon bulk micromachining process

Successful metal liftoff requires a retrograde photoresist profile, or one created using a bi-layer process. Coupled with an evaporator setup for liftoff deposition, these ensure a discontinuity in metal coverage so that the unwanted field metal can be lifted off cleanly, without tearing or defects. An evaporator with an optimized liftoff configuration necessitates precise source-to-substrate alignment

We present a new set of simulation models, organized in a testbed. The aim of the testbed consists in providing researchers with a platform able to credibly represent the complexity of modern semiconductor manufacturing. The testbed is open to public use, and include so far four models. A high-volume/low-mix model and a low-volume/high-mix model constitutes the foundation of the testbed. Two additional

In this paper, a qualification management problem arising in semiconductor wafer fabrication facilities (wafer fabs) is studied. The stepper machines, a common bottleneck in many wafer fabs, must be qualified to process lots of different families. A qualification time window is associated with each stepper and family. It can be reinitialized as needed and can be extended by on-time processing of lots

In this paper, we present a system for the detection and classification of defects in semiconductor units. The proposed system consists of three stages: proposal generation stage, defect detection stage and refinement stage. In the proposal generation stage, changes on the target unit are detected using a novel change detection approach. In the second stage, a deep neural network is used to classify

Quality inspection in semiconductor manufacturing is of great importance in the modern industries. In the recent years, intelligent data-driven condition monitoring methods have been successfully developed and applied in the industrial applications. However, despite the promising condition monitoring performance, the existing methods generally assume the training and testing data are from the same

Wafer maps contain information about various defect patterns on the wafer surface and automatic classification of these defects plays a vital role to find their root causes. Semiconductor engineers apply various methods for wafer defect classification such as manual visual inspection or machine learning-based algorithms by manually extracting useful features. However, these methods are unreliable,

With the rapidly increasing test time of semiconductor testing, the trend is currently toward improving test parallelism by exploiting multi-site testing. However, excessive test I/O channels and test power consumption lead to the degradation of multi-site testing efficiency owing to the limited number of tester I/Os and power capacity. In this paper, we present an advanced low pin count test architecture

Demand for products of dynamic random-access memory (DRAM) has dramatically increased since 2019. To satisfy the soaring demand, many companies have increased their supply for DRAM products. The DRAM CoSi 2 resistance significantly affects the quality of a DRAM product. The case company under this study suffered from deviations of the CoSi 2 resistances of its DRAM products from a target value of 11

The spatial failure patterns in wafer defect maps can be related to problems in the manufacturing and test process. Therefore, failure pattern recognition can be used for root cause analysis, which is very important for defect diagnosis resolution improvement and yield learning. However, previous studies show that wafers with recognizable failure patterns only account for a small part of all defective

We are interested in the influence of spare part service measures on the performance of the front-end wafer fabrication process. This process is characterized by re-entrant flows due to the multiple layers present on chips. This exacerbates the effects of flow variability. We focus on the bottleneck resource. We consider three different service measures. The traditional aggregate fill rate and downtime

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The world is a rather different place now than it was last November, when I wrote the last of these editorials. As we deal with the worldwide economic slowdown, social distancing and the other consequences of the Covid-19 pandemic, I am grateful to all members of the TSM community who continue to work under trying conditions to keep the journal’s business going.

As a guest Editor for the special section on the 2017, 2018, and 2019 International Conference on Microelectronic Test Structures (ICMTS), I am gratified to be able to present our IEEE Transactions on Semiconductor Manufacturing readers with a selection of papers based on work presented at the 2017, 2018, and 2019 conferences.

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Ti, Co, Pt, and Ni salicide processes optimized for a range of CMOS technology nodes down to 90nm were fabricated using 0.35 $\mu {\mathrm{ m}}$ SiGe BiCMOS. On-wafer circuitry was used to program discrete eFuse elements to compare their pre and post programmed resistances as well as their behavior during programming between each salicide process employed, with TEM analysis to confirm successful electromigration