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This special section of IEEE Transactions on Semiconductor Manufacturing presents extended versions of papers originally presented as part of the IEEE 33 rd International Conference on Microelectronic Test Structures (ICMTS) which was hosted at the University of Edinburgh, Scotland. Originally planned to take place at the University’s South Hall Complex in April 2020, the impact of the global pandemic

Since its beginning in 1992 in Japan, International Symposium on Semiconductor Manufacturing (ISSM) has provided unique opportunities to share the best practices of semiconductor manufacturing technologies for professionals. At the symposiums, semiconductor manufacturing professionals discussed the technologies developed to meet the worldwide requirements for advanced manufacturing. It is becoming

We developed a method of measuring microscopic $\zeta $ potential (ZP) from force vs distance (FD) curves observed by atomic force microscope (AFM). ZP in microscopic regions on wafer surfaces may be one of the most important design guides of chemical mechanical polishing slurries applicable to ultrafine patterned wafers, while ZP is generally observed as an average information for a wide area. Our

Detecting defects in the inspection stage of semiconductor manufacturing process is a crucial task to improve yield and productivity as well as wafer quality. Recent Advances in semiconductor process technology have greatly increased the transistor density. As a result, an increasingly high number of defects inevitably emerge and we need a more accurate and efficient detection method to manage them

Photolithography is the bottleneck for quality improvement in semiconductor manufacturing processes. The decreasing critical dimensions of the semiconductor product requires more effective run-to-run control technology. Currently, Exponential Weighted Moving Average (EWMA) control scheme is widely used in the overlay control of lithography processes. In this article, we address three shortcomings of

The growth process of Czochralski (Cz) silicon single crystal is a dynamic time-varying system with nonlinearity, strong coupling, large hysteresis, and uncertain model. Traditional model-based control methods are difficult to achieve satisfactory crystal growth control effects, and it is difficult to ensure that the crystal quality meets the actual process requirements. Therefore, from the perspective

Moisture removal techniques such as purge have been developed for the front opening unified pod (FOUP) in the semiconductor industry. The FOUP purge can significantly increase the quality of integrated circuit (IC) products. An experimental model of a simulated clean room, was designed at Taipei Tech. A mini environment (ME) and a FOUP were installed inside the model. Smoke flow visualization technique

Deep Learning approaches have revolutionized in the past decade the field of Computer Vision and, as a consequence, they are having a major impact in Industry 4.0 applications like automatic defect classification. Nevertheless, additional data, beside the image/video itself, is typically never exploited in a defect classification module: this aspect, given the abundance of data in data-intensive manufacturing

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

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This work proposes a methodology to find lithography yield detractors using Design Rule Checks (DRC) that are derived from a supervised Machine Learning (ML) model. The probability of being an outlier in layout parameter domain has a strong correlation with the probability of process failure. Moreover, the failing patterns exhibit relatively complex and non-linear behavior and often form complex clusters

Manufacturing of microsystems based on complex three-dimensional microstructures requires critical steps such as mass calibrations and integration process. However, such steps involve several manipulation steps which are not well controlled thus the fragile 3D microstructures could be damaged or destroyed. In this work, we have demonstrated an AFM based direct mass measurement and manufacturing of

Investigating heterointerfaces with test structures is crucial for fabricating electronic and photonic devices. Recently, we proposed and developed a PbS colloidal quantum dot/ZnO/Si hybrid infrared detector for infrared-sensitive optoelectronic devices on silicon-based large-scale integrated circuits. The conventional circular transfer length method (CTLM) is commonly used for evaluating Ohmic contact

We propose and demonstrate a drop-in test structure to visualize and measure the residual stress in the conformally deposited film. For reliable device process of microsystems (such as 3-D MEMS), the residual stress must be controlled through quantitative evaluation at each deposition step. A small drop-in test structure placed near the main sample is suitable for monitoring film characteristics. We

Field-Plate (FP) MOSFET structure has been studied to get higher performance characteristics. To get low drift layer resistance, reduction of the trench width is one typical method with FP-MOSFET because it enables us to design the fine cell pitch of the FP-MOSFET. The main method for reducing the trench width is to design large trench angle. However large trench angle for better characteristics causes

For advanced equipment control, two schemata of real-time fault detection were performed using machine learning algorithms in silicon etching in SF 6 /O 2 /Ar plasma. Fault detection and classification is investigated with the plasma state information with optical emission spectroscopy (OES) data to find the root cause of the anomaly in the process parameters. Fault detection and control is also demonstrated

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Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

One of the most pleasant aspects of the Editor in Chief’s job is to recognize outstanding contributions from the TSM community. The TSM Best Paper Award is presented annually to a paper published in the previous calendar year that is recognized by the Editorial Board to have made an outstanding contribution to the field. Papers are nominated at the time of acceptance by the handling Associate Editor;

In this study, the imaging of metal ions and nanoparticles deposited on a structured silicon surface was investigated using a laser ablation-inductively coupled plasma-mass spectrometry (LA-ICP-MS). For application, 8 $\times $ 8 Petri-dish pillars, each with a diameter of 250 $\mu \text{m}$ and height of 300 $\mu \text{m}$ , were constructed on a silicon wafer. The etched pillar surface took a droplet

This work presents possible variations in TRL calibrated on-wafer S-parameters measurements with change in the on-wafer reflect design (pad open to pad short or vice-versa) in the TRL calibration method. The variations in each error-term values due to the change in the on-wafer reflect in the TRL calibration are examined which shows the source match and reflect tracking as possible error-terms bringing

Wafer test is carried out after integrated circuits (IC) fabrication to screen out bad dies. In addition, the results can be used to identify problems in the fabrication process and improve manufacturing yield. However, the wafer test itself may induce defects to otherwise good dies. Test-induced defects not only hurt overall manufacturing yield but also create problems for yield learning, so the source

Recurrent neural network (RNN) is employed as a machine learning model for fast optical proximity correction (OPC). RNN consists of a number of neural network instances which are serially connected, with each instance in charge of one segment. RNN thus allows some localized segments to be corrected together in one execution, which offers higher accuracy. A basic RNN is extended by introducing gated

Statistical quality control in semiconductor manufacturing hinges on effective diagnostics of wafer bin maps, wherein a key challenge is to detect how defective chips tend to spatially cluster on a wafer—a problem known as spatial pattern recognition . Recently, there has been a growing interest in mixed-type spatial pattern recognition—when multiple defect patterns, of different shapes, co-exist on

In LED semiconductor manufacturing, it is important to evaluate the wafer reflectance in order to validate the quality of wafers. In this work, a learning model based on ${K}$ -means clustering and neural networks is proposed to analyze the relationship between etching parameters and wafer reflectance under a complex etching environment. The implemented clustering algorithm is used to cluster historical

Aluminum nitride (AlN) is a semiconductor material with the wide band gap. The requirement of the substrate for the semiconductor device is no surface damage. In this paper, based on the principle of the hydration reaction of aluminum nitride, the single crystal aluminum nitride was polished under dry conditions and wet conditions using a sol-gel (SG) tool. The abrasive used in the SG polishing tool

The corrosion of ceramic chamber parts causes particles in plasma etching process, so that the production yield and the overall equipment effectiveness (OEE) at LSI mass production line are decreased. We have developed magnesium oxide (MgO)-based ceramics whose corrosion resistance in reactive plasma is higher than conventional ceramic materials. In this study, we have prepared a shower-head-type electrode

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

Prospective authors are requested to submit new, unpublished manuscripts for inclusion in the upcoming event described in this call for papers.

These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.

Suppression of harmful effect due to by-product on homo-epitaxial growth of 4H-SiC films using a high speed wafer rotation vertical CVD method was demonstrated. Influence of by-product, such as 3C-SiC deposit on a hot-wall and Si deposit on gas nozzles, formed during the epitaxial growth was investigated in two comparative studies. The analysis of triangular defects with 3C-SiC down-falls on the films

Defect classifications are the very important steps as the in-line defect inspection of the semiconductor manufacturing procedure. The conventional defect classifications are usually through visual judgement by engineer or technical assistant. However, it’s time-consuming and laborious. In our recent study, the artificial intelligence automatic defect classification (AI-ADC) performed promisingly good

A novel foundry yield model for integrated circuit products has been developed based on critical area scaling. The newly proposed model does not need the information of the defect density by failure mode. This has considerably simplified the model inputs, and avoided the complicated and costly process to obtain the accurate defect density by failure mode. First, the critical area concept and the existing

This paper describes a chamber and recipe-independent fault detection and classification (FDC) indicator using the example of aluminum sputtering tools. We developed this indicator to detect abnormal discharge in an aluminum sputtering chamber when using a legacy FDC system. Abnormal discharge has several modes in the sputtering chamber, with abnormal discharge to a wafer commonly causing pattern defects

Electrical properties and microstructure of phosphorus (P) implanted p-type Si substrates were evaluated by four-point probe (4PP), Differential Hall Effect Metrology (DHEM), secondary ion mass spectrometry (SIMS) and transmission electron microscopy (TEM) techniques, after RTA 750–950°C and CO 2 laser 120–140W annealing. When RTA temperature was increased, defect concentration at a-Si/c-Si interface

Model-based control methods do not produce satisfactory control results with the batch process control of Czochralski (CZ) silicon monocrystalline with complex nonlinearity, large delay, and time-varying dynamics. Therefore, this paper proposes a data-driven model-free adaptive iterative learning control method (MFAILC) to achieve precision control of the batch process. Firstly, to improve the accuracy

Detecting the defects of the semiconductor devices produced using manufacturing processes is essential for quality assurance, and it requires the acquisition and accurate classification of high-resolution scanning electron microscopy images. However, owing to the difficulty of automation, the classification process is costly, and its efficiency must also be improved. To improve the classification accuracy

Quality control is an important issue in semiconductor manufacturing. Statistical process control (SPC) is known as a powerful method for accomplishing process stability and reducing variability. In this paper, we adopt the quality-oriented statistical process control (QOSPC) method. In QOSPC, product quality test data, such as electrical performance and product reliability, are incorporated into the

In advanced field plate trench power MOSFETs (FP-MOSFETs), narrow and deep trench causes lots of challenges for process integration. Especially, process optimization for silicon in trench is the most crucial. Sequential phosphorus doping process is expected to form decent silicon electrodes in narrow and deep trenches. Therefore, we studied new process optimization of FP-MOSFETs with sequential phosphorus-doped

Advanced Chemical-mechanical polishing (CMP) process not only needs to maintain stable run-to-run thickness control but also achieve better within wafer/within chip planarization performance. Furthermore, slurries or other consumable parts, like PAD and Disks selection are also the keys for CMP process optimization. The most difficult thing in CMP process is to have capability to predict and cover

This paper describes a method for rapid resolution of parametric failure during the development period. Since the number of samples is small, it is not possible to carry out general big data analysis of white defect failures of CMOS image sensors (CISs) during the development period in the same way as can be done during the mass production period. Our feature value analysis of white defects based on

In a semiconductor plasma etcher, it is becoming increasingly necessary to improve productivity by reducing unplanned equipment maintenance. Thus, predictive maintenance (PdM) is typically conducted using equipment data to predict the failure timing, after which proactive measures should be taken. In PdM, the planned maintenance schedule is updated on the basis of the predicted failure timing. However

In order to further improve the productivity of manufacturing equipment, it is indispensable to monitor the conditions of all the manufacturing equipment and not just the processing chambers. In this paper, we present a robust machine learning based deterioration diagnosis technology with harmonic sensor, which has frequency characteristics that have high sensitivity to deterioration and low sensitivity

We investigated the reduction of equivalent oxide thickness (EOT) of the in-situ formed Hf-based metal/oxide/nitride/oxide/silicon (MONOS) structure nonvolatile memory (NVM) device utilizing the HfON tunneling layer (TL). In case of the HfO 2 TL, the SiO 2 interfacial layer (IL) was formed which incrased EOT. The HfON device shows on/off current of $3.2 \times 10^{6}$ at drain voltage ( $\text{V}_{\mathrm{

Metal-insulator-semiconductor field-effect transistors (MISFETs) with high-k HfN x multilayer gate dielectrics fabricated with Si surface flattening process were investigated. The Si surface flattening process was carried out by Ar/1.0%H 2 annealing for 30 min. A higher $\text{I}_{\mathrm{ on}}/{\mathrm{ I}}_{\mathrm{ off}}$ current ratio was obtained by increasing the number of HfN x gate dielectric

Frequency response to stimuli applied to acoustic micro-electro-Mechanical Systems (MEMS) yield meaningful information of certain defects affecting such devices. This article presents the effects of three distinct root causes of failures affecting the low-frequency response of MEMS microphones: lid attach holes, die attach holes and broken vents with experimental inductions of these effects for the

Etch selectivity between layers is an important parameter in the fabrication of microelectronics and microsystems. This is particularly true in the case of isotropic gas/vapour etching methods used to release free standing structures through the selective etching of sacrificial layers. Commonly used structural materials have been reported to be largely inert when exposed to a given vapour etchant,

Fault prognosis under multiple fault modes is critical to predictive maintenance of complex tools in semiconductor manufacturing. However, the inherent data discrepancy among different tools and data imbalance with limited fault data coexist in real industrial scenario, making the task quite challenging. Therefore, this article proposes a novel two-stage deep transfer learning-based framework for prognosis

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Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

Wafer map defect pattern recognition provides useful clues to yield learning. However, most wafer maps have no special spatial patterns and are full of noises, which make pattern recognition difficult. Especially, recognizing scratch and line types of defect patterns is challenging for process and test engineers. It takes a lot of manpower to identify such patterns, as hidden defective dies may exist

In semiconductor manufacturing, data-driven methodologies have enabled the resolution of various issues, particularly yield management and enhancement. Yield, one of the crucial key performance indicators in semiconductor manufacturing, is mostly affected by production resources, i.e., equipment involved in the process. There is a lot of research on finding the correlation between yield and the status

Mura defect classification is a critical concern for thin-film transistor liquid crystal display (TFT-LCD) manufacturers. In recent years, artificial intelligence technologies have been successfully applied in numerous areas. However, such approaches require large amounts of training image data. Simultaneously, product differentiation and customization strategies have forced the TFT-LCD manufacturing

As the technology node in semiconductor manufacturing continuously shrinks its feature size and boosts the transistor density, etch bias is facing great challenges that require much better control of the edge placement error (EPE). The traditional applications of etch bias either by rule or by model are sometimes of lower precision or too much time consuming. We propose and demonstrate several innovative