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TDMR welcomes Dr. Abhisek Dixit as a new member of the TDMR Editorial Board. Dr. Dixit is an expert on device characterization and modelling of different nanometer technologies, such as bulk Si, PD, and FD-SOI BiCMOS. His experience will be of great help in reviewing and evaluating technical aspects, such as quantum computing hardware, CMOS hot-carrier and radiation effects, pulsed/RF characterization

The IEEE International Integrated Reliability Workshop (IIRW) is a unique event that takes place every year at the beautiful Fallen Leaf Lake, in Tahoe, California. This workshop brings together reliability engineers and researchers from around the world, to exchange ideas over four days in a relaxed, friendly, and informal atmosphere. The workshop focuses on the recent advances in research concerning

You are reading the Editorial of the Special Section of IEEE Transactions on Device and Materials Reliability with a collection of the best papers of the 2019 edition of the IEEE IOLTS, an established IEEE symposium which focuses for exactly one quarter of a century on the challenges and solutions for computing and electronic circuits and systems robust design . Robustness from the IOLTS technical

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Ensuring high reliability in modern integrated circuits (ICs) requires the employment of several die screening methodologies. One such technique, commonly referred to as die inking, aims to discard devices that are likely to fail, based on their proximity to known failed devices on the wafer. Die inking is traditionally performed manually by visually inspecting each manufactured wafer and thus it is

In Space applications, the scaling of transistors has made integrated circuits (ICs) more susceptible to soft errors, caused by radiation strikes. When a soft error causes a bit flip in a memory device, this event is referred to as a Single Event Upset (SEU). Since SEU errors degrade system performance and eventually lead to system failure, the design of radiation-resilient memory is substantial. This

A huge shift in classical system integration composed of heterogeneous and homogeneous substances from 2D to 2.5D or even 3D assembly is a promising solution to satisfying the requirements of electronic packages, such as high operating speed, multifunctionality, and low form factor, under the physical limits of nanoscaled transistors and bottlenecks in related fabrication technologies. However, considerable

As the standard complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) generates a leakage current due to ionizing radiation reacting with silicon in a radiological environment, radiation hardening of CMOS devices is being actively investigated. If a radiation-tolerant IC (RTIC) is designed, it is very important to examine the design possibility of an application specific IC (ASIC)

Embedded systems are being aggressively integrated in every aspect of modern life, with uses ranging from personal devices to devices deployed in critical systems, such as autonomous vehicles, aircrafts, and industrial control systems. Embedded systems handle sensitive information, which can be potentially exposed leveraging their poor security posture. In this paper, we present a novel attack vector

In this paper, we show that stress-tests can be potentially used as power-noise viruses in denial-of-service (DoS) attacks by causing voltage emergencies that may lead to data corruptions and system crashes in multi-core processors. This attack targets processors whose operating voltage has been reduced in-the-field for improving energy efficiency. To protect such undervolted processors from this type

In this paper, we propose a new learning-guided approach for diagnosis of intra-cell defects that may occur in customer returns. In the first part of the paper, only static defects modeled by stuck-at faults have been assumed. Several supervised learning algorithms were considered, with various levels of efficiency. In the second part of the paper, we have extended the previous work by dealing with

This research work reports reliability assessment of junctionless (JL) FinFET in the presence of interfacial trap charges and radiations. The degradation in performance of JL FinFET is evaluated by calculating various figure of merit. Linearity behavior of the device is studied by considering higher order coefficient of transconductance, VIP2, VIP3, IIP3, IMD3. Also, a comparative analysis of various

Modern large-scale computing systems (data centers, supercomputers, cloud and edge setups and high-end cyber-physical systems) employ heterogeneous architectures that consist of multicore CPUs, general-purpose many-core GPUs, and programmable FPGAs. The effective utilization of these architectures poses several challenges, among which a primary one is power consumption. Voltage reduction is one of

It is commonly accepted that the performance and time-to-failure of modern semiconductor transistors are seriously affected by single defects located in the insulator or at the insulator/semiconductor interface. The impact of such single defects on the device current ranges from several pico-ampere up to hundreds of nano-ampere and their characterization poses a major challenge for measurement instruments

The charge trapping effects on AlGaN/GaN HEMTs under UV illumination are investigated using the pulsed current-voltage (I-V) measurement method. The test samples are unpassivated Schottky-gate HEMTs and metal-insulator-semiconductor HEMTs (MIS-HEMTs) with SiN gate dielectric. For HEMTs, the dominant charge trapping sources are the surface trap states, whereas, for MIS-HEMTs, they are trap states in

The easy-to-use point-load on elastic foundation (PoEF) test, similar (or alternative) to a typical biaxial bending ball-on-ring test, is studied for determining the bending strength of thin silicon dies. The feasibility of this test method with a linear theory is also evaluated using a nonlinear finite element method (NFEM) by taking into account geometric and contact nonlinearities. The mechanics

The fundamental model of energy transformation between the inductor and the power transistor for the unclamped inductive switching (UIS) test is inspected. Based on the experimental results, the energy stored in the inductor at the period of the channel turn-on can be dissipated by the power transistor after the channel is turned off. In this work, a new theoretical model to well describe the electrical

The effects of high-field stress are evaluated for industrial-quality AlGaN/GaN HEMTs as a function of bias and temperature. Positive and negative threshold voltage shifts are observed, depending on stress conditions, indicating the presence of acceptor-like and donor-like traps in these devices. Worst-case transconductance degradation under rated device operating conditions is observed for devices

This paper reports an extensive analysis of the short-term effects of extremely high driving current on the performance and reliability of commercial high-power blue LEDs. To this aim, five different groups of devices, having different structures and chip areas, were submitted to increasing levels of bias current, until catastrophic failure was reached. For the first time we provide information (i)

Molded underfill process provides many benefits for higher productivity and lower cost over the conventional capillary underfill process. However, the void defects in a molded underfill process could cause pop-corning effect and solder extrusion during the reflow process. This paper presents a highly efficient and accurate hybrid model that can be applied to diagnose the void risk in vacuum molded

In modern MOS technologies continuous scaling of the geometry of transistors has led to an increase of the variability between nominally identical devices. To study the variability and reliability of such devices, a statistically significant number of samples needs to be tested. In this work we present a characterization study of defects causing BTI and RTN, performed on custom built arrays consisting

We compare and report in this work heavy-ion irradiation induced single event transients (SETs) in sub-10nm node SOI multiple gate FETs with the help of calibrated 3-D TCAD simulations. Our analysis includes the nanosheet FET (NSFET), nanowire FET (NWFET), and FinFET along with two different device design modes based on the doping profiles, namely the inversion (INV) and junctionless mode (JL). We

This paper investigates the impact of different interface trap charges (ITCs) on dual-material gate-oxide-stack double-gate TFET (DMGOSDG-TFET) by introducing localized charges (donor/acceptor) at the interface of semiconductor/insulator. For this, we have observed the effects of different ITCs on both conventional dual material control gate tunnel field effect transistor (DMCG-TFET) and dual-material

Fin height and width dependence of negative and positive Bias Temperature Instability (N/PBTI) on logic for memory high- $\kappa $ metal gate (HKMG) FinFET transistors is reported for the first time. It was observed that NBTI degradation is less severe when increasing the physical height of the silicon fin. The increased fin height results in a lower effective defect density, believed to be related

The digital designs operating in sub/near-threshold region are susceptible to timing errors due to the extreme impact of process, voltage, and temperature (PVT) variations. This paper proposes a new error-detecting latch (EDL) to mitigate the impact of PVT variations. The proposed EDL is a single-phase clocked design, which significantly reduces the clock power consumption of the design. The proposed

Continued scaling of DRAM technologies has required a limitation of the power dissipation from the logic components on-chip, while downscaling both transistor oxide thickness and gate length. One route to enable further scaling, while circumventing excessive leakage currents, is the integration of high-permittivity ( ${\kappa }$ ) metal-gate (HKMG) components into the logic and high-voltage (e.g.,

The in-memory computation of logic operations is a promising paradigm that could enable the development of highly efficient computing architectures, ideal for battery-powered devices. Indeed, Resistive Random Access Memory (RRAM) devices and the material implication logic (IMPLY) have been experimentally demonstrated to enable low-power logic-in-memory (LIM) circuits. Still, device and circuit non-idealities

In this article, a novel full-chip EM simulation tool, called EMSpice simulator is proposed. The new method starts from first principles and simultaneously considers two major interplaying physics effects in EM failure process: the hydrostatic stress and electronic current/voltage in a power grid network. The new tool starts by reading the power grid layout information from Synopsys IC Compiler. It

Ring-Oscillator (RO) are most suitable to investigate the reliability of digital CMOS circuits operating up to GHz frequencies as a good correlation has been observed between RO degradation and Product Fmax degradation. In addition, the RO degradation testing can be performed with similar equipment used for discrete device reliability characterization. In this work, we discuss the role of BTI/HCI contribution

A new low-complexity method to decode single symbol correction Reed-Solomon codes is proposed in this paper. This decoding algorithm takes advantage of the equivalent parity-check matrix representation to apply majority logic techniques that avoid the needs of computing Galois Field inversions, divisions and logarithms, unlike previous efficient solutions. The derived architectures allow to increase

The working environment of Planar Lightwave Circuit (PLC) optical splitter is complex and diverse. In addition to withstanding the test of environmental temperature changes, the device may also be affected by mechanical shock such as vibration. Through the thermal-vibration coupling online test, it was found that the insertion loss of the PLC optical splitter changes significantly when the vibration

In this paper, the total ionizing dose (TID) effects of the Sense-Switch pFLASH cell consisting of sense (T 1 ) and switch (T 2 ) co-floating gate pFLASH transistors fabricated with a $0.13\mu \text{m}$ eFLASH technology are studied. Firstly, the impact of TID effects on the programming/erasing state’s characteristics of T 1 and T 2 transistors are mainly analyzed though Current-Voltage (I-V) and

We report on a novel semiconductor reliability technique that incorporates an electrically detected magnetic resonance (EDMR) spectrometer within a conventional semiconductor wafer probing station. EDMR is an ultrasensitive electron paramagnetic resonance technique with the capability to provide detailed physical and chemical information about reliability limiting defects in semiconductor devices.