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2020 Index IEEE Transactions on Device and Materials Reliability Vol. 20 IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2021-01-11
Presents the 2020 subject/author index for this publication.
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Editorial Kudos to Our Reviewers IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-12-10 Edmundo A. Gutiérrez-D.
The technical lpar contributions of the authors to T-DMR are quite relevant to our readership. However, that quality comes associated with the amount of effort donated to our “cause” by our manuscript reviewers. These are the people who ensure that the manuscripts appearing in T-DMR are of the highest quality. Our reviewers have a demonstrated track record of efficient and timely manuscript review
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Editorial for December 2020 IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-12-10 Edmundo A. Gutiérrez-D.
It is my pleasure to announce the TDMR community the appointment of Dr. Karumbu N. Meyyappan as Editor of TDMR. Dr. Meyyappan is an expert on Interconnects, BGA, Sockets/Connectors, Substrate Technologies, Board Technologies. Dr. Meyyappan received the Ph.D. degree from the University of Maryland at College (Microelectronic Packaging—Mechanical Engineering). He has a large industry experience with
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Simultaneous and Sequential Triggering in Multi-Finger Floating-Base SCRs Depending on TLP Pulse Rise Time IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-10-26 Hasan Karaca; Clément Fleury; Steffen Holland; Vasantha Kumar; Hans-Martin Ritter; Guido Notermans; Dionyz Pogany
Multi-finger floating-base silicon controlled rectifiers (SCRs) of discrete technologies are investigated by transmission line pulses (TLP) with short (300ps) and long (10ns) pulse rise times (RT). Transient interferometric mapping (TIM) is applied to study the finger triggering dynamics. The measurements are correlated with TCAD simulation. It is found that for short RT the fingers trigger simultaneously
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Low-Leakage and Variable VHOLD Power Clamp for Wide Stress Time Range From ESD to Surge Test IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-11-11 Koki Narita; Mototsugu Okushima
In recent years, on-chip clamp designs for enhancing destructive immunity of ICs mounted on systems against residual currents of system level immunity tests have been proposed. To cope with a long duration pulse (several tens ${\mu }\text{s}$ ) such as a surge immunity test is one of the issues of the system level on-chip clamp. A clamp combined RC-trigger and static trigger is one approach to achieve
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Transient Overshoot Voltages During VF-TLP Pulses for Bipolar Devices in the Presence of Lowly Doped Regions IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-11-11 Steffen Holland; Guido Notermans; Hans-Martin Ritter
The transient overshoot behavior of bipolar devices is investigated by means of very fast transmission line pulses (VF-TLP). All devices under investigation, a forward biased diode, an open base transistor and a SCR comprise a lowly doped region (LDR). Measurements have been done for rise times of 0.3ns and 1ns. To separate the voltage drop inside the device from parasitic contributions TCAD simulations
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Electron Beam Induced Degradation in Electrical Characteristics of Optocoupler IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-10-06 R. Sujatha; Ramakrishna Damle; Dinesh Kumar
This article describes the electrical degradation in the I-V characteristics and the Current Transfer Ratio (CTR) of commercial optocoupler (4N35) exposed to an electron beam. The devices are exposed to an electron beam of various doses and the I-V characteristics of LED and output characteristics of the phototransistor are measured as a function of accumulated electron dose. The result indicates that
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Accelerated Stress Tests and Statistical Reliability Analysis of Metal-Oxide/GaN Nanostructured Sensor Devices IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-10-05 Md Ashfaque Hossain Khan; Ratan Debnath; Abhishek Motayed; Mulpuri V. Rao
In this work, sensor die/process and packaging reliabilities of metal-oxide/GaN nanowire-based gas sensors have been studied for the first time, using industry standard accelerated lifetime tests, such as- High Temperature Operating Life, High Temperature Storage Life, Temperature Cycling Test and Highly Accelerated Stress Test. The metal-oxide functionalization used for sensing ethanol exposure in
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Integer Codes Correcting Single Errors and Detecting Burst Errors Within a Byte IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-10-26 Aleksandar Radonjic
Correcting single and detecting adjacent errors has become important in memory systems using high density DRAM chips. The reason is that, in these systems, the strike of a single energetic particle can upset one or more adjacent bits. In this article, we present a simple solution for this problem based on integer codes capable of correcting single errors and detecting ${l}$ -bit burst errors confined
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Using the Octagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-10-26 Vinicius Vono Peruzzi; William Souza Cruz; Gabriel Augusto da Silva; Eddy Simoen; Cor Claeys; Salvador Pinillos Gimenez
This article describes an experimental comparative study of the matching between the Octo conventional (octagonal gate geometry) and Conventional (rectangular gate shape) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) Integrated Circuits (ICs) technology and exposed to different X-rays
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Impact of Gamma-Ray Radiation on DC and RF Performance of 10-nm Bulk N-Channel FinFETs IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-10-27 K. Aditya; R. Singh; M. Kumar; R. Vega; A. Dixit
In this article, the impact of gamma-ray radiation on DC and RF response of 10-nm bulk n-channel FinFETs is investigated. Firstly, the radiation tolerance of these devices under DC measurement conditions is reported as various layout level device parameters, such as the gate length ( $L_{G}$ ), number of fins ( $N_{FIN}$ ), and number of fingers ( $N_{FINGER}$ ) are scaled. Then for the first time
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Trap-Assisted and Stress Induced Safe Operating Area Limits of AlGaN/GaN HEMTs IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-10-26 Bhawani Shankar; Ankit Soni; Srinivasan Raghavan; Mayank Shrivastava
This experimental study reports a systematic investigation of Safe Operating Area (SOA) limits in AlGaN/GaN HEMT using sub- $\mu \text{s}$ pulse characterization. During stress, on-the fly Raman and CV characterization is done to probe mechanical strain evolution and the resultant defect/ trap generation across HEMT. Role of carrier trapping induced electric field shift and associated piezoelectric
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Various Reliability Investigations of Low Temperature Polycrystalline Silicon Tunnel Field-Effect Thin-Film Transistor IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-11-03 William Cheng-Yu Ma; Hui-Shun Hsu; Hsiao-Chun Wang
Various reliability issues of low temperature polycrystalline silicon (LTPS) tunnel field-effect transistor (TFET) are comprehensively studied for the first time and compared with conventional LTPS thin-film transistor (TFT). For the positive and negative gate bias stress (P/NGBS) instability, the NGBS causes more serious electrical degradation for both LTPS-TFETs and TFTs because of the higher trap
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Accelerated Degradation of IGBTs Due to High Gate Voltage at Various Temperature Environments IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-09-22 You-Cheol Jang; Soo-Seong Kim; Min-Woo Ha; Yong-Sang Kim
In this study, degradation phenomena due to gate bias stress at elevated temperature for the reliability test of punch-through IGBTs, which are widely used in DC circuit systems for automotive applications, were investigated. For the reliability tests of various temperatures, 4000 times temperature cycle stress was applied in IGBTs between −40°C and 200°C to accelerate the degradation process using
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A Physics-Based Single Event Transient Pulse Width Model for CMOS VLSI Circuits IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-09-10 Y. M. Aneesh; B. Bindu
The single-event transients in MOSFETs due to heavy ion strikes introduce soft errors in sub-50 $nm$ CMOS VLSI circuits. These transients are easily captured and propagated in high-frequency CMOS VLSI circuits. The capture rate mainly depends on the single-event transient (SET) pulse width and the clock frequency of the circuits. An estimation of the SET pulse width through a physics-based model that
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A Gate-Grounded NMOS-Based Dual-Directional ESD Protection With High Holding Voltage for 12V Application IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-09-08 Kyoung-Il Do; Bo-Bae Song; Yong-Seo Koo
Dual-direction electrostatic discharge (ESD) protection devices can discharge both positive and negative ESD surges, owing to their excellent area efficiency. This study proposes a novel dual-direction MOSFET ESD protection device with a high holding voltage. Most existing dual-direction ESD protection devices are based on silicon-controlled rectifiers (SCR). Among them, the low triggering dual-directional
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Table of contents IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-09-03
Presents the table of contents for this issue of the publication.
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IEEE Transactions on Device and MaterialsReliability publication information IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-09-03
Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
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Editorial for New TDMR Editor Byoung Woon Min IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-09-03 Byoung Woon Min
I would like to introduce Dr. Byoung Woon Min as a new TDMR Editor. Dr. Min is going to support TDMR in the topic of memories and advanced semiconductor devices technologies.
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Editorial for TDMR Editor Oscar Huerta IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-09-03 Oscar Huerta
Iam glad to introduce Dr. Oscar Huerta as a new TDMR Editor. Dr. Huerta is an expert on device physics, degradation, reliability, characterization, and modeling. He got his Ph.D. title for INAOE, Mexico, in 2019, with the thesis “ Charge-trapping dynamics in MOSFETs: An experimental approach with magnetic fields. ” He has seven years of experience in academia and industry, and has spent time at the
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A Study of the Relationship Between Endurance and Retention Reliability for a HfOₓ-Based Resistive Switching Memory IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-07-07 Wei-Min Chung; Yao-Feng Chang; Yu-Lin Hsu; Y. -C. Daphne Chen; Chao-Cheng Lin; Chang-Hsieh Lin; Jihperng Leu
This study determines the relationship between retention and endurance reliability for a HfO x -based resistive random access memory (ReRAM). A TiN (15 nm) / HfO x (6 nm) / Ti (10 nm) / TiN (40 nm) stacked structure is fabricated and tested to verify its basic characteristics and reliability. The high resistance states (HRS) retention behavior is characterized and is found to degrade over 100x on the
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Temperature Dependent Reliability of Polysilicon Emitter Bipolar Transistors Under High Current Stress IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-07-13 Kunfeng Zhu; Peijian Zhang; Wensuo Chen; Xueliang Xu; Kaizhou Tan; Jinle Gui; Yonghui Yang; Feiyu Jiang
Temperature dependent high forward current stress induced drift of electrical parameters (current gain ( ${\beta }$ ) variations, emitter resistance ( R $_{E}$ ) decrease) in polysilicon emitter bipolar transistors has been revealed. It shows that the ambient temperature surrounding the test device, i.e., the lattice temperature, plays a key role in the reliability issues of the polysilicon emitter
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Effect of Device Dimensions, Layout and Pre-Gate Carbon Implant on Hot Carrier Induced Degradation in HKMG nMOS Transistors IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-07-07 Pardeep Duhan; V. Ramgopal Rao; Nihar R. Mohapatra
The hot carrier (HC) induced degradation has become a major concern in advanced CMOS technologies because of non-scalable $\text{V}_{\mathrm{ DD}}$ . In this work, we have shown that the HC induced degradation in gate-first HKMG nMOS transistors can be modulated by optimizing the device width, lanthanum capping layer thickness, and pre-gate carbon (C) implant. The physics responsible for these observations
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Time Dependent Shift in SOA Boundary and Early Breakdown of Epi-Stack in AlGaN/ GaN HEMTs Under Fast Cyclic Transient Stress IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-07-07 Bhawani Shankar; Swati Shikha; Anant Singh; Jeevesh Kumar; Ankit Soni; Sayak Dutta Gupta; Srinivasan Raghavan; Mayank Shrivastava
This experimental study reports first observations of (i) SOA boundary shift in AlGaN/GaN HEMTs and (ii) early time-to-fail of vertical AlGaN/GaN epi-stack under fast changing (sub-10ns rise time) cyclic pulse transient stress, which otherwise qualified for 600 V DC stress. It is shown that a epi stack qualified for 10 years lifetime under DC stress, fails faster under cyclic transient stress. The
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NrGO Floating Gate/SiOXNY Tunneling Layer Stack for Nonvolatile Flash Memory Applications IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-07-20 Mahesh Soni; Ajay Soni; Satinder K. Sharma
This paper presents an ultra–thin silicon oxynitride (SiO X N Y , 4 nm) tunneling layer, nitrogen functionalized reduced graphene oxide (NrGO, 3–5 layer) floating gate (FG) and poly (methyl methacrylate) (PMMA, 60 nm) blocking layers based Al/PMMA/NrGO/SiO X N Y /p–Si/Au, non–volatile flash memory (NVFM) structures. The ultra–thin SiO X N Y helps in improving the interface with Si, resulting in lower
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Investigation of Chip Temperature on Response Characteristics of the Humidity Sensor From ppm to %RH IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-07-24 Md Rahat Mahboob; Anwar Ulla Khan; Lokesh Kumar; Tarikul Islam
Many research articles are reported on humidity measurement in the literature. But there is no critical study of temperature on the response characteristics of the humidity sensors, particularly in ppm-level. Developing an experimental set up for studying the temperature effect is challenging as the variation of the ambient temperature not only varies the response of the sensor but also the humidity
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Reliability-Oriented Automated Design of Double-Sided Cooling Power Module: A Thermo-Mechanical-Coordinated and Multi-Objective-Oriented Optimization Methodology IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-07-27 Zheng Zeng; Kaihong Ou; Liang Wang; Yue Yu
Compared with the traditional single-sided cooling (SSC) power module, owing to the decreased thermal resistance and packaging parasitics, the double-sided cooling (DSC) power module is a promising solution of the motor drive for electric vehicle (EV) implementation. However, the lack of the model to characterize the thermo-mechanical interaction mechanism in the DSC power module challenges the co-design
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Reliability of NAND Flash Memory as a Weight Storage Device of Artificial Neural Network IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-07-27 Md Mehedi Hasan; Biswajit Ray
NAND flash memory is a popular choice for storing a large number of model weights of an Artificial Neural Network (ANN) in many Internet of Things devices and edge computing applications. While being used as a weight storage device, the bit error rate of flash memory plays a significant role in the performance of the ANN application. In this paper, we propose two novel weight storage method in NAND
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Investigation of Single Event Transient Effects in Junctionless Accumulation Mode MOSFET IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-08-04 Avashesh Dubey; Rakhi Narang; Manoj Saxena; Mridula Gupta
The Junctionless Accumulation Mode Double Gate MOSFET (JAM DG MOSFET) is a promising novel architecture for future nano-scaled devices because of its outstanding electrical characteristics, e.g., lower subthreshold swing, lower drain induced barrier lowering, i.e., lower short channel effects and higher $\text{I}_{\mathrm{ ON}}/\text{I}_{\mathrm{ OFF}}$ ratio. In this paper, a comprehensive analysis
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In Situ Transmission Electron Microscopy Study of Conductive Filament Formation in Copper Oxides IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-08-10 Xinchun Tian; Sanaz Yazdanparast; Geoff Brennecka; Xiaoli Tan
The structural and electrical property changes of two types of copper oxides (CuO and Cu 2 O) under voltage bias are studied with in situ transmission electron microscopy (TEM). The phases of different materials are confirmed with electron diffraction. In both types of oxides, dynamic conductive path formation and dissolution are observed. The decrease in resistance of CuO film is found to be accompanied
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Low Temperature and High Pressure Oxidized Al2O3 as Gate Dielectric for AlInN/GaN MIS-HEMTs IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-08-13 Srikanth Kanaga; Gourab Dutta; Bhuvnesh Kushwah; Nandita DasGupta; Amitava DasGupta
Low temperature (LT) and high pressure oxidized (HPO) Al 2 O 3 is investigated as a gate dielectric for AlInN/GaN MIS-HEMTs. The time and temperature of the oxidation process was optimized for best performance. X-ray photoelectron spectroscopic (XPS) studies confirmed the near complete oxidation of Al to form Al 2 O 3 . MIS-HEMTs with 7 nm thick LT-HPO Al 2 O 3 showed six orders reduction in gate leakage
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Method of Precise Positioning for Defect Failure Analysis Based on Nano-Probing and EBAC IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-08-17 Kuibo Lan; Li Tian; Yinlong Wei; Xiaodi Huang; Guoxuan Qin
Failure analysis (FA) becomes increasingly crucial for semiconductor industries with the scale-down and larger integration of devices. In order to overcome the limitation of traditional optical resolution for FA techniques, this article proposed an effective method of precise positioning of circuit defect based on localized probing technique, nano-probing and electron beam absorbed current (EBAC).
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Introducing IEEE Collabratec IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-09-03
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IEEE Transactions on Device and Materials Reliability information for authors IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-09-03
These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
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The Influence of N-Type Buried Layer on SCR ESD Protection Devices IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-09-04 Yang Wang; Xijun Chen; Dandan Jia; Jun Lu; Weipeng Wei; Peng Dong
This article investigates the effect of N-type buried layer (NBL) on the holding voltage and failure current of conventional low voltage triggered silicon-controlled rectifier (LVTSCR) and conventional dual directional silicon-controlled rectifier (DDSCR) devices. LVTSCR and DDSCR with N-type buried layer are fabricated on a 0.18- $\mu \text{m}$ Bipolar CMOS DMOS (BCD) technology. In order to verify
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Effect of Crack Evolution on the Resistance and Current Density of the Al Metallization in the IGBT Module During Power Cycling IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-09-03 Fei Qin; Jingyi Zhao; Tong An; Jingru Dai; Yanwei Dai; Pei Chen
This study quantifies the correlations between crack evolution and electrical performance degradation of the Al metallization in insulated gate bipolar transistor (IGBT) modules. The resistance of the Al metallization under different power cycling times was measured by the four-point probe method. The cracks that occur in the Al metallization were investigated by measuring crack geometric parameters
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Short Circuit Detection and Fault Current Limiting Method for IGBTs IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-08-24 Mohamed Halick Mohamed Sathik; Prasanth Sundararajan; Firman Sasongko; Josep Pou; Viswanathan Vaiyapuri
Power devices may become damaged or even fail completely due to over-current caused by external factors such as ac line transients, mechanical overload, misfiring, inverter shoot-through, etc. Some of these incidents can result in a very high current (few times higher than the system’s rated current) flow through the electrical drive system. Electrical machines have the capability to withstand very
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On-Chip Adaptive VDD Scaled Architecture of Reliable SRAM Cell With Improved Soft Error Tolerance IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-08-24 Neha Gupta; Ambika Prasad Shah; Rana Sagar Kumar; Tanisha Gupta; Sajid Khan; Santosh Kumar Vishvakarma
Negative bias temperature instability (NBTI) is the major reliability issue which affects many parameters such as threshold voltage, mobility, and leakage current. The threshold voltage of the PMOS transistor increases due to NBTI with stress time, which degrades the circuit performance. In this article, we have proposed a novel reliable data-dependent low power 10T SRAM cell, which is highly stable
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Hybrid Multi-Graphene/Si Avalanche Transit Time Terahertz Power Oscillator: Theoretical Reliability and Experimental Feasibility Studies IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-08-21 Debraj Chakraborty; Sulagna Chatterjee; Moumita Mukherjee
The prospects of Terahertz (0.3 THz-5.0 THz) power generation with laterally doped hybrid Graphene/Si (Single-Layer ( $\text{S}_{\mathrm{ L}}\text{G}$ ), Bi-Layer ( $\text{B}_{\mathrm{ L}}\text{G}$ ) and Multi-Layer ( $\text{M}_{\mathrm{ L}}\text{G}$ )) Mixed Tunneling Avalanche Transit Time (GL-h-MITATT) oscillator is explored through an indigenously developed and experimentally verified self-consistent
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Investigation of Quantization Effects on RTS Due to Oxide Traps Induced by Channel Hot-Carrier-Stressing in pMOSFETs IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-08-19 Tanvir Ahmed; Zeynep Çelik-Butler
Although it is the worst degradation mechanism, the effect of channel hot carrier (CHC) stressing on random telegraph signals (RTS) has not been given enough attention in pMOSFETs. We report on the effect of CHC stressing on different RTS trap parameters namely screened scattering coefficient which controls the amount of charge carrier mobility fluctuations due to remote Coulomb scattering by the trap
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Effect of Different PBO-Based RDL Structures on Chip-Package Interaction Reliability of Wafer Level Package IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-06-25 Chong Qin; Yi Li; Haiyang Mao
In this paper, CPI (chip-package interaction) reliability of WLP (wafer level package) was investigated. PBO (Polybenzoxazole)-based RDL (redistribution layer) structure was the primary focus. Firstly, the stress distribution for PBO structures was studied by simulation. Secondly, two types of the chip with different PBO structures completed the accelerating experiments. Based on our investigation
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A VDD Correction Method for Static Stability Test of SRAM Bit Cell IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-06-25 Yuyan Liu; Zheng Shi; Weiwei Pan; Fan Lan
SRAM stability is a major concern in nanometer CMOS technologies. As the most important metrics of SRAM static stability, the static characteristics of SRAM are derived by static characteristic curves (read butterfly curve, standby butterfly curve, read N curve, write N curve and WNM curve). This paper deduces the read butterfly curve transfer function as an example to show the effect of supply voltage
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Applying a Statistical Model to the Observed Texture Evolution of Fatigued Metal Films IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-06-22 Barbara Pedretscher; Michael Nelhiebel; Barbara Kaltenbacher
Reliably modeling fatigue induced degradation of metal films requires a consistent mathematical description of the physically relevant damage driving forces. The processes, which trigger deformation, damage and eventually failure, have to be included and combined in a physically meaningful way to obtain a valid model. Therefore, it is essential to consider the material response to applied stress, as
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Oxide Edge Trap Density Extraction in Silicon Nanowire MOSFET From Tunnel Current Noise Measurement in Gated Diode Like Arrangement IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-06-05 Deepak Kumar Sharma; Arnab Datta
Edge traps in the gate oxide of silicon nanowire MOSFETs have been extracted from tunnel current noise measurement in a gated diode like arrangement. We have found that, low frequency noise in tunnel current results from collective response of the edge traps available within the gate oxide surrounding band-to-band generation (BTBG) region of silicon nanowire, and when the BTBG region is accessed by
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[Front cover] IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-06-05
Presents the front cover for this issue of the publication.
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Editorial Introducing New TDMR Editor Abhisek Dixit IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-06-05 Abhisek Dixit
TDMR welcomes Dr. Abhisek Dixit as a new member of the TDMR Editorial Board. Dr. Dixit is an expert on device characterization and modelling of different nanometer technologies, such as bulk Si, PD, and FD-SOI BiCMOS. His experience will be of great help in reviewing and evaluating technical aspects, such as quantum computing hardware, CMOS hot-carrier and radiation effects, pulsed/RF characterization
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Guest Editorial IEEE International Integrated Reliability Workshop (IIRW) 2019 IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-06-05 Stanislav Tyaginov; Zakariae Chbili
The IEEE International Integrated Reliability Workshop (IIRW) is a unique event that takes place every year at the beautiful Fallen Leaf Lake, in Tahoe, California. This workshop brings together reliability engineers and researchers from around the world, to exchange ideas over four days in a relaxed, friendly, and informal atmosphere. The workshop focuses on the recent advances in research concerning
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Editorial—Robust System Design IEEE IOLTS 2019 IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-06-05 Dimitris Gizopoulos; Dan Alexandrescu
You are reading the Editorial of the Special Section of IEEE Transactions on Device and Materials Reliability with a collection of the best papers of the 2019 edition of the IEEE IOLTS, an established IEEE symposium which focuses for exactly one quarter of a century on the challenges and solutions for computing and electronic circuits and systems robust design . Robustness from the IOLTS technical
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IEEE Transactions on Device and Materials Reliability information for authors IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-06-05
Provides instructions and guidelines to prospective authors who wish to submit manuscripts.
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Physical Study of SiC Power MOSFETs Towards HTRB Stress Based on C-V Characteristics IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-06-01 Wadia Jouha; Mohamed Masmoudi; Ahmed El Oualkadi; Eric Joubert; Pascal Dherbécourt
The quality of the gate-oxide and Oxide/SiC interfaces is one of the crucial issues in the implementation of silicon carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) in the industrial power electronic applications. The main goal of this work is to investigate the gate-oxide integrity and to understand the basic phenomena involved on 4H-SiC MOSFET by the mean of Capacitance-Voltage
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Insights Into the Effect of TiN Thickness Scaling on DC and AC NBTI Characteristics in Replacement Metal Gate pMOSFETs IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-05-28 Longda Zhou; Qianqian Liu; Hong Yang; Zhigang Ji; Hao Xu; Bo Tang; Eddy Simoen; Haojie Jiang; Ying Luo; Xiaolei Wang; Xueli Ma; Yongliang Li; Jun Luo; Huaxiang Yin; Chao Zhao; Wenwu Wang
Fast characterization methods are utilized to investigate DC and AC negative bias temperature instability (NBTI) characteristics in pMOSFETs with different TiN capping layer thicknesses ( ${t} _{\mathrm{ TiN}}$ ). The impacts of ${t} _{\mathrm{ TiN}}$ scaling on the threshold voltage shift ( ${\Delta }\text{V}_{\mathrm{ T}}$ ), pre-existing hole traps ( ${\Delta }\text{V}_{\mathrm{ HT}}$ ), generated
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Fundamental Thermal Limits on Data Retention in Low-Voltage CMOS Latches and SRAM IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-05-22 Elahe Rezaei; Marco Donato; William R. Patterson; Alexander Zaslavsky; R. Iris Bahar
Ultra-low-power systems with substantial computing capacity require latches and SRAMs to operate at extremely low supply voltages. However, with aggressive technology scaling, reliability becomes a major challenge due to unavoidable process variations and the presence of multiple noise sources, including intrinsic thermal noise. This paper provides a quantitative measure of reliability by calculating
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Automated Die Inking IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-05-19 Constantinos Xanthopoulos; Arnold Neckermann; Paulus List; Klaus-Peter Tschernay; Peter Sarson; Yiorgos Makris
Ensuring high reliability in modern integrated circuits (ICs) requires the employment of several die screening methodologies. One such technique, commonly referred to as die inking, aims to discard devices that are likely to fail, based on their proximity to known failed devices on the wafer. Die inking is traditionally performed manually by visually inspecting each manufactured wafer and thus it is
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SRAM Radiation Hardening Through Self-Refresh Operation and Error Correction IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-05-15 M. Sultan M. Siddiqui; Sharma Ruchi; Loi Van Le; Taegeun Yoo; Ik-Joon Chang; Tony Tae-Hyoung Kim
In Space applications, the scaling of transistors has made integrated circuits (ICs) more susceptible to soft errors, caused by radiation strikes. When a soft error causes a bit flip in a memory device, this event is referred to as a Single Event Upset (SEU). Since SEU errors degrade system performance and eventually lead to system failure, the design of radiation-resilient memory is substantial. This
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Demonstration of an Equivalent Material Approach for the Strain-Induced Reliability Estimation of Stacked-Chip Packaging IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-05-15 Chang-Chun Lee; Pei-Chen Huang; Yan-Cian Lin; Bow-Tsin Chian
A huge shift in classical system integration composed of heterogeneous and homogeneous substances from 2D to 2.5D or even 3D assembly is a promising solution to satisfying the requirements of electronic packages, such as high operating speed, multifunctionality, and low form factor, under the physical limits of nanoscaled transistors and bottlenecks in related fabrication technologies. However, considerable
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Design for High Reliability of CMOS IC With Tolerance on Total Ionizing Dose Effect IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-05-14 Minwoong Lee; Seongik Cho; Namho Lee; Jongyeol Kim
As the standard complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) generates a leakage current due to ionizing radiation reacting with silicon in a radiological environment, radiation hardening of CMOS devices is being actively investigated. If a radiation-tolerant IC (RTIC) is designed, it is very important to examine the design possibility of an application specific IC (ASIC)
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Stealthy Information Leakage Through Peripheral Exploitation in Modern Embedded Systems IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-05-12 Dimitrios Tychalas; Anastasis Keliris; Michail Maniatakos
Embedded systems are being aggressively integrated in every aspect of modern life, with uses ranging from personal devices to devices deployed in critical systems, such as autonomous vehicles, aircrafts, and industrial control systems. Embedded systems handle sensitive information, which can be potentially exposed leveraging their poor security posture. In this paper, we present a novel attack vector
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Run-Time Protection of Multi-Core Processors From Power-Noise Denial-of-Service Attacks IEEE Trans. Device Mat Reliab. (IF 1.407) Pub Date : 2020-05-12 Vasileios Tenentes; Shidhartha Das; Daniele Rossi; Bashir M. Al-Hashimi
In this paper, we show that stress-tests can be potentially used as power-noise viruses in denial-of-service (DoS) attacks by causing voltage emergencies that may lead to data corruptions and system crashes in multi-core processors. This attack targets processors whose operating voltage has been reduced in-the-field for improving energy efficiency. To protect such undervolted processors from this type