Presents the 2020 subject/author index for this publication.

The technical lpar contributions of the authors to T-DMR are quite relevant to our readership. However, that quality comes associated with the amount of effort donated to our “cause” by our manuscript reviewers. These are the people who ensure that the manuscripts appearing in T-DMR are of the highest quality. Our reviewers have a demonstrated track record of efficient and timely manuscript review

It is my pleasure to announce the TDMR community the appointment of Dr. Karumbu N. Meyyappan as Editor of TDMR. Dr. Meyyappan is an expert on Interconnects, BGA, Sockets/Connectors, Substrate Technologies, Board Technologies. Dr. Meyyappan received the Ph.D. degree from the University of Maryland at College (Microelectronic Packaging—Mechanical Engineering). He has a large industry experience with

Multi-finger floating-base silicon controlled rectifiers (SCRs) of discrete technologies are investigated by transmission line pulses (TLP) with short (300ps) and long (10ns) pulse rise times (RT). Transient interferometric mapping (TIM) is applied to study the finger triggering dynamics. The measurements are correlated with TCAD simulation. It is found that for short RT the fingers trigger simultaneously

In recent years, on-chip clamp designs for enhancing destructive immunity of ICs mounted on systems against residual currents of system level immunity tests have been proposed. To cope with a long duration pulse (several tens ${\mu }\text{s}$ ) such as a surge immunity test is one of the issues of the system level on-chip clamp. A clamp combined RC-trigger and static trigger is one approach to achieve

The transient overshoot behavior of bipolar devices is investigated by means of very fast transmission line pulses (VF-TLP). All devices under investigation, a forward biased diode, an open base transistor and a SCR comprise a lowly doped region (LDR). Measurements have been done for rise times of 0.3ns and 1ns. To separate the voltage drop inside the device from parasitic contributions TCAD simulations

This article describes the electrical degradation in the I-V characteristics and the Current Transfer Ratio (CTR) of commercial optocoupler (4N35) exposed to an electron beam. The devices are exposed to an electron beam of various doses and the I-V characteristics of LED and output characteristics of the phototransistor are measured as a function of accumulated electron dose. The result indicates that

In this work, sensor die/process and packaging reliabilities of metal-oxide/GaN nanowire-based gas sensors have been studied for the first time, using industry standard accelerated lifetime tests, such as- High Temperature Operating Life, High Temperature Storage Life, Temperature Cycling Test and Highly Accelerated Stress Test. The metal-oxide functionalization used for sensing ethanol exposure in

Correcting single and detecting adjacent errors has become important in memory systems using high density DRAM chips. The reason is that, in these systems, the strike of a single energetic particle can upset one or more adjacent bits. In this article, we present a simple solution for this problem based on integer codes capable of correcting single errors and detecting ${l}$ -bit burst errors confined

This article describes an experimental comparative study of the matching between the Octo conventional (octagonal gate geometry) and Conventional (rectangular gate shape) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) Integrated Circuits (ICs) technology and exposed to different X-rays

In this article, the impact of gamma-ray radiation on DC and RF response of 10-nm bulk n-channel FinFETs is investigated. Firstly, the radiation tolerance of these devices under DC measurement conditions is reported as various layout level device parameters, such as the gate length ( $L_{G}$ ), number of fins ( $N_{FIN}$ ), and number of fingers ( $N_{FINGER}$ ) are scaled. Then for the first time

This experimental study reports a systematic investigation of Safe Operating Area (SOA) limits in AlGaN/GaN HEMT using sub- $\mu \text{s}$ pulse characterization. During stress, on-the fly Raman and CV characterization is done to probe mechanical strain evolution and the resultant defect/ trap generation across HEMT. Role of carrier trapping induced electric field shift and associated piezoelectric

Various reliability issues of low temperature polycrystalline silicon (LTPS) tunnel field-effect transistor (TFET) are comprehensively studied for the first time and compared with conventional LTPS thin-film transistor (TFT). For the positive and negative gate bias stress (P/NGBS) instability, the NGBS causes more serious electrical degradation for both LTPS-TFETs and TFTs because of the higher trap

In this study, degradation phenomena due to gate bias stress at elevated temperature for the reliability test of punch-through IGBTs, which are widely used in DC circuit systems for automotive applications, were investigated. For the reliability tests of various temperatures, 4000 times temperature cycle stress was applied in IGBTs between −40°C and 200°C to accelerate the degradation process using

The single-event transients in MOSFETs due to heavy ion strikes introduce soft errors in sub-50 $nm$ CMOS VLSI circuits. These transients are easily captured and propagated in high-frequency CMOS VLSI circuits. The capture rate mainly depends on the single-event transient (SET) pulse width and the clock frequency of the circuits. An estimation of the SET pulse width through a physics-based model that

Dual-direction electrostatic discharge (ESD) protection devices can discharge both positive and negative ESD surges, owing to their excellent area efficiency. This study proposes a novel dual-direction MOSFET ESD protection device with a high holding voltage. Most existing dual-direction ESD protection devices are based on silicon-controlled rectifiers (SCR). Among them, the low triggering dual-directional

Presents the table of contents for this issue of the publication.

Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.

I would like to introduce Dr. Byoung Woon Min as a new TDMR Editor. Dr. Min is going to support TDMR in the topic of memories and advanced semiconductor devices technologies.

Iam glad to introduce Dr. Oscar Huerta as a new TDMR Editor. Dr. Huerta is an expert on device physics, degradation, reliability, characterization, and modeling. He got his Ph.D. title for INAOE, Mexico, in 2019, with the thesis “ Charge-trapping dynamics in MOSFETs: An experimental approach with magnetic fields. ” He has seven years of experience in academia and industry, and has spent time at the

This study determines the relationship between retention and endurance reliability for a HfO x -based resistive random access memory (ReRAM). A TiN (15 nm) / HfO x (6 nm) / Ti (10 nm) / TiN (40 nm) stacked structure is fabricated and tested to verify its basic characteristics and reliability. The high resistance states (HRS) retention behavior is characterized and is found to degrade over 100x on the

Temperature dependent high forward current stress induced drift of electrical parameters (current gain ( ${\beta }$ ) variations, emitter resistance ( R $_{E}$ ) decrease) in polysilicon emitter bipolar transistors has been revealed. It shows that the ambient temperature surrounding the test device, i.e., the lattice temperature, plays a key role in the reliability issues of the polysilicon emitter

The hot carrier (HC) induced degradation has become a major concern in advanced CMOS technologies because of non-scalable $\text{V}_{\mathrm{ DD}}$ . In this work, we have shown that the HC induced degradation in gate-first HKMG nMOS transistors can be modulated by optimizing the device width, lanthanum capping layer thickness, and pre-gate carbon (C) implant. The physics responsible for these observations

This experimental study reports first observations of (i) SOA boundary shift in AlGaN/GaN HEMTs and (ii) early time-to-fail of vertical AlGaN/GaN epi-stack under fast changing (sub-10ns rise time) cyclic pulse transient stress, which otherwise qualified for 600 V DC stress. It is shown that a epi stack qualified for 10 years lifetime under DC stress, fails faster under cyclic transient stress. The

This paper presents an ultra–thin silicon oxynitride (SiO X N Y , 4 nm) tunneling layer, nitrogen functionalized reduced graphene oxide (NrGO, 3–5 layer) floating gate (FG) and poly (methyl methacrylate) (PMMA, 60 nm) blocking layers based Al/PMMA/NrGO/SiO X N Y /p–Si/Au, non–volatile flash memory (NVFM) structures. The ultra–thin SiO X N Y helps in improving the interface with Si, resulting in lower

Many research articles are reported on humidity measurement in the literature. But there is no critical study of temperature on the response characteristics of the humidity sensors, particularly in ppm-level. Developing an experimental set up for studying the temperature effect is challenging as the variation of the ambient temperature not only varies the response of the sensor but also the humidity

Compared with the traditional single-sided cooling (SSC) power module, owing to the decreased thermal resistance and packaging parasitics, the double-sided cooling (DSC) power module is a promising solution of the motor drive for electric vehicle (EV) implementation. However, the lack of the model to characterize the thermo-mechanical interaction mechanism in the DSC power module challenges the co-design

NAND flash memory is a popular choice for storing a large number of model weights of an Artificial Neural Network (ANN) in many Internet of Things devices and edge computing applications. While being used as a weight storage device, the bit error rate of flash memory plays a significant role in the performance of the ANN application. In this paper, we propose two novel weight storage method in NAND

The Junctionless Accumulation Mode Double Gate MOSFET (JAM DG MOSFET) is a promising novel architecture for future nano-scaled devices because of its outstanding electrical characteristics, e.g., lower subthreshold swing, lower drain induced barrier lowering, i.e., lower short channel effects and higher $\text{I}_{\mathrm{ ON}}/\text{I}_{\mathrm{ OFF}}$ ratio. In this paper, a comprehensive analysis

The structural and electrical property changes of two types of copper oxides (CuO and Cu 2 O) under voltage bias are studied with in situ transmission electron microscopy (TEM). The phases of different materials are confirmed with electron diffraction. In both types of oxides, dynamic conductive path formation and dissolution are observed. The decrease in resistance of CuO film is found to be accompanied

Low temperature (LT) and high pressure oxidized (HPO) Al 2 O 3 is investigated as a gate dielectric for AlInN/GaN MIS-HEMTs. The time and temperature of the oxidation process was optimized for best performance. X-ray photoelectron spectroscopic (XPS) studies confirmed the near complete oxidation of Al to form Al 2 O 3 . MIS-HEMTs with 7 nm thick LT-HPO Al 2 O 3 showed six orders reduction in gate leakage

Failure analysis (FA) becomes increasingly crucial for semiconductor industries with the scale-down and larger integration of devices. In order to overcome the limitation of traditional optical resolution for FA techniques, this article proposed an effective method of precise positioning of circuit defect based on localized probing technique, nano-probing and electron beam absorbed current (EBAC).

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This article investigates the effect of N-type buried layer (NBL) on the holding voltage and failure current of conventional low voltage triggered silicon-controlled rectifier (LVTSCR) and conventional dual directional silicon-controlled rectifier (DDSCR) devices. LVTSCR and DDSCR with N-type buried layer are fabricated on a 0.18- $\mu \text{m}$ Bipolar CMOS DMOS (BCD) technology. In order to verify

This study quantifies the correlations between crack evolution and electrical performance degradation of the Al metallization in insulated gate bipolar transistor (IGBT) modules. The resistance of the Al metallization under different power cycling times was measured by the four-point probe method. The cracks that occur in the Al metallization were investigated by measuring crack geometric parameters

Power devices may become damaged or even fail completely due to over-current caused by external factors such as ac line transients, mechanical overload, misfiring, inverter shoot-through, etc. Some of these incidents can result in a very high current (few times higher than the system’s rated current) flow through the electrical drive system. Electrical machines have the capability to withstand very

Negative bias temperature instability (NBTI) is the major reliability issue which affects many parameters such as threshold voltage, mobility, and leakage current. The threshold voltage of the PMOS transistor increases due to NBTI with stress time, which degrades the circuit performance. In this article, we have proposed a novel reliable data-dependent low power 10T SRAM cell, which is highly stable

The prospects of Terahertz (0.3 THz-5.0 THz) power generation with laterally doped hybrid Graphene/Si (Single-Layer ( $\text{S}_{\mathrm{ L}}\text{G}$ ), Bi-Layer ( $\text{B}_{\mathrm{ L}}\text{G}$ ) and Multi-Layer ( $\text{M}_{\mathrm{ L}}\text{G}$ )) Mixed Tunneling Avalanche Transit Time (GL-h-MITATT) oscillator is explored through an indigenously developed and experimentally verified self-consistent

Although it is the worst degradation mechanism, the effect of channel hot carrier (CHC) stressing on random telegraph signals (RTS) has not been given enough attention in pMOSFETs. We report on the effect of CHC stressing on different RTS trap parameters namely screened scattering coefficient which controls the amount of charge carrier mobility fluctuations due to remote Coulomb scattering by the trap

In this paper, CPI (chip-package interaction) reliability of WLP (wafer level package) was investigated. PBO (Polybenzoxazole)-based RDL (redistribution layer) structure was the primary focus. Firstly, the stress distribution for PBO structures was studied by simulation. Secondly, two types of the chip with different PBO structures completed the accelerating experiments. Based on our investigation

SRAM stability is a major concern in nanometer CMOS technologies. As the most important metrics of SRAM static stability, the static characteristics of SRAM are derived by static characteristic curves (read butterfly curve, standby butterfly curve, read N curve, write N curve and WNM curve). This paper deduces the read butterfly curve transfer function as an example to show the effect of supply voltage

Reliably modeling fatigue induced degradation of metal films requires a consistent mathematical description of the physically relevant damage driving forces. The processes, which trigger deformation, damage and eventually failure, have to be included and combined in a physically meaningful way to obtain a valid model. Therefore, it is essential to consider the material response to applied stress, as

Edge traps in the gate oxide of silicon nanowire MOSFETs have been extracted from tunnel current noise measurement in a gated diode like arrangement. We have found that, low frequency noise in tunnel current results from collective response of the edge traps available within the gate oxide surrounding band-to-band generation (BTBG) region of silicon nanowire, and when the BTBG region is accessed by

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TDMR welcomes Dr. Abhisek Dixit as a new member of the TDMR Editorial Board. Dr. Dixit is an expert on device characterization and modelling of different nanometer technologies, such as bulk Si, PD, and FD-SOI BiCMOS. His experience will be of great help in reviewing and evaluating technical aspects, such as quantum computing hardware, CMOS hot-carrier and radiation effects, pulsed/RF characterization

The IEEE International Integrated Reliability Workshop (IIRW) is a unique event that takes place every year at the beautiful Fallen Leaf Lake, in Tahoe, California. This workshop brings together reliability engineers and researchers from around the world, to exchange ideas over four days in a relaxed, friendly, and informal atmosphere. The workshop focuses on the recent advances in research concerning

You are reading the Editorial of the Special Section of IEEE Transactions on Device and Materials Reliability with a collection of the best papers of the 2019 edition of the IEEE IOLTS, an established IEEE symposium which focuses for exactly one quarter of a century on the challenges and solutions for computing and electronic circuits and systems robust design . Robustness from the IOLTS technical

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The quality of the gate-oxide and Oxide/SiC interfaces is one of the crucial issues in the implementation of silicon carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) in the industrial power electronic applications. The main goal of this work is to investigate the gate-oxide integrity and to understand the basic phenomena involved on 4H-SiC MOSFET by the mean of Capacitance-Voltage

Fast characterization methods are utilized to investigate DC and AC negative bias temperature instability (NBTI) characteristics in pMOSFETs with different TiN capping layer thicknesses ( ${t} _{\mathrm{ TiN}}$ ). The impacts of ${t} _{\mathrm{ TiN}}$ scaling on the threshold voltage shift ( ${\Delta }\text{V}_{\mathrm{ T}}$ ), pre-existing hole traps ( ${\Delta }\text{V}_{\mathrm{ HT}}$ ), generated

Ultra-low-power systems with substantial computing capacity require latches and SRAMs to operate at extremely low supply voltages. However, with aggressive technology scaling, reliability becomes a major challenge due to unavoidable process variations and the presence of multiple noise sources, including intrinsic thermal noise. This paper provides a quantitative measure of reliability by calculating

Ensuring high reliability in modern integrated circuits (ICs) requires the employment of several die screening methodologies. One such technique, commonly referred to as die inking, aims to discard devices that are likely to fail, based on their proximity to known failed devices on the wafer. Die inking is traditionally performed manually by visually inspecting each manufactured wafer and thus it is

In Space applications, the scaling of transistors has made integrated circuits (ICs) more susceptible to soft errors, caused by radiation strikes. When a soft error causes a bit flip in a memory device, this event is referred to as a Single Event Upset (SEU). Since SEU errors degrade system performance and eventually lead to system failure, the design of radiation-resilient memory is substantial. This

A huge shift in classical system integration composed of heterogeneous and homogeneous substances from 2D to 2.5D or even 3D assembly is a promising solution to satisfying the requirements of electronic packages, such as high operating speed, multifunctionality, and low form factor, under the physical limits of nanoscaled transistors and bottlenecks in related fabrication technologies. However, considerable

As the standard complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) generates a leakage current due to ionizing radiation reacting with silicon in a radiological environment, radiation hardening of CMOS devices is being actively investigated. If a radiation-tolerant IC (RTIC) is designed, it is very important to examine the design possibility of an application specific IC (ASIC)

Embedded systems are being aggressively integrated in every aspect of modern life, with uses ranging from personal devices to devices deployed in critical systems, such as autonomous vehicles, aircrafts, and industrial control systems. Embedded systems handle sensitive information, which can be potentially exposed leveraging their poor security posture. In this paper, we present a novel attack vector

In this paper, we show that stress-tests can be potentially used as power-noise viruses in denial-of-service (DoS) attacks by causing voltage emergencies that may lead to data corruptions and system crashes in multi-core processors. This attack targets processors whose operating voltage has been reduced in-the-field for improving energy efficiency. To protect such undervolted processors from this type