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Application of Monte Carlo (MC) simulations in the statistical analysis of LED lumen maintenance is presented in this paper. Lumen maintenance data is acquired using experimental tests accomplished in the electro-optics laboratory of the Mazinoor lighting industry, which is an accredited laboratory by Iranian National Standards organization. The sampling rate and the duration of the experiments are

The low-frequency noise of short channel triple-gate junctionless (TG JL) MOSFET has been investigated in the frequency and time domains before and after hot carrier aging (HCA). The objective of this work is to investigate the interaction between HCA/flicker noise (1/f noise) and random telegraph noise (RTN) of short channel length device (L = 25 nm) exhibiting high density of interface traps. Significant

This work aims at understanding and eliminating thermo-mechanically induced circumferential cracks that form during cooling for a 400 °C annealed copper (Cu) through-glass via (TGV) with a mean outer diameter of $47.5~\mu \text{m}$ , made in Corning HPFS fused silica glass. An exponential dependence was found between Cu metallization thickness and the likelihood for the formation of circumferential

The reverse breakdown characteristics of 4H-SiC Junction Barrier Schottky (JBS) rectifiers adopting the different floating limiting rings (FLRs) termination structures are experimented and analyzed under the repetitive avalanche current stress. The experimental results indicate that the breakdown voltage (BV) shift of the device after the repetitive avalanche current stress is highly dependent on the

In response to the rapid development of wireless communication, enhancement of temperature stability and power durability for surface acoustic wave (SAW) devices is both scientifically and technologically important in the 5G era. This paper discusses the utilization of 5-layer electrode Ti/Cu/Ti/Cu/Ti to the development of high power and low loss temperature-compensated surface acoustic wave (TC-SAW)

This work investigates the impact of gate-oxide stacking on the performance of source-pocket engineered (SPE) GaSb/Si heterojunction (HJ) vertical TFETs (VTFETs) based 8T SRAMs. The 8T SRAMs circuits are designed using the SPE-HJ-VTFETs with three different gate-oxide engineered structures: laterally stacked HfO 2 /Al 2 O 3 gate-oxide, vertically stacked Al 2 O 3 /HfO 2 gate-oxide and only Al 2 O 3

Pulsed Flip-flops (FFs) are popular elements in the design of high-speed microprocessors. Technology scaling has led to a considerable increase in manufacturing process variation and aging phenomena affecting the reliability of these FFs. In this paper, the timing reliability of pulsed FFs is improved using a transistor-level restructuring technique. In this technique, we modify the pull-down network

This paper proposes a new structure named a Side Contact lateral Doping Field Effect Diode (SLFED) to overcome the short channel effects of a regular field effect diode (FED). The fabrication of this new structure is simple that can be fabricated by the standard CMOS process technology, and it offers good electrical characteristics. Furthermore, a comprehensive analysis of FEDs has presented. Our results

The multichip power module is a popular application for large-capacity and high-frequency converters. However, the existence of an asymmetric circuit layout has a significant influence on the current sharing among parallel SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). In this paper, the mechanism of the dynamic current imbalance resulting from the asymmetry of signal terminal confluence

With the technology scaling down, the single event transients produced in the combinational circuit lead to an increasing threat to reliability. In this paper, Dummy Gate Enhanced Charge Sharing (DGECS) technique is proposed to mitigate single event transients, and enhances the pulse quenching of logic cells by increasing the charge sharing between key transistors. Mixed-mode 3-D technology computer

In this paper, investigation of Double Channel (DC) AlGaN/GaN HEMT has been presented using extensive TCAD simulation under the influence of Single Event Transient (SET) effect. Various models used to emulate Single Channel (SC) and DC HEMT in the TCAD are calibrated with the help of previously reported work. In order to present clear insight into the device behaviour, thermal model has also been included

A packaging approach for cost-effective and ultrathin high-power phosphor-based white light-emitting-diode (WLED) emitters with outstanding reliability is presented. By removing the encapsulant in the conventional method, the new approach employs a single silicone-phosphor thin layer instead of multiple phosphor layers in chip-scale package (CSP) WLED for both encapsulations, as well as wavelength

Device reliability predictions of the low-k amorphous dielectric material SiCOH using its negative magnetoresistance (MR) is demonstrated herein. The magnitude of the MR is related to the density of defects at the interface and within the bulk of the dielectric material. Moreover, the mean-free path of carriers in the bulk dielectric material within the conduction band is increased in the presence

This work presents an efficient test technique for detecting resistive short defects in STT-MRAM arrays. The proposed technique is based on monitoring the current mismatch flowing into and out of the cell caused by a weak or strong short defect. This technique is used to propose a low area overhead Design-for-Testability (DFT) circuit to employ in STT-MRAM arrays to distinguish defect-free cells from

The reliability of the integrated circuits (ICs) has become one of the greatest challenges with the increasing complexity of the electromagnetic environment. On this basis, an explicit difference in the damage location is observed in the high-power microwave (HPM) radiated CMOS inverters. The detailed damage mechanism analysis is performed. The analysis shows that the overcurrent-dominant failure and

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The effect of proton irradiation on the electrical properties of AlGaN/GaN high electron mobility transistors (HEMTs) with hydrogen treatment is studied. Hydrogen treatment makes the damage caused by proton irradiation worse. The AlGaN/GaN HEMTs with hydrogen treatment at $2.0 \times 10^{14}\text{p}$ /cm 2 3-MeV proton irradiation fluence experience a decrease by 37.3% in the saturation current, a

On-chip electrostatic discharge (ESD) protection is becoming more challenging for integrated circuits (ICs) made in advanced technology nodes. The ESD-induced design overhead, including ESD parasitic effects and layout area, inherent to the traditional in-Silicon PN-junction-based ESD protection devices, rapidly becomes unbearable to high-performance and complex ICs. A disruptive above-Si mechanical

Phase-change memory (PCM) as emerging non-volatile memory has attracted more attention and considered as the promising replacement of the main memory. PCM has shown good scalability and high storage density, but data storage reliability has become a challenge and concern. When data are written into PCM cells by a phase transition between amorphous and crystalline, the resistance of each state drifts

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For years, the IEEE International Integrated Reliability Workshop (IIRW) has been held at the edge of Fallen Leaf Lake in California, just south of Lake Tahoe. Typically, the conference is a four-day event comprised of lively discussions, beautiful vistas, and is an unparalleled informal event that is a fertile ground for the exchange of ideas and professional networking. For 2020 however, the conference

We present detailed ON-state gate current characterization of Schottky gate p-GaN capped AlGaN/GaN high-electron-mobility transistors (HEMTs) on two distinct gate processes. The threshold voltage is monitored from $10~\mathrm {\mu }\text{s}$ up to 100 s under positive gate bias stress and during recovery. The threshold voltage stability is affected by the balance between hole and electron current in

The impact of the interface layer on charge trapping and polarization switching at multiple temperatures is investigated. At high temperatures, a ferroelectric field effect transistor with a metal-ferroelectric-insulator-semiconductor (MFIS) gate-stack shows conventional electron-trapping dominated PBTI (i.e., $\Delta \text{V}_{\mathrm{ t}} > 0$ ), whereas at room temperature, negative threshold voltage

Resistive Random access memory (RRAM) devices together with the material implication (IMPLY) logic are a promising computing scheme for realizing energy efficient reconfigurable computing hardware for edge computing applications. This approach has been recently shown to enable the in-memory implementation of Binarized Neural Networks. However, an accurate analysis of the performance achieved on a real

This work reports on charging damage induced by gate antennae in high- $\kappa $ (HK) Replacement Metal Gate (RMG) technology for the HK-first and HK-last integration flows, comparing plate and comb layouts. For the HK-first devices, a significant degradation of the Gate Induced Drain Leakage (GIDL) occurs for both types of antennae, which is analyzed in terms of activation energy and corresponding

To improve MOS transistors operating characteristics, such as the switching speed and power consumption, the dimensions of integrated devices are continuously decreased, amongst other advances. One of the main drawbacks of geometry scaling is the increased variability of the threshold voltage between nominally identical devices. The origin for this lies in defects located inside the oxide and at the

As Fin Field Effect Transistor (FinFET) scales aggressively, even a single point defect becomes a source of performance variability. The point defect is inevitably introduced not only by process damage such as epitaxial growth and ion implantation but also by cosmic rays. Technology computer-aided design (TCAD) is able to simulate the characteristics of the device with the defect. In this work, a machine

Electromigration (EM) has emerged as a major reliability concern for interconnects in advanced technology nodes. Most of the existing EM analysis works focus on the power lines. There exists a limited amount of work which analyzes EM failures in the signal lines. However, various emerging spintronic-based memory technologies such as the Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM)

Modern storage devices such as hard disk drives (HDDs) and solid state drives (SSDs) have reached capacities beyond 18TB. Failure of such devices requires data recovery from parities. Given the large capacities, the recovery process may take up to a few days depending on the bandwidth and the erasure coding scheme implemented. During the recovery, the system is vulnerable to data loss if additional

Impact of bias-temperature stress (BTS) has been assessed in a three-terminal vertical current driver fabricated by room temperature processing of IGZO/Ni/IGZO stack on a p-silicon substrate. Under normal working condition and at a low voltage, the driver exhibits 10 4 ON-OFF current ratio with remarkable 46 mV/decade subthreshold slope, because of 0.89 eV Schottky barrier presented by the Ni/IGZO

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In this work, three MISHEMT devices with different electric-field-dispersion layer (EDL) behave the same pristine electrical properties. EDL, which is low dielectric constant (low-k), can effectively disperse electric field, which enhances breakdown voltage and improves reliability in MISHEMT. In a comparison of devices with high-k and low-k EDL, the on-state current ( $\text{I}_{\mathrm{ on}}$ ) of

The lifetime of light-emitting diodes (LEDs) is highly dependent on usage conditions such as operating temperature and drive current. It is costly and impractical to test the LEDs on every usage condition. Previous studies used the Arrhenius equation and Black’s model to investigate the relationship of operating temperature, drive current and lumen maintenance life. However, they are found to be less

This paper presents experimental and numerical analysis of a buried P-pillar (BP) lateral double-diffused metal-oxide semiconductor (LDMOS) fabricated on a silicon-on-insulator (SOI) substrate. The experimental results indicate that the specific on-resistance ( $R_{ {on,sp}}$ ) of the SOI BP-LDMOS is 9.5 $\text{m}\Omega \cdot {\mathrm{ cm}}^{{2}}$ with a breakdown voltage (BV) of 229 V, which corresponds

Multilevel finite element analysis (FEA) was used to study the effects of wiring density and solder pillar structure on chip-package interaction (CPI) for advanced Cu/low k mixed-signal chips. The mixed signal chip has analog and digital wiring designs with different metal densities, incorporating extreme low-k (ELK), low-k (LK) and oxide dielectrics in 10 wiring layers. The results are compared with

As the operating conditions are getting harsher, the failure analysis of Phase Change Memory (PCM) are getting more and more important. In this work, some nonvolatile Phase Change Memory (PCM) devices based on Ge 2 Sb 2 Te 5 are found RESET stuck failure during the pulsed mode switching. The causes, which result in the early failure of the PCM, have been studied by combining transmission electron microscopy

A compact 3D thermal model is developed for the quick and accurate thermal characterization of self-heating in Back-End-of-Line (BEoL) interconnect network for reliability assessment. The model offers a more accurate thermal tool compared to the currently used conservative 2D reduced models. Both 2D and 3D reduced models are developed and verified against numerical simulations of different configurations

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Popcorning is a well-known effect in plastic encapsulated microcircuits (PEM) and it occurs in chip tantalum capacitors. The sensitivity of components to the presence of moisture during soldering is characterized by the moisture sensitivity level (MSL); however, contrary to PEMs, there is no standard procedure for establishing MSL for tantalum capacitors. The effect of absorbed moisture on soldering

Static Random Access Memory (SRAM) is primarily used as a memory storage element, which is susceptible to radiation-induced Single Event Upsets (SEUs). Hence, a robust SRAM bit-cell design is primarily a difficult task to address the space radiation environment. Furthermore, as the transistor’s size moves into nanometer regimes, a new challenge like Single Event Multiple Effects (SEME’s) evolved in

In this article, we present an extensive investigation of the time-dependent drain breakdown occurring in GaN-on-Si power HEMTs with p-GaN gate under long-term OFF-state stress. In particular, the time-dependent breakdown induced by high-temperature-reverse-bias stress is investigated as a function of different process and structural variations. Main results demonstrate that, by varying the gate-to-drain

In a spacecraft, flip-flops take part in holding operational configuration for long durations. Single event transients (SETs) at control inputs of such flip-flops can culminate in single event upsets (SEUs). An SEU may cause loss of one or more mission objectives or service disruption or life reduction of the spacecraft. Many radiation-hardened-by-design (RHBD) circuits are presented in the literature

This work presents a novel gated- diode SCR-incorporated BJT (SIB) structure for ESD protection purpose. A gated diode built in the SIB structure modulates reverse-biased P + / N-well diode for better junction breakdown control. This device could achieve high TLP second breakdown current /ESD threshold close to that of an SCR, very high holding voltage, and reduced trigger voltage, as well as excellent