Modern technologies and devices ranging from smartphones, computers, cloud computing, industrial automation, automobiles, to the Internet of Things are enabled by integrated circuits (ICs) and their associated packages. The ICs have evolved from the early small-scale integration (SSI) to the later more complex very-large-scale integration (VLSI) and the subsequent ultra-large-scale integration (ULSI)

The interaction between the continuous microstructure evolution during thermal cycling and the long-term reliability of wafer-level chip-scale packages (WLCSPs) with Sn–1.0Ag–0.5Cu (wt%) (SAC105), Sn–3.0Ag–0.5Cu (wt%) (SAC305), and Sn–3.9Ag–0.6Cu (wt%) (SAC396) solder ball interconnects were investigated. Three different body-sized WLCSP with three different solder alloys on three different board thickness

Many connections exist in complex electronic equipment, which leads to a long duration of intermittent fault test and difficulty in achieving comprehensive coverage of intermittent fault. The intermittent fault mechanism and the multichannel intermittent fault parameter parallel capture method are investigated. A smaller module covers multiple intermittent connection faults in electronics and prevents

A rapid method based on activation energy values for the lifetime assessment of PP films used as dielectrics for capacitors is proposed. The activation energy is determined from a nonisothermal measurement made by differential scanning calorimetry and an aging test at a single elevated temperature. The use of the onset temperature of the exothermal peak is proposed to evaluate the activation energy

Stud bumping using a traditional wire bonding process followed by the severing of the wire material from the ball bond has been widely applied in flip chip packages. Traditionally, Au stud bumps were employed because of the physical properties of gold, but the mediocre reliability of Au with Al pads and the cost of gold make this material unfavorable for industrial needs. Copper stud bumps were also

In order to control the impact behavior of the microprobe test process in microelectronics final test, based on the rapid response and intelligent controllability of magnetorheological (MR) fluid, a novel micro-MR flexible loader was designed to be loaded into the microprobe test system. The results show that the new system can effectively achieve smooth loading, and over-loading could be avoided by

With the advantages of high-power density, easy series connection, and failure short-circuit mode, the press pack packaging technology has been widely adapted in insulated gate bipolar transistors (IGBTs) which are applied for high-voltage and high-power density power apparatuses. Accurate modeling of temperature field in the press pack IGBTs (PP IGBTs) is vitally significant with the increasing power

This article focuses on the electrical performance of a new Ethernet contact with four differential pairs called “Octomax.” The eight pins of the contact are inserted in a section of 17 mm 2 . Such a high-speed interconnect solution is specially developed to operate at 10 Gbits/s in harsh environments for military and aerospace applications. The theoretical study up to 1 GHz enables quantifying the

This article presents the improved formulations for the latency insertion method (LIM) for diodes and MOSFETs utilizing the voltage-in-current framework. LIM is a fast circuit simulation algorithm, which computes the solutions to the voltages and currents in a circuit in a leapfrog manner, instead of a simultaneous matrix solution typically performed in the modified nodal analysis formalism. This allows

The conventional finite-difference time-domain (FDTD) method is efficient for microwave frequencies, but requires a large number of time steps for low frequencies. In this work, a hybrid Crank–Nicolson (CN) FDTD-SPICE method is applied to field-circuit analyses in low- frequency wideband problems. The unconditionally stable CN-FDTD method is used to give a rapid full wave solution by overcoming the

Bonding wires are widely used in microwave circuits and chip packaging. The exposure to harsh environments may lead to connection failure in these wires. In this article, the impact of such failures on signal transmission was studied using model analysis and experimental testing. The effects of gold bonding wire failure on both the dc and high frequency characteristics were analyzed. Signal reflection

Modern wireless devices operate on multiple frequency bands and, thus, can benefit from frequency-reconfigurable radio frequency (RF) components, especially filters that are typically larger in size and are required for every frequency band. In addition, many applications, such as wearable electronics, desire stable performance from the devices when they are bent or flexed. However, most of the reconfigurable

In manufacturing industries, yield is the essential quality for any mass production process. Particularly, in advanced and complex semiconductor processes, the yield requirements are becoming more stringent. Process capability index $C_{pk} $ has been widely employed to measure yield for processes with a very low fraction defective. However, unobserved slight and temporary process variations due to

A 650-V and 10-A silicon carbide (SiC) stacked cascode assembly has been proposed and demonstrated, in which a low-voltage Si-MOSFET (LV Si-MOSFET) is stacked on a high-voltage SiC buried gate static induction transistor (HV SiC-BGSIT). This is achieved by mounting Al bumps on the source pad of the HV SiC-BGSIT die and inserting a stacked Ag paste/epoxy layer between the HV SiC-BGSIT die and LV Si-MOSFET

In this letter, we propose a novel signaling figure of merit (s-FoM) for comparison of signaling schemes across different packaging technologies. It considers all the essential metrics that affect system performance and efficiency and combines them in a simple, easily quantifiable manner. These include energy per bit, data-bandwidth per unit shoreline, latency, length of the link, and real-estate overhead

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Modern technologies and devices ranging from smartphones, computers, cloud computing, industrial automation, and automobiles to the Internet of Things are enabled by integrated circuits (ICs) and their associated packages. The ICs have evolved from the early small-scale integration (SSI) to the later more complex very-large-scale integration (VLSI) and the subsequent ultra-large-scale integration (ULSI)

The multilayer structure of 3-D network-on-chips (3-D NoC) leads to the unequal thermal conductance between different layers and, as a result, an unbalanced thermal distribution in the chip. This issue leads to the low reliability and performance degradation of 3-D NoCs. To ensure thermal safety, 3-D NoCs require effective cooling methods. Several thermal-aware routing algorithms have been proposed

A polylithic integration technology called heterogeneous interconnect stitching technology (HIST) is explored in this article. HIST provides both 2.5-D and 3-D integration capabilities enabled by multi-height and fine-pitch compressible microinterconnects (CMIs). The ANSYS Workbench simulator is used to optimize and simulate the multi-height and fine-pitch CMIs. A testbed is fabricated and assembled

With the development of high-power light-emitting diodes (LEDs), the heat flux density of devices has continued to increase, which, in turn, requires the development of increasingly effective methods of heat dissipation to control the working temperature of LEDs. Due to their impressive performance in solid refrigeration and energy harvesting, thermoelectric devices such as thermoelectric coolers (TECs)

In order to improve the optical and electrical consistency in lighting and display, light emitting diode (LED) dies should be sorted and aligned precisely one by one. As per given current production process practices, the sorting efficiency is required to be more than 36 thousand units per hour (KUPH), while the alignment deviation should not exceed 1 mil (25.4 $\mu \text{m}$ ) and all dies’ angle

Package-integrated and ultrathin power dividers with footprint smaller than unit $\lambda ~_{0}~^{\mathrm{ 2}}$ at the operating frequency of 28-GHz 5G new radio (NR) n257 and n258 bands are presented for the first time for small-cell applications. These power dividers are also configured as antenna arrays using endfire Yagi–Uda antenna elements. Utilizing minimal matching techniques, two-, three-

Molding compounds (MCs) are widely used as an encapsulation material for integrated circuits; however, traditional MCs are susceptible to moisture and charge spreading over time. The increase in dissipation factor due to the increase of parasitic electrical conductivity ( $\sigma$ ) and the decrease in dielectric strength $(E_{\mathrm {MC}}^{\mathrm {Crit}})$ restrict their applications. Thus, a fundamental

We report laser-based fault isolation methodologies for the localization of open and short failures in $1 \times 5\,\,\mu \text{m}$ via-last through-silicon via (TSV) structures for 3-D system-on-chip (SoC) integration. Due to the photosensitive TSV interconnect capacitance, observation of the photocapacitance response enables nondestructive localization of metallization ruptures. A light-induced capacitance

Downscaling of package wiring has been the singular focus to achieve higher logic-memory interconnect density to meet next-generation needs for high-bandwidth computing. This article presents, for the first time, a systematic modeling and experimental study of sub-5- $\mu \text{m}$ -diameter microvia reliability. Geometry design considerations and build-up dielectric material properties in evaluating

This article aims to propose a predictive abnormality detection model in the stencil printing process (SPP). The SPP is the main contributor to surface mounting technology (SMT) soldering defects. The prediction of abnormal conditions is necessary to enhance the first-pass yield and reduce the reworking costs of the printed circuit board (PCB) assembly line. In this research, a novel multiphase intelligent

In this work, we developed a process to release the optical waveguides locally from the back side of a silicon-on-insulator wafer to enable a connection and an interaction between organic materials and photonic devices. The release procedure is realized by a local back-side etch followed by a chemical wet etch. Furthermore, certain process steps for a controlled removal of the buried oxide below the

The intermittent fault (IF) in electrical systems is considered to be one of the most challenging problems to tackle. At present, there remains a lack of understanding as to the mechanism of IF. Therefore, this letter is focused on the characteristics of IF in electrical connectors under vibration environment. Based on the mechanical structure of a certain kind of electrical connector, a dynamic model

This letter provides an overview of the metal-embedded chiplet assembly for microwave integrated circuits (MECAMICs) technology. MECAMIC is a 2.5-D wafer-level packaging approach that provides seamless heterogeneous integration capabilities of compound semiconductor transistors (e.g., GaN HEMTs) with passive components and interconnects using a backside metal embedding process. The chiplets are embedded

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Organic materials have been widely used in photovoltaic solar applications because of their flexibility and low cost. Poly(3,4-ethylenedioxythiophene) (PEDOT) has been known to have good mechanical stability under stretching and bending and also has good electrical and optical properties. Unlike inorganic materials, PEDOT can withstand high strains. In flexible solar cells, modules are usually exposed

Solid diffusion bonding of the copper–zinc system is preliminarily investigated as a possible bonding solution for power modules. This article proposed a method of bonding Zn foil on substrate-plated Ag to obtain the solder joints. The formation and transformation of intermetallic compounds (IMCs) in Cu–Zn and Ag–Zn joints were investigated. The results showed that the AgZn 3 phase was compressed and

In this article, we cover the fundamentals of neural networks and Bayesian learning with a focus on signal and power integrity problems arising in packaging. Rather than only focus on mathematical formulations, we explain the important concepts and the intuition behind them, thereby demystifying the use of machine learning for these problems. We also share some of the recent developments in this area

With the advantage of high surface-roughness tolerance, the pillar–concave Cu–Cu direct bonding without chemical-mechanical planarization (CMP) is investigated in detail, including the mechanism of thermal compensation, analysis of roughness, bonding strength, and bonding reliability. With the special design of Cu bond structure, excellent bonding results can be achieved under low thermal budget (150

Optimization of liquid-cooled heatsinks (cold plates) is of critical importance due to their widespread application in high-performance electronic packages consisting of heterogeneous integrated systems, field programmable gate arrays (FPGAs), and on-chip hotspots. In this study, the thermo-hydraulic performance of a commercial microchannel impingement cold plate is analyzed in detail. Impingement

The basic function of wire connection systems is to assure a low resistance and a stable long-term electromechanical connection. The quality of this connection is determined by the quality of a large number of electromechanical interstrand and strand/connector contacts. The aim of this study is to analyze the parameters that influence the performance of wire connection systems with a new measurement

This article presents a new approach to construct parameterized reduced-order models for nonlinear circuits. The reduced model is obtained such that it matches the variations in the DC operating point of the original full circuit in response to variations in several of its key design parameters. The new approach leverages, through the use of circuit moments with respect to the design parameters, the

This article presents the electrical circuit model of signal–ground through-silicon vias (TSVs) in a silicon microfluidic pin-fin heat sink in which the pin-fins are surrounded by deionized water. Such TSVs are asymmetric vertically because the TSVs are partially embedded in cylindrical pin-fins as well as in a rectangular silicon base. In this article, we propose a circuit model that segregates the

Contact bounce is a common phenomenon in the closing process of the electromagnetic relay under capacitive loads. The investigations on the contact characteristics are mainly conducted by experimental methods. However, the experimental method is extremely complicated and time-consuming in structural design, and it cannot clearly reveal the mechanism of contact bounce. Therefore, a new theoretical model

Crosstalk noise suppression is a crux in the high-speed integrated circuit design, which requires weak-coupling between transmission lines (TLs) over a wide band. To overcome the difficulty, this article presents a novel method to suppress the broadband crosstalk noise between a single TL and the differential pair based on spoof surface plasmon polaritons (SPPs). Due to the subwavelength feature of

Modeling of multiport data characterizing high-speed modules, such as packages, vias, and complex multiconductor interconnects is becoming increasingly important in signal and power integrity applications. Vector fitting (VF) algorithm has been widely used by designers for macromodeling and system identification from such multiport tabulated data. Since VF and strategies based on it require many iterations

Making photonic sintering of metal nanoparticles, a viable nanomanufacturing process for printed electronics requires an understanding of all of the parameters that lead to variability in the photonic sintering process. This article examines the effects of variability in the exact location of nanoparticles within a packing on the thermo-optical properties of the assemblies. Multiple discrete-element

In this work, the effects of extreme thermal fluctuations on the reliability of solder joints were investigated. For this purpose, the solder joints in insulated-gate bipolar transistor (IGBT) devices were exposed to the conventional thermal cycling and the thermal shock cycling (TSC) tests. The finite element method (FEM) simulation results indicated that the accumulated creep energy in solder layer

The void in the solder layer is one of the most important aging forms of the insulated-gate bipolar transistor (IGBT) module. In this article, the influence mechanism of different void fractions on the thermal conductivity and specific heat capacity of the solder layer is studied. An improved Cauer model considering the void damage of the solder layer is established, and its model parameter extraction

This study, to the best of authors’ knowledge, is the first to investigate the feasibility of using picosecond UV laser ablation to fabricate ultrasmall microvias scaled down to 3 $\mu \text{m}$ and less with a pitch of 8 $\mu \text{m}$ in a 5- $\mu \text{m}$ Ajinomoto buildup film (ABF). The state-of-the-art microvias are 20 $\mu \text{m}$ in diameter by a nanosecond UV laser and 5 $\mu \text{m}$

Typical die shift is beyond several tens micrometers or more, which is a serious problem on advanced fan-out wafer-level packaging (FOWLP), to give inevitable misalignment errors in the subsequent photolithography processes for fine-pitch redistributed wiring layer (RDL) formation. In particular, this problem is expected to grow all the more serious in chiplets and tiny dies less than 1 mm in a side

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A low-loss fan-out wafer-level package (FOWLP) has been proposed for millimeter-wave application. To ensure the radio frequency (RF) signal transition in a ground–signal–ground (GSG) configuration, the signal structure in the redistribution layer (RDL) is tightly surrounded by its ground. Over a wideband, the proposed RDL structure results in a low loss and a good match at the RF port. Moreover, an

Flexible implantable bioelectrodes have the potential to advance neural sensing and muscle stimulation, especially in peripheral nerve injuries. In such cases, the application of electrical stimulation to muscles prevents muscular atrophy and helps to bridge the gap between the injured nerve and the corresponding muscle. This article investigates the fabrication and characterization of a novel, cost-effective

During usage, printed electronic components are often stretched, bent, folded, and/or twisted to conform to underlying structure. In this article, tests have been developed for characterizing the mechanical and high-frequency electrical behavior of inkjet-printed patch antennas on flexible polyethylene terephthalate (PET) substrates under uniaxial and biaxial bending. A patch antenna is designed to

Better mechanical, thermal properties and longer lifetimes are needed for the die attach layer in high-power electronic packaging. As traditional Sn–Ag–Cu (SAC) solders have many limitations, the sintered nanosilver materials are becoming one of the substitutes for high-power electronic packaging. However, the high performance of sintered nanosilver materials is only achieved when its fine sintering

In this study, a very high-throughput and low-cost packaging method for fabricating the fan-in chip-scale package is presented. Emphasis is placed on the utilization of the existing printed circuit board (PCB) panel carriers and the corresponding PCB equipment for making the redistribution-layers (RDLs), vias, under bump metallurgy (UBM), contact pads, solder mask, and surface finishing of the package

In this article, the fan-out chip-last panel-level packaging for heterogeneous integration is investigated. Emphasis is placed on the design, materials, process, fabrication, and simulation of thermomechanical reliability of a heterogeneous integration of one large chip (10 mm $\times 10$ mm) and two small chips (7 mm $\times 5$ mm) by a fan-out method with a redistribution-layer (RDL)-first substrate

Hybrid dc switches have better performance with regard to energy conservation and less arc erosion than conventional semiconductor switches and mechanical switches. A novel hybrid dc switch based on a SiC-MOSFET is developed, and it accomplishes arc-less commutation if the current is below a threshold value, which is mainly determined by the boiling voltage of its contact material. However, as it is