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In a time where the demands for electronic systems and components are rising in an unprecedented fashion, the complexity for designing these components and systems is increasing at a similar pace. From wearable and handheld devices to autonomous vehicles to data centers and supercomputers, the growing amount of integration and the demand for more efficient access to ever-increasing data are pushing

A numerically robust and computationally efficient approach for evaluating a planar layered substrate’s static Green’s function is developed based on the adaptive form of the spectral differential equation approximation method. The method uses a $p$ th-order finite element method (FEM) solution of the 1-D ordinary differential equation governing the spectrum of the layered-media Green’s function with

This article proposes a black-box behavioral modeling framework for analog circuit blocks (CBs) operating under small-signal conditions around nonstationary operating points. Such variations may be induced either by changes in the loading conditions or by event-driven updates of the operating point for system performance optimization, e.g., to reduce power consumption. An extension of existing data-driven

With a short product cycle as we see today, fast and accurate modeling methods are becoming crucial for the development of new generation of electronics devices. Furthermore, increased complexity in circuitry and integration compounds design iteration and the associated, high-dimensional sensitivity analysis and performance optimization studies. Therefore, black-box surrogate models replacing the actual

The ever-increasing demand for higher bandwidth and lower loss makes the predictability of high-speed interconnect performance increasingly challenging. Validating models against measurements of manufactured test structures requires not only accurate methodology but also understanding of the uncertainty impact. S-parameter measurements, characterization of materials, manufacturing processes, and models

Modern high-performance server microprocessors need to integrate multiple intellectual property (IP) blocks in a single chip to achieve higher performance. Due to the diverse supply voltage requirements of these IP blocks, their supply voltages are generated locally on the chip using fully integrated voltage regulators (FIVRs). FIVR is designed using on-chip power bridges, bridge drivers, control circuits

This article presents a fully automated algorithm for the extraction of parameterized macromodels from frequency responses. The reference framework is based on a frequency-domain rational approximation combined with a parameter-space expansion into Gaussian radial basis functions (RBFs). An iterative least-squares fitting with positivity constraints is used to optimize model coefficients, with a guarantee

System-in-foil technology continues to realize relevance in industry and research. In this article, a digital process chain for the fabrication of bend-sensitive sensor structures on a flexible polyimide foil is described. This means that none of the steps in this process chain requires the manufacturing of a structured mask or cliché. Therefore, an arbitrary layout can be manufactured and easily be

The bond wires failure is one of the most common failure modes of the insulated gate bipolar transistor (IGBT) module, which will cause an increase in the overall ON-state voltage drop $V_{\mathrm {CE}}$ , and it is generally believed to not affect the junction-to-case thermal resistance $R_{\mathrm {th}jc}$ . The measured $V_{\mathrm {CE}}$ mainly consists of two parts: the voltage drop of the IGBT

Machine learning (ML) is widely used for building data-driven models that are highly useful for optimization. In this study, a finite element model-based adaptive ML method is presented for chip package reliability prediction and design optimization. This ML method employs a validated multi-scale finite element model for training data generation. An adaptive sampling scheme is developed to optimize

This article presents a novel alternative for measuring the heat power generated by microelectronic devices during their designing stages. The proposed system is comprised of an uncommon geometry and a signal-processing measuring strategy based on the calorimetric principle and natural convection. The calorimeter is nonconventional compared to others proposed in the literature because it does not require

Switching performance of a low-voltage switching device (LVSD) is determined by limiting current and stopping re-ignition. This is strongly influenced by how the arc moves inside the LVSD quenching chamber during the switching process. Improved switching performance is achieved when the arc quickly enters and stays inside the splitter plates of the LVSD, with the arc attached to the surface of the

Heat dissipation of the fan-out (FO) package is a primary concern in advanced electronic packaging. It is a challenge to characterize the thermal performance using the actual geometry of the FO package due to the complex structure and time-consuming calculations. A simplified FO model was constructed based on the equivalent material principle and the mathematical FO model was validated by using the

The reliability of electronics systems primarily depends on the temperature of the electronics components. The development of cost-effective thermal management solutions to cater to the cooling of next-generation electronics systems is the need of the hour. The extended surface is the most reliable, convenient, and cost-effective heat transfer technology to remove the heat generated by the electronics

This article is focused on the thermal design and three-dimensional (3-D) package optimization of planar magnetic components (PMCs), including transformers and inductors for application in an electric vehicle composite boost dc–dc converter. Each PMC comprises electrical windings in printed circuit board (PCB) form in combination with a ferrite core. Multiple features of each PMC package are thermally

Temperature sensitive electrical parameter (TSEP) approaches are widely employed in the junction temperature ( $T_{j}$ ) detection and prediction of power devices, especially the switching parameter. In this article, the voltage-rise time and its loss during the turn-off process are used as the TSEP index for the detection of junction temperature because of the coupling relationship with the maximum

This article proposes a methodology for the fast translation of ideal lumped-element values to the form of a 3-D physical layout using low-temperature cofired ceramic (LTCC) dielectric. It is explained how this approach is implemented without requiring complex formulas and uses a simulation-based process which leads to consume less optimization/tuning processing time. The proposed methodology is applied

This article introduces a novel method of laser ablation patterning-based additive manufacturing (AM) to develop a broadband planar antenna for sub-6 GHz wireless communications applications. The presented technique consists of fused deposition modeling (FDM) and the laser ablation cutting-based metal patterning. The metal layer is transferred to a thermoplastic-based ABS substrate without any postprocessing

In the above article [1] , Figs. 22 and 24 were mistakenly reproduced in Figs. 25 and 21 , respectively. The correct versions of Figs. 21 and 25 are provided here.

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The outpouring of emotion and appreciation for Prof. Avram (Avi) Bar-Cohen from his students and colleagues in the academic, industrial, and government communities in Heat Transfer and Electronics Packaging is a testament to the truly profound impact that he had on our professional and personal lives. Awards are being renamed in his honor, tributes are pouring in [1] , special issues of the IEEE Transactions

Beta-gallium oxide ( $\beta $ -Ga 2 O 3 ) has attracted considerable attention for power devices due to its superior properties and the availability of device-quality native substrates compared to gallium nitride (GaN) technologies. In particular, devices such as the current aperture vertical electron transistor (CAVET) have a higher breakdown voltage compared to lateral transistors made from $\beta

GaN radio frequency (RF) power amplifiers offer many benefits including high power density, reduced device footprint, high operating voltage, and excellent gain and power-added efficiency. Accordingly, these parts are enabling next-generation technologies such as fifth-generation (5G) base transceiver stations and defense/aerospace applications such as high-performance radar and communication systems

An inverter or converter achieves the desired dc–ac or dc–dc conversion as required by electric and hybrid electric vehicles. This conversion is typically performed using semiconductor switches such as Insulated Gate Bipolar Transistors (IGBTs) modules consisting of transistors and diodes. Multiple transistors-diode pairs are integrated under a common copper base plate (also referred to as case). As

Under a given set of boundary conditions (BCs), the thermal performance of an electronic system is generally evaluated based on its steady-state response to constant power loads and thermal BCs that are time-averaged values of the actual transient or cyclic loads and BCs. Such analysis may produce accurate results if the time dependence of the power cycles and thermal BCs is small. Ideally, transient

The electromagnetic interference (EMI) problems are crucial for system-in-package (SiP) due to the high demand of miniaturization and dense integration. Shielding methods are generally employed to protect SiP from EMI, through assessing the key performance index, i.e., shielding effectiveness (SE). In this article, the SE of a SiP is evaluated by using near-field scanning method. The SEs derived by

In order to understand high-G shock reliability of the 3-D integrated structure microsystem (3-D-ISM), it is studied by the finite element method (FEM). First, a numerical model of the 3-D-ISM is established for simulation. Then, appropriate elements are used to discretize the geometry, and certain initial and boundary conditions are enforced. Acceleration up to 20000 G is applied to the high-G shock

In the present investigation, a numerically driven direct and inverse study is conducted for the simultaneous prediction of the internal heat generation, electric field, and magnetic field strengths in porous pin fins from the surface temperature profile in electronic cooling applications. Consideration under imposed electrical and magnetic fields along with all modes of heat transport is given. Initially

Recently, the circuit under pad (CUP) designs are getting very popular because they could save lots of silicon especially for high-density and high-complexity applications. Polysilicon is a material widely used in many electronic device components. When such devices are placed underneath the bond pads, it is highly expected not to show any change in the electrical behavior due to any kind of thermo-mechanical

The thermoelectric effect forms the basis of Peltier cooling that has attracted interest for solid-state refrigeration for more than a century. The dearth of materials level efficiency in converting between heat and electricity has limited widespread applications. With renewed focus on energy technologies in the past three decades, the thermoelectric effect has been intensely explored in new materials

Fast and accurate thermal analysis is critical in designing power electronics converters through virtual prototyping to achieve high power density, efficiency, etc. Virtual prototyping can save cost and time in comparison to hardware prototyping and experimental test and can lead to an overall optimized design. For removing the heat in power converters effectively, forced convection, such as air cooling

Microstrip ultra-wide band (UWB) delay lines consisting of a novel periodically loaded transmission line (PLTL) are presented, along with discontinuous structured guard lines (DSGLs). The distinctive advantage of the proposed approach is that the far-end crosstalk (FEXT) between the adjacent lines is effectively suppressed comparing to the conventional circuits. Afterward, the crosstalk of connected

The panel-level redistribution-layer (RDL)-first fan-out packaging for hybrid substrate is studied. Emphasis is placed on the process, materials, design, and fabrication of: 1) heterogeneous integration of one large chip and one small chip with 50- $\mu \text{m}$ pitch (minimum); 2) fine metal linewidth and spacing RDL-first substrate on a temporary panel carrier; 3) ordinary build-up package substrate

Some packaging technologies of electronic devices introduce compressive biaxial stress and variable vertical stress. In unipolar MOS devices, stress variations typically only linearly affect drain current via carrier mobility. Collector currents of bipolar devices are additionally affected by variations in intrinsic carrier concentration. This leads to increased variability of key device parameters

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The rapid growth of the advanced consumer 5G wireless mobile phones has propelled the demands of fabricating surface acoustic wave (SAW) filters with smaller size and high performance. Three-dimension wafer-level package (3-D WLP) for SAW filter is a promising solution to replace conventional surface mounted technology and chip-scale packaging. In this article, a new WLP for SAW filter with a size

Hermetic sealing microelectronic devices in package become more and more of a challenge for manufacturers due to the complexity of thermal management, getter integration, and material selection and interactions. Such complexity drives the original equipment manufacturer (OEM) to deliver the equipment and technology to meet manufacturers’ requirements. This study has successfully demonstrated that a

Accurate junction temperature measurement is of great significance for the reliability assessment of power insulated-gate bipolar transistor (IGBT) devices. The $V_{\mathrm {CE}}(T)$ method is the most widely used junction temperature measurement method and is recommended by various test standards, the first step of which is the $K$ factor calibration (i.e., calibration). As a new type of package structure

Solder interconnects are essential to the reliability of electronic devices. The addition of alloying elements was reported to provide beneficial effects to the microstructure and mechanical reliability of lead-free solder alloys. In this work, the effects of Sb addition on the mechanical behavior of SAC305 solder alloy were investigated. Based on differential thermal analysis, it was observed that

Metal curving or metal denting is usually an unwanted phenomenon in the printed circuit board (PCB) process. However, curved metal could provide some benefits to enhance performance of radio frequency components. In this article, an approach is proposed to develop a double-curved metal (DCM) in a multilayer PCB process by allocating a metal upon an air cavity and then laminating with buffer layers

Due to the increasing throughput of high-performance integrated circuits, the power consumption of recent high-performance computing systems has grown significantly, leading to greater on-chip current demand. The large current flowing within the power delivery system produces challenging issues, such as electromigration, low power efficiency, and thermal hot spots. To reduce on-chip current demand

A cost-effective ball grid array (BGA) packaged surface-mount off-center-fed dipole antenna element and its array are proposed for 5G millimeter-wave new radio (NR) applications. The proposed antenna element exhibits a compact size of $0.61 \,\,\lambda _{0} \times 0.61\,\,\lambda _{0} \times 0.16\,\,\lambda _{0}$ ( $\lambda _{0}$ is the wavelength in free space at the center operating frequency) and

A novel and compact millimeter-wave (mm-Wave) spatial power combiner is developed integrating a silicon-based integrated circuit (IC) in a metal waveguide (WG). As an initial step toward integrating a silicon-based active IC in a WG, a passive back-to-back (B2B) transition incorporating a four-way spatial power splitter and combiner is realized at $E$ -band (71–86 GHz). In contrast to existing solutions

In this article, we modeled, analyzed, and evaluated a large-scale memristor crossbar array in a neuromorphic system for a deep neural network (DNN) considering signal integrity (SI). Since hardware-based DNN using a memristor crossbar array operates in an analog way, it has serious reliability problems caused by interconnects, driver, and nonlinear memory cells. The interconnects including an on-chip

For system manufacturers, packaging of the ball grid array (BGA) of wireless communication modules can be performed via solder paste printing. As reballing can be conducted via the pretinning process, it can be compatible with its existing surface mount technology (SMT). This study referred to the Taguchi experimental design to plan its experiment. Three quality characteristics related to the consistency

In the above article [1] , a new reference [19] must be added to the end of the last sentence of the second paragraph in Section I: “Recently, Cu TSV filling has been completed, and therefore making it a complete structure which contains both 3-D MIM capacitor and Cu TSV core [19].” The details of [19] are as follows:

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