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Analysis of thermal stability in underlap and overlap DMG FinFETs including self-heating effects Microelectron. J. (IF 2.2) Pub Date : 2024-03-09 Rashi Chaudhary, Rajesh Saha, Menka Yadav
This work investigates the impact of the self-heating effect (SHE) on SOI Dual-Material Gate (DMG) FinFETs with channel engineering including gate underlapped and overlapped structures. Both these structures are compared with conventional DMG FinFET to detect the possible effects of SHE on DC characteristics and thermal parameters. The drop rates of ON current (I), Off-current (I), Maximum transconductance
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A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS Microelectron. J. (IF 2.2) Pub Date : 2024-03-08 Heng Zhang, Xuan Guo, Ben He, Hanbo Jia, Xinyu Liu
This paper proposed a pipelined analog-to-digital converter (ADC) that utilizes a high-linearity input buffer and a two-step input-split fully differential ring amplifier (ringamp). The implemented input buffer based on a gain-boost cascode current source, is optimized for linearity over a wider frequency range by suppressing fluctuations in tail current. To save power consumption without compromising
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Ultra-wideband high gain low group delay variation amplifier for phased-array radar system Microelectron. J. (IF 2.2) Pub Date : 2024-03-07 Bofan Chen, Zhiqun Li, Zewen Xu, Jiapeng Wan, Zhennan Li, Yitong Xiong, Yan Pu
This paper describes an ultra-wideband (UWB) three-stage cascaded high gain amplifier with low group delay variation for phased-array radar system. The shunt inductor at the input not only provides an electrostatic discharge (ESD) path to ground, but also introduces a new notch for , thus extending the matching bandwidth. Staggered tuning of load impedance peaks at each stage facilitates a balance
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Modeling of inner-outer gates and temperature dependent gate-induced drain leakage current of junctionless double-gate-all-around FET Microelectron. J. (IF 2.2) Pub Date : 2024-03-07 Nitish Kumar, Aakanksha Mishra, Ankur Gupta, Pushpapraj Singh
—In this paper, the temperature-dependent gate-induced drain leakage (GIDL) current model is proposed with the help of a lateral electric field (E) across the inner and outer gate interfaces of the junctionless double-gate-all-around (JL-DGAA) field-effect transistor (FET). The E at the interface is obtained from the surface potential equation after solving the 3D Poisson equation with appropriate
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Design and application of germanium based complementary TFET devices with step tunneling paths Microelectron. J. (IF 2.2) Pub Date : 2024-03-06 Rui Chen, Huiyong Hu, Xinlong Shi, Ruizhe Han, Peijian Zhang, Tao Liu, Liming Wang
Expanding tunneling has consistently been one of the approaches to enhance the on-state current () and performance of Tunnel Field-Effect Transistor (TFET). This paper proposes a novel structure for TFET called Step Tunneling Path TFET (STP TFET). The stepped tunneling path is achieved by preparing majority carrier channel and introducing pocket doping layers and lightly doped channel extension regions
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A 0.6V 119 dB High-CMRR Low-NEF PGA with common-mode voltage control for ECG recording Microelectron. J. (IF 2.2) Pub Date : 2024-03-06 Siwan Dong, Ruoyu Zhang, Chuqiang Jing, Menghan Yuan
This paper proposes a programmable gain amplifier (PGA) with common-mode voltage control for ECG recording. In order to ensure that input common-mode interference (CMI) does not deteriorate amplifier performance, a novel common-mode voltage control module is proposed, which soaks up CMI and maintains the common-mode input within the expected range. Utilizing a standard 65 nm CMOS process, our PGA runs
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A high-throughput and low-storage stereo vision accelerator with dependency-resolving strided aggregation for 8-path semi-global matching Microelectron. J. (IF 2.2) Pub Date : 2024-03-05 Yitong Rong, Xuyang Duan, Jun Han
Semi-global matching(SGM) is a well-known algorithm that generates depth maps from two images. However, due to its high computation, memory requirements and the inherent data dependency problem, implementing SGM in real-time is challenging. In this paper, we propose dependency-resolving strided cost aggregation(SCA) to resolve the data dependency problem. We also propose a cost distillation scheme
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A new CMOS-memristor based D-latch with fewer components Microelectron. J. (IF 2.2) Pub Date : 2024-03-05 Ge Shi, Chenyu Wang, Fei Qiao, Rubin Lin, Shien Wu, Yanwei Sun, Mang Shi, Jianqiang Han
In order to study the function of memristor in new devices, a new D-latch is proposed in this paper, which is composed of threshold-type memristor, transistor, resistor and NOT gate. The proposed D-latch uses fewer components than previous. The transistor controls the on-off of the signal, and NOT gate changes the resistance state of memristor. The voltage divider circuit composed of memristor and
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A low power 16-bit 50 MS/s pipeline ADC with 104 dB SFDR in 0.18 μm CMOS Microelectron. J. (IF 2.2) Pub Date : 2024-03-04 Xiaodan Zhou, Weipeng He, Dongbing Fu, Jianan Wang, Guangbing Chen, Qiang Li
This paper presents a low-power 16-bit 50-MS/s pipeline analog-to-digital converter (ADC). An improved switched-capacitor bias technique is proposed to reduce power consumption while maintaining excellent performance, and a novel bootstrapped switch is implemented to improve the linearity further. An INL-(integral nonlinearity) based capacitor mismatch calibration is proposed to calibrate the capacitor
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A high-pass shaped LMS algorithm based predistortion technique for fractional-N BB-DPLLs Microelectron. J. (IF 2.2) Pub Date : 2024-03-02 Tuan Minh Vo
In this paper, we prove that rather than the second-order modulator (DSM) as typically believed using the first-order one yields a faster convergence for the linear-piecewise predistortion technique employed in digital/time converter (DTC) based fractional- Bang-Bang digital phase-locked-loops (BB-DPLLs). We also propose a novel technique that addresses the limit-cycle issue happening in near-integer
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A low-noise, 0.05–17.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators Microelectron. J. (IF 2.2) Pub Date : 2024-02-29 Depeng Sun, Ruiqing Wang, Feng Bu, Yuan Gao, Xiaoteng Zhao, Ruixue Ding, Shubin Liu, Rong Zhou
This paper presents a low-noise ultra-wideband fractional-N change pump phase-locked loop (CPPLL). By adopting two parallel voltage-controlled oscillators (VCOs) and the synchronized dual-core design, the 8.5–17.8-GHz output is covered and the phase noise is reduced by about 3 dB with the halving total equivalent inductance of the tank. Meanwhile, the clock distribution is designed to obtain 0.05–8
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An efficient algorithm for estimating gate-level power consumption in large-scale integrated circuits Microelectron. J. (IF 2.2) Pub Date : 2024-02-28 Zejia Lyu, Jizhong Shen
Estimating power dissipation in Very Large Scale Integrated (VLSI) circuits, particularly large-scale sequential circuits, is a significant challenge in Electronic Design Automation (EDA). Benchmarked against PrimeTime PX, the proposed algorithm proficiently analyzes large-scale combinational and sequential circuits. This research begins with a power analysis algorithm for combinational circuits, focusing
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An analytical subthreshold I–V model of SiC MOSFETs Microelectron. J. (IF 2.2) Pub Date : 2024-02-26 Yi Li, Tao Zhou, Geng Jiang, Liangbin Deng, Zixuan Guo, Qiaoling Sun, Bangyong Yin, Yuqiu Yang, Junyao Wu, Huan Cai, Jun Wang, Jungang Yin, Qin Liu, Linfeng Deng
In this article, an analytical I–V model for calculating subthreshold current of SiC MOSFETs is presented. This model starts with planar MOSFETs and utilizes the one-dimensional Poisson’s equation to derive an analytical expression for the surface potential. Subsequently, it employs this expression as a foundation for subthreshold current calculations. Then the model is extended to DMOSFETs based on
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Multi-bit per cycle true random number generator based on XOR-XNOR ring oscillator unit Microelectron. J. (IF 2.2) Pub Date : 2024-02-24 Qitian Fan, Feng Ran, Limin Yan
To achieve a fast and resource-efficient entropy source, we present a novel oscillator unit, called XOR-XNOR ring oscillator (XXRO) which consists of an XOR gate and an XNOR gate. The XXRO unit has an internal feedback loop that allows the accumulation of jitter within the unit. Connecting multiple XXRO units forms a new entropy source. We utilize the differences between the XXRO units in the entropy
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A novel step architecture based negative capacitance (SNC) FET: Design and circuit level analysis Microelectron. J. (IF 2.2) Pub Date : 2024-02-24 Santosh Kumar Padhi, Vadthiya Narendar, Atul Kumar Nishad
This study investigates the effects of temperature on RF/Analog and linearity parameters using a 3 nm technology node Step-Negative capacitance FinFET (SNC-FinFET) for the first time. The SNC-FinFET exhibits superior performance compared to the conventional step architecture, with an enhancement of 7.2% in I (ON-current), 73.58% in I (OFF-current), excellent SS (Sub-threshold Swing) of 57.51 mV/decade
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A nanosecond-scale CuI synaptic memristor prepared by a solution-based process Microelectron. J. (IF 2.2) Pub Date : 2024-02-24 Bochang Li, Wei Wei, Li Luo, Ming Gao, Chunxiang Zhu
Owing to the synaptic behaviors and functions, memristors are intensively studied as a critical component for the neuromorphic computing system which is considered as an effective scenario to tackle the performance bottleneck existing in modern computers based on the von Neumann architecture. A novel synaptic device base on the CuI memristor prepared with a solution-based process is proposed in this
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Performance improvement for the CMOS rail-to-rail amplifier via APSO-based design and SNN’s training Microelectron. J. (IF 2.2) Pub Date : 2024-02-23 Xianming Liu, Shihong Wu, Wenrun Xiao, Chenhui Zhao, Chao Huang, Donghui Guo
This paper proposes an adaptive Particle Swarm Optimization(APSO) global search algorithm and Spiking Neural Network(SNN) surrogate model-based optimization design method for analog integrated circuits performance enhancement. The initial design parameters are calculated by numerical computation. The global design space is extended and explored using APSO in the main loop, with constraint testing ensuring
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Logic-in-memory application of silicon nanotube-based FBFET with core-source architecture Microelectron. J. (IF 2.2) Pub Date : 2024-02-22 Sai Shirov Katta, Tripty Kumari, P.S.T.N Srinivas, Pramod Kumar Tiwari
The performance of a silicon nanotube-based feedback field-effect transistor (SiNT FBFET) with a core-source architecture has been explored in this work for the use in logic-in-memory (LIM) applications. Both n-channel and p-channel FETs with extremely symmetric transfer characteristics and a high current ratio of 10 are implemented in a single structure using the core and outer gates. SiNT FBFET exhibits
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High efficiency active rectifier with low-power self-biased comparator for low-frequency piezoelectric vibration energy harvesting of AUV Microelectron. J. (IF 2.2) Pub Date : 2024-02-19 Tzung-Je Lee, Yu-Wei Liu
This paper proposes an Active Rectifier for low-frequency vibration piezoelectric (PZE) energy harvesting of Autonomous Underwater Vehicle (AUV). By using the cross-coupled NMOS transistors and active driven PMOS transistor, the turned-on resistance across the transistors could be minimized such that the voltage conversion efficiency is improved. Besides, the problem of the reverse current is avoided
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Logic cloning based approximate signed multiplication circuits for FPGA Microelectron. J. (IF 2.2) Pub Date : 2024-02-19 Abhinav Kulkarni, Messaoud Ahmed Ouameur, Daniel Massicotte
As hardware circuits become larger and more intricate, there is a growing need for approximate circuit techniques. These approaches offer a trade-off, sacrificing some system accuracy in exchange for greater hardware resource efficiency and energy conservation. In the context of FPGA-based computation-intensive arithmetic multiplication, Logic Cloning () is introduced to systematically induce controlled
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An optimized EEGNet processor for low-power and real-time EEG classification in wearable brain–computer interfaces Microelectron. J. (IF 2.2) Pub Date : 2024-02-19 Jiacheng Cao, Wei Xiong, Jie Lu, Peilin Chen, Jian Wang, Jinmei Lai, Miaoqing Huang
Brain–computer interfaces (BCIs) based on electroencephalogram (EEG) signals have recently gained significant attention. EEGNet is a lightweight convolutional neural network designed for EEG-based BCIs. Previous EEGNet processors are implemented with high-precision fixed-point numbers, resulting in high power consumption and resource utilization. To address these drawbacks, this paper proposes a low-precision
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An evenly-spaced-phase all-digital DLL using dual-loop SAR control Microelectron. J. (IF 2.2) Pub Date : 2024-02-16 Sijie Chen, Tingcun Wei, Nan Chen
This study introduces an all-digital delay-locked loop (ADDLL), which generates 20 evenly-spaced-phase clock signals. A successive-approximation register (SAR)-based dual-loop control is used to realize the locking process of the ADDLL. A modified SAR unit combined with a tri-state digital phase detector (TSDPD) is adopted to achieve a closed-loop operation of the ADDLL. A delay matrix, which can significantly
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GaN-based wide-band high-efficiency power amplifier with multi harmonic resonance Microelectron. J. (IF 2.2) Pub Date : 2024-02-15 Mohammad Zaid, Ahtisham Pampori, Mohammad Sajid Nazir, Yogesh Singh Chauhan
This paper introduces a novel multi-harmonic resonance approach in designing a single-ended parallel-circuit class – E/F power amplifier (PA). At its core, this innovative design integrates a novel reactance compensation technique with multi-harmonic tuning at the load, to achieve unprecedented wideband characteristics and elevated efficiency. The approach is further distinguished by the strategic
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A design method of bipolar junction transistor for high-precision remote temperature sensing Microelectron. J. (IF 2.2) Pub Date : 2024-02-12 Linfeng Wei, Wenchang Li, Tianyi Zhang, Jian Liu
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A 1.5MSPS, 120 dB SFDR, ±10 V input range SAR ADC with sampling nonlinearity compensation and inherent 2-b coarse ADC for MSBs decision Microelectron. J. (IF 2.2) Pub Date : 2024-02-09 Hongrui Luo, Zihao Jiao, Yang Chen, Jie Zhang, Quan Sun, Xiaofei Wang, Hong Zhang
This paper presents a high-precision, successive-approximation-register (SAR) analog-to-digital converter (ADC) with maximum input range of ±10 V for industry applications, where the wide-range input signal is sampled directly on part of the capacitive digital-to-analog converter (CDAC) via high-voltage (HV) sampling switches. An inherent 2-b coarse ADC is designed to avoid charge leakage under large
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A low-noise class AB amplifier fabricated by 180 nm BCD process for servo circuit of quartz flexible accelerometer Microelectron. J. (IF 2.2) Pub Date : 2024-02-08 Peipei Li, Li Luo, Qi Wei
Quartz Flexible Accelerometer (QFA) system has gained extensive utilization in related navigation system due to the high precision, exceptional stability, and rapid response. The operational amplifier as the pivotal component of the analog servo circuit intricately relative to the performance of the QFA system. In this paper, the electrical mechanism of the QFA readout system and the influence of operational
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A novel recessed-source negative capacitance gate-all-around tunneling field effect transistor for low-power applications Microelectron. J. (IF 2.2) Pub Date : 2024-02-08 Weijie Wei, Weifeng Lü, Ying Han, Caiyun Zhang, Dengke Chen
A recessed-source (RS) negative capacitance (NC) gate-all-around (GAA) tunneling field effect transistor (RS-NCGAATFET) was proposed to achieve low power consumption and high performance. An additional RS allowed easy control of the operation of the NCGAATFET by both lateral and vertical band-to-band tunneling. Furthermore, the RS enhanced the driving ability and capacitance characteristics of the
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A 4–20 GHz switched-line true time delay in GaAs pHEMT technology Microelectron. J. (IF 2.2) Pub Date : 2024-02-08 Jie Wang, Dongning Hao, Wei Zhang, Xiubo Liu, Zhangyong Li, Yanyan Liu
A 5-bit switched-line true time delay (TTD) circuit is proposed based on 0.25-μm GaAs pHEMT technology. The delay structure within the TTD units is formed by employing second-order all-pass networks (APNs). A double-pole double-throw (DPDT) switch is specifically designed to replace the conventional cascading of two single-pole double-throw (SPDT) switches, thus, minimizing the insertion loss introduced
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A 9T-SRAM based computing-in-memory with redundant unit and digital operation for boolean logic and MAC Microelectron. J. (IF 2.2) Pub Date : 2024-02-07 Xin Li, Mengya Gao, Zihua Ren, Kefeng Yu, Wenjuan Lu, Chenghu Dai, Wei Hu, Chunyu Peng, Xiulong Wu
The proposal of compute-in-memory (CIM) is a breakthrough for the traditional von Neumann architecture to achieve efficient computing research. This architecture has unique advantages in the computing field thanks to supporting multi-line computing and without data transmission between processor and memory. In this paper, an in-memory computing structure based on 9T SRAM unit is proposed, which can
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High throughput dynamic dual entropy source true random number generator based on FPGA Microelectron. J. (IF 2.2) Pub Date : 2024-02-07 Yu Chen, Huaguo Liang, Linghui Zhang, Liang Yao, Yingchun Lu
True Random Number Generator (TRNG), a primitive language of hardware security, plays a significant role in key generation, data encryption, initialization vectors, and other situations. To address the problem of incompatibility between low resource overhead and high throughput of TRNG, a dual entropy source TRNG architecture based on Field Programmable Gate Array (FPGA) is proposed, whose entropy
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Performance investigation of different low power SRAM cell topologies using stacked-channel tri-gate junctionless FinFET Microelectron. J. (IF 2.2) Pub Date : 2024-02-05 Devenderpal Singh, Shalini Chaudhary, Basudha Dewan, Menka Yadav
At the sub-22 nm technology node, junctionless FinFETs are regarded as advantageous alternatives for conventional FinFET due to their simpler fabrication and uniform doping concentrations. These devices are the most significant alternatives to CMOS technology which can be used in the most recent static random access memory (SRAM) cells. The paper presents a novel high noise margin and low subthreshold
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A high gain-flatness C-band variable gain LNA in a 0.25 μm GaAs pHEMT process Microelectron. J. (IF 2.2) Pub Date : 2024-01-31 Dengbao Sun, Cong Zhou, Guodong Su, Zengda Wang, Xiang Wang, Jun Liu
This paper presents a C-band (4–8 GHz) transconductance-controlled variable gain low noise amplifier (Gm-VGLNA) with excellent gain-flatness. The impedance and gain of the improved amplifier-cell (IA) are analyzed, and a current-controlled E-mode pHEMT load (CEL) structure is proposed to improve the gain-flatness performance in a wideband frequency range. The Gm-VGLNA is designed and fabricated using
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A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks Microelectron. J. (IF 2.2) Pub Date : 2024-02-03 Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
Recently, self-driving cars have been eagerly studied and developed. In such applications, to transmit large-capacity data acquired by sensor devices such as radars, LiDARs, and high-definition cameras, optical fiber networks are promising as intra-vehicle systems. One type of intra-vehicle optical network has a unidirectional optical ring topology, in which the optical receiver operates in the burst
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Effect of ambipolarity suppression in PNPN TFET with dopant segregated Schottky-drain technique Microelectron. J. (IF 2.2) Pub Date : 2024-01-29 Aadil Anam, S. Intekhab Amin, Dinesh Prasad, Naveen Kumar, Sunny Anand
In this paper, a comparative analysis of ambipolarity suppression in conventional PNPN-TFET(D-1) is studied using TCAD simulation. By replacing the drain with metal silicide, and by implementing the dopant-segregated Schottky-barrier drain (DSSBD) in conventional PNPN-TFET, two new devices named PNPM-TFET(D-2) and DSSB-PNPM-TFET(D-3) has been proposed for suppressing the ambipolarity. The narrow n+
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Real-time channel temperature monitoring of p-GaN HEMTs based on gate leakage current Microelectron. J. (IF 2.2) Pub Date : 2024-01-29 Luqiao Yin, Shuang Wu, Kailin Ren, Wenkui Zhang, Jianhua Zhang
The thermal response of Lateral GaN-based High Electron Mobility Transistor (HEMT) is much faster than that of Si-based power devices, owing to its higher power density. This makes temperature-related effects even more critical for GaN HEMTs, highlighting the necessity of monitoring their operating temperature to improve the efficiency and reliability of power circuits. In this article, a real-time
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Optimization of junctionless stacked nanosheet FET – RF stability perspective Microelectron. J. (IF 2.2) Pub Date : 2024-02-02 Balasubbareddy M, Sivasankaran K
Radio frequency (RF) stability is an indispensable selection component to operate the device in RF range. An unstable device is susceptible to oscillating for any passive termination networks at input/output ports. In this article, the RF stability performance of junctionless stacked nanosheet FET (JL-SNSHFET) is deliberated by investigating the impact of its geometrical parameters, and ambient temperature
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A comparative study of work function variations in III-V heterojunction and homojunction tunnel field-effect transistors Microelectron. J. (IF 2.2) Pub Date : 2024-01-31 Yunhe Guan, Jiachen Lu, Hao Zhang, Zhen Dou, Haifeng Chen, Feng Liang
In this paper, we present a comparative study on the impact of work function variations (WFV) between the III-V heterojunction and homojunction tunnel field-effect transistors (TFETs) vis TCAD simulation. It reveals that, in general, the current variation of both devices decrease as the gate voltage increases, and the threshold voltage variations generally increase with the increase of threshold current
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A 55 μ W 2.4 GHz wake-up receiver with offset-based peak detection achieving −90dBm sensitivity for IoT applications Microelectron. J. (IF 2.2) Pub Date : 2024-01-26 Yan Zhao, Chao Chen, Jun Yang
The paper proposes a 2.4 GHz ultra-low power wake-up receiver (WuRX) with offset-based peak detection and mixer-first based radio frequency (RF) front-end for IoT applications. The mixer-first based front-end eliminates RF modules to reduce power consumption. Based on the transparency of the passive mixing switches, a 2-path passive mixer (2-PPM) constructs the high-Q band-pass filter (BPF) at the
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A complementary ternary inverter based on the line tunneling field effect transistors Microelectron. J. (IF 2.2) Pub Date : 2024-01-28 Bin Lu, Dawei Wang, Guoqiang Chai, Yulei Chen, Zhu Li, Jiale Sun, Hongliang Lu
A novel line-tunneling field effect transistor (LTFET) incorporating a reversed p-i-n structure is introduced. The line-tunneling process provides high ION and low SS while the reversed p-i-n structure keeps the IOFF independent on the gate voltage. The inclusion of this mixed conduction mechanism renders the proposed device well-suited for designing complementary ternary logic based on the off-state
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Non-fourier phonon heat transport in graphene nanoribbon field effect transistors based on modified phonon hydrodynamic lattice Boltzmann method Microelectron. J. (IF 2.2) Pub Date : 2024-01-24 Xixin Rao, Songcheng Li, Yuancheng Yan, Haitao Zhang, Chengdi Xiao
Graphene, with its exceptional thermal conductivity and electron mobility, is widely recognized as a potential candidate for next-generation transistor materials. Despite the lack of pronounced phonon hydrodynamic phenomena at room temperature in graphene materials, momentum-conserving phonon normal scattering predominantly drives phonon hydrodynamic transport. Current methodologies, including the
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A precision current sensing circuit with chopper amplifier of symmetric topology Microelectron. J. (IF 2.2) Pub Date : 2024-01-24 Tian Han, Fazhan Zhao, Ximing Fu, Xiaowu Cai, Weiwei Yan, Haitao Zhao, Wenxin Zhao, Bo Li
Precision current detection is essential in smart power switches. In this paper, a current-sensing amplifier with symmetric topology is presented, which adopts the chopping technique to improve sensing accuracy. This design offers four advantages at the same time. Firstly, the rail-to-rail complementary differential pairs are achieved to obtain a full input voltage swing, and the Class AB output stage
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A Fractional-N DTC-based ADPLL using path-select multi-delay line TDC and true fractional division technique Microelectron. J. (IF 2.2) Pub Date : 2024-01-24 Zirui Jin, Ang Hu, Xiaoyu Shan, Dongsheng Liu, Chengcheng Zhang, Jinsong Cui, Xuecheng Zou
This paper presents a fractional-N all-digital phase-locked loop (ADPLL). A 4-bit multi-delay line time-to-digital converter (MDL-TDC) using path selection technique is proposed to achieve a 4-ps resolution with 0.24-mW power consumption at 52 MS/s. A TDC offset calibration method is used to eliminate TDC metastability. An isolated constant-slope digital-to-time converter (ICS-DTC) is utilized to cancel
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Study on the impact of the resonant cavity and lateral acoustic edge reflector for AlSc0.095N-based S0 mode Lamb-wave resonators Microelectron. J. (IF 2.2) Pub Date : 2024-01-23 Jicong Zhao, Zexin Sun, Zhi Dong, Yanmeng Dang, Shitao Lv, Wenhao Ye, Haiyan Sun, Quan Shi
In this paper, the impact of the resonant cavity and lateral acoustic edge reflector on the performance of the S0 mode Lamb-wave resonators based on Aluminum nitride film doped with scandium concentration of 9.5 % (AlSc0.095N) were systematically studied. Through the theoretical analysis and experimental verification, we found that the Q value of the resonator can be improved by defining a miniaturized
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A 6T1C pixel circuit compensating for TFT electrical characteristics variations, voltage drop, and OLED degradation Microelectron. J. (IF 2.2) Pub Date : 2024-01-17 Huicheng Zhao, Bo Yu, Ning Wei, Hongzhen Chu, Yuehua Li, Xinlin Wang, Hongyu He
A voltage-programmed pixel circuit based on low-temperature poly-silicon (LTPS) thin-film transistors (TFTs) is presented for active-matrix organic light-emitting diode (AMOLED) displays. The circuit consists of six p-type transistors and one capacitor (6T1C). During the extraction stage, the circuit extracts the driving TFT’s threshold voltage and the power supply voltage. During the data input stage
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Optimization of DE-QG TFET using novel CIP and DCT techniques Microelectron. J. (IF 2.2) Pub Date : 2024-01-16 Manivannan T.S., K.R. Pasupathy, Mohd Rizwan Uddin Shaikh, G. Lakshminarayanan
In this paper, two novel techniques Channel-Intermediate-Pocket (CIP) and Dual-Channel-Type (DCT) are proposed to optimize the Drain Engineered-Quadruple Gate TFET (DE-QG TFET). The proposed DCT technique is realized by making half of the channel area with lightly doped n- and the other half with the lightly doped p- channel. The CIP technique is implemented by inserting a pocket exactly at the junction
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A 28.9–38.8 μW dual-mode 10-bit column parallel single-slope ADC with minimum voltage feedback for CMOS image sensors Microelectron. J. (IF 2.2) Pub Date : 2024-01-16 Shengping Yuan, Zhoudeng Li, Shanghong Yu, Fanghui Yin, Xian Tang
A dual-mode low-power column parallel single-slope (SS) ADC incorporating Minimum Voltage Feedback (MVF) is proposed for CMOS image sensors. When it works in low-power mode, the ADC utilizes a minimum voltage feedback approach and a dynamic bias structure to minimize the power consumption after the ramp signal surpasses the minimum voltage of a row. In its acceleration mode, it uses the minimum voltages
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Physics based model development of a double gate reverse T-shaped channel TFET including 1D and 2D band-to-band tunneling components Microelectron. J. (IF 2.2) Pub Date : 2024-01-13 K. Manikanta, Umakanta Nanda, Chandan Kumar Pandey
In this article, a Double gate reverse T-shaped channel tunnel field effect transistor (DG-RT-TFET) is mathematically modeled. The TFET has the potential for exhibiting various types of tunneling mechanisms. The modeled device encompasses both 1D and 2D Band-to-Band (BTBT) tunneling components, with each component developed in the epi-channel and channel, respectively. The study reveals that the 2D
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Comprehensive experimental study on Schottky contact super barrier rectifier Microelectron. J. (IF 2.2) Pub Date : 2024-01-14 Qisheng Yu, Zhengyuan Zhang, Aohang Zhang, Jiaweiwen Huang, Wensuo Chen
In this paper, on the basis of further discussion of the device structure and operational mechanism of the Schottky contact Super Barrier Rectifier (SSBR), more key experimental results and comparative analysis are added. The experimental results and discussion of the influence of Schottky contact barrier, supper barrier, key cellular parameters and epitaxial layer on device performance are proposed
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Single inductor multi-PZTs SECE and electromagnetic voltage multiplier rectifier hybrid interface circuit Microelectron. J. (IF 2.2) Pub Date : 2024-01-10 Ge Shi, Xiangzhan Hu, Shengyao Jia, Xing Liang, Yanwei Sun, Mang Shi, Binrui Wang
This paper proposes a single inductor multi-piezoelectric transducers (PZTs) SECE and electromagnetic voltage multiplier rectifier hybrid interface circuit (MP-SECE-VMR), which harvest energy from multi-input PZTs and electromagnetic generator (EMG). The MP-SECE-VMR adopts a voltage multiplier rectifier circuit, utilizing the diode-connected MOSFET configuration which used as diodes to effectively
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A 65 nm CMOS rail-to-rail auto-zero operational amplifier based on charge pump internal power supply Microelectron. J. (IF 2.2) Pub Date : 2024-01-09 Jun-an Zhang, Chuandao Zhang, Yuan Feng, Qingwei Zhang, Tiehu Li
A high-gain, low-offset, and low-power auto-zero operational amplifier with rail-to-rail input/output is proposed. Based on a time-interleaved charge pump high-voltage on-chip internal power supply, the PMOS differential pair input configuration will achieve a rail-to-rail input range with constant transconductance. Time-interleaved auto-zero continuously eliminates the input offset voltage of the
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A 2-2 MASH ΔΣ ADC with fast-charge CLS input buffer and dual double sampling achieving 103.3-dB SNDR and ±2.5-ppm/FSR INL Microelectron. J. (IF 2.2) Pub Date : 2024-01-03 Yang Chen, Binyu Cai, Changhuan Chen, Weiliang Peng, Quan Sun, Xiaofei Wang, Hong Zhang
This paper presents a 2-2 multi-stage-noise-shaping (MASH) ΔΣ analog-to-digital converter (ADC), in which an integrator with dual double sampling (DDS) technique and stability compensation is proposed to save the area of capacitors without increasing the thermal noise. In addition, a fast-charge correlated-level-shifting (CLS) input buffer is also proposed to improve the linearity with acceptable power
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Numerical simulation of copper electrodeposition for Through Silicon Via (TSV) with SPS-PEG-Cl additive system Microelectron. J. (IF 2.2) Pub Date : 2024-01-02 Yanan Tao, Chao Liang, Ziqi Mei, Zhiqiang Song, Yu Wu, Yunna Sun, Wenqiang Zhang, Yong Ruan, Xiaoguang Zhao
Through silicon via (TSV) technology is crucial for modern semiconductor device package, enabling high-performance integrated microsystems. This paper investigates the mechanism of the bottom-up copper deposition process in TSV, leveraging a co-adsorbed polyether-Cl-suppression layer and accelerators for optimized filling profiles. We present numerical simulations of the effects of additives (accelerator
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A 0.55-mm2 8-bit 32-GS/s TI-SAR ADC with optimized hierarchical sampling architecture Microelectron. J. (IF 2.2) Pub Date : 2024-01-05 Jiale Ding, Yukai Huang, Hao Zhang, Tian Feng, Feida Wang, Dengquan Li, Zhangming Zhu
This paper analyzes the bandwidth of the time-interleaved analog-to-digital converter (TI-ADC) with hierarchical sampling and presents an 8-bit 32-GS/s TI-ADC in 28-nm CMOS. The front-end sampler is implemented by a two-stage hierarchical sampling architecture to extend the analog input bandwidth. The 32-way sub-ADCs are realized with 2b/cycle successive approximation register (SAR) architecture and
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A 8.1-nW, 4.22-kHz, −40–85 °C relaxation oscillator with subthreshold leakage current compensation and forward body bias buffer for low power IoT applications Microelectron. J. (IF 2.2) Pub Date : 2024-01-05 Rong Zhou, Linwei Wang, Jianhang Yang, Zhen Li, Xiaoteng Zhao, Shubin Liu
This paper presents a relaxation oscillator (RxO) utilizing subthreshold transistor leakage current compensation (SLC) technology to expand the operating range from 70 °C to 85 °C at high temperatures. The compensated RxO outperforms the uncompensated counterpart by 25 times for temperature coefficient (TC). Additionally, forward body bias (FBB) technology optimizes the digital buffer delay with temperature
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Inverter-based noise-shaping SAR ADC for low-power applications Microelectron. J. (IF 2.2) Pub Date : 2024-01-05 Ali Badawy, Ayman Ismail
Noise-Shaping (NS) Successive-Approximation (SAR) Analog-to-Digital Converters (ADCs) are one of the most heavily researched ADC topologies in recent years. This high attention is attributed to the advantages of the NS SAR architecture that combines the merits of ΣΔ and SAR converters. However, the implementation of the NS SAR loop-filter in a passive or an active form imposes challenging tradeoffs
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Improvement of reverse conduction characteristic and single event effect for a novel vertical GaN field effect transistor with an integrated MOS-channel diode Microelectron. J. (IF 2.2) Pub Date : 2024-01-04 Xintong Xie, Shuxiang Sun, Zhijia Zhao, Pengfei Zhang, Jie Wei, Xin Zhou, Jingyu Shen, Jinpeng Qiu, Xiaorong Luo
A vertical GaN-based field-effect transistor with an integrated MOS-channel diode (MCD) is used to improve the reverse conduction characteristic and transient single-event effect (SEE). The device features an MCD acting as a free-wheel diode formed between trench source metal on the source dielectric and a P-type blocking layer (PBL), wherein MIS structure is formed by trench source, source dielectric
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The area-efficient gate level information flow tracking schemes of digital circuit with multi-level security lattice Microelectron. J. (IF 2.2) Pub Date : 2024-01-03 Yongliang Chen, Xiaole Cui, Xiaoxin Cui, Xing Zhang
The Gate Level Information Flow Tracking (GLIFT) is an effective method to uphold the information security for high-assurance digital circuits. The GLIFT method associates a security label with each data bit and monitors these labels to expose the illegal information flow in the circuit under tracking. However, the label propagation usually consumes a significant area overhead, especially for the multi-level
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Noninverting Schmitt trigger circuit with electronically tunable hysteresis Microelectron. J. (IF 2.2) Pub Date : 2023-12-28 Aryan Kannaujiya, Abhay Pratap Singh, Ambika Prasad Shah
This paper reports a tunable hysteresis CMOS Schmitt trigger design techniques and an investigation of new buffer-based designs. The sizing of the two feedback inverters controls the two trip points of the structure independently. By the addition of voltage tune controlled sourcing transistor, the hysteresis window can be easily changed. Moreover, the new designs are immune to the kick-back noise coming
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A 5 kHz-BW 18-bit zoom ADC with gain-enhanced CLS-assisted FIA Microelectron. J. (IF 2.2) Pub Date : 2023-12-26 Wenjia Xu, Ming Chen, Li Zhou, Jie Chen
This paper presents a 5 kHz-BW 18-bit fully dynamic zoom ADC for low-power and high-resolution applications. A gain-enhanced cascode floating inverter amplifier (FIA) with correlated level shifting (CLS) assisted is proposed to achieve 68.5 dB effective gain with high energy efficiency. The data-weighted averaging (DWA) technique is implemented to suppress the nonlinearity caused by feedback DAC mismatch