The performance of silicon complementary metal–oxide–semiconductor integrated circuits can be enhanced through the monolithic three-dimensional integration of additional device layers. For example, silicon integrated circuits operate at low voltages (around 1 V) and high-voltage handling capabilities could be provided by monolithically integrating thin-film transistors. Here we show that high-voltage amorphous oxide semiconductor thin-film transistors can be integrated on top of a silicon integrated circuit containing 100-nm-node fin field-effect transistors using an in-air solution process. To solve the problem of voltage mismatch between these two device layers, we use a top Schottky, bottom ohmic contact structure to reduce the amorphous oxide semiconductor circuit switching voltage. These contacts are used to form Schottky-gated thin-film transistors and vertical thin-film diodes with excellent switching performance. As a result, we can create high-voltage amorphous oxide semiconductor circuits with switching voltages less than 1.2 V that can be directly integrated with silicon integrated circuits.

可以通过附加器件层的单片三维集成来增强硅互补金属-氧化物-半导体集成电路的性能。例如，硅集成电路在低电压（大约1 V）下工作，并且可以通过单片集成薄膜晶体管来提供高电压处理能力。在这里，我们表明，可以使用空中解决方案将高压非晶氧化物半导体薄膜晶体管集成到包含100纳米节点鳍式场效应晶体管的硅集成电路的顶部。为了解决这两个器件层之间的电压不匹配的问题，我们使用顶部肖特基底部欧姆接触结构来降低非晶氧化物半导体电路的开关电压。这些触点用于形成具有出色开关性能的肖特基门控薄膜晶体管和垂直薄膜二极管。结果，我们可以创建开关电压小于1.2 V的高压非晶氧化物半导体电路，该电路可以直接与硅集成电路集成。