This paper presents a dual driven feedback 10T (DDFB10T) static random-access memory (SRAM) bit cell with good read and write stability and that is free from half select issue. This DDFB10T cell working at V_DD = 0.9 V achieves 1.5× higher static voltage noise margin (SVNM), and 0.48× lesser write trip voltage (WTV) than 6T SRAM cell. Monte Carlo simulation employing local and global variation using Cadence Virtuoso tool with 45 nm technology proves that the proposed bit cell is highly immune against process, voltage, and temperature (PVT) variations. The proposed DDFB10T bit cell exhibits lesser SVNM variability when it is normalized to that of 6T SRAM bit cell. The proposed DDFB10T cell is designed with the capability to provide a bit interleaved architecture for reducing half select issues.

本文提出了一种双驱动反馈 10T (DDFB10T) 静态随机存取存储器 (SRAM) 位单元，具有良好的读写稳定性，并且没有半选问题。与 6T SRAM 单元相比，该 DDFB10T 单元在 V _DD  = 0.9 V 下工作的静态电压噪声容限 (SVNM) 高 1.5 倍，写入触发电压 (WTV) 低 0.48 倍。蒙特卡罗模拟使用具有 45 nm 技术的 Cadence Virtuoso 工具采用局部和全局变化证明，所提出的位单元对工艺、电压和温度 (PVT) 变化具有高度免疫性。所提出的 DDFB10T 位单元在归一化为 6T SRAM 位单元时表现出较小的 SVNM 可变性。所提议的 DDFB10T 单元设计为能够提供位交错架构以减少半选择问题。