SiO₂ is one of the most widely used dielectric materials in optical and electronic devices. The Josephson voltage standard (JVS) chip fabrication process has rigorous requirements for the deposition temperature and step-coverage profiles of the SiO₂ insulation layer. In this study, we deposited high-quality SiO₂ insulation films at 60 °C using inductively coupled plasma-chemical vapor deposition (ICP-CVD) to fulfill these requirements and fabricate JVS chips simultaneously. SiO₂ films have a high density, low compressive stress, and a sloped sidewall profile over the vertical junction steps. The sidewall profiles over the vertical junction steps can be adjusted by changing the radio frequency (RF) power, ICP power, and chamber pressure. The effects of sputtering etch and sloped step coverage were enhanced when the RF power was increased. The anisotropy ratio of the deposition rate between the sidewall and the bottom of the film was lower, and the sloped step coverage effect was enhanced when the ICP power was increased, or the deposition pressure was decreased. The effects of the RF power on the stress, density, roughness, and breakdown voltage of the SiO₂ films were also investigated. Despite increased compressive stress with increasing RF power, the film stress was still low and within acceptable limits in the device. The films deposited under optimized conditions exhibited improved densities in the Fourier transform infrared spectra, buffered oxide etch rate, and breakdown voltage measurements compared with the films deposited without RF power. The roughness of the film also decreased. The step-coverage profile of the insulation layer prepared under optimized conditions was enhanced in the junction and bottom electrode regions; additionally, the performance of the device was optimized. This study holds immense significance for increasing the number of junctions in future devices.

中文翻译：

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用于垂直阶梯覆盖的具有倾斜侧壁轮廓的高质量 SiO2 薄膜的低温沉积

SiO ₂是光学和电子器件中使用最广泛的介电材料之一。_{约瑟夫森电压标准 (JVS) 芯片制造工艺对 SiO 2}绝缘层的沉积温度和阶梯覆盖曲线有严格的要求。在这项研究中，我们使用电感耦合等离子体化学气相沉积 (ICP-CVD) 在 60 °C 下沉积了高质量的 SiO _{2绝缘膜，以满足这些要求并同时制造 JVS 芯片。}二氧化硅_{_}薄膜在垂直结台阶上具有高密度、低压缩应力和倾斜的侧壁轮廓。可以通过改变射频 (RF) 功率、ICP 功率和腔室压力来调整垂直结台阶上的侧壁轮廓。当射频功率增加时，溅射蚀刻和倾斜台阶覆盖的效果会增强。增加ICP功率或降低沉积压力时，侧壁与薄膜底部之间沉积速率的各向异性比较低，倾斜阶梯覆盖效果增强。RF功率对SiO _{2的应力、密度、粗糙度和击穿电压的影响}电影也进行了调查。尽管随着射频功率的增加压缩应力增加，但薄膜应力仍然很低，并且在器件的可接受范围内。与没有射频功率沉积的薄膜相比，在优化条件下沉积的薄膜在傅里叶变换红外光谱、缓冲氧化物蚀刻速率和击穿电压测量中表现出更高的密度。薄膜的粗糙度也降低了。在优化条件下制备的绝缘层的阶梯覆盖分布在结和底部电极区域得到了增强；此外，还优化了设备的性能。这项研究对于增加未来设备中的结数量具有重要意义。