This article presents an analytical approach to estimate jitter in CMOS inverters in the presence of ground-bounce noise (GBN). The relationships between output and input, considering the effect of ground noise, are derived in terms of device parameters for modeling the timing variations. The deviation of each transition edge from the ideal transition edge is modeled using analytical equations to obtain peak-to-peak ground noise induced jitter. To examine the proposed modeling, five case studies are considered for covering the time domain as well as frequency domain estimations. The results obtained using the proposed methodology have a close match with those obtained from the simulations using the electronic design automation (EDA) tool. To claim the independence of proposed modeling with respect to a particular technology, the results are verified at 40, 65, and 180 nm technology nodes of United Microelectronics Corporation (UMC).

中文翻译：

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基于器件参数的 CMOS 逆变器中接地反弹引起的抖动的分析建模

本文介绍了一种分析方法，用于在存在接地反弹噪声 (GBN) 的情况下估计 CMOS 反相器中的抖动。考虑到接地噪声的影响，输出和输入之间的关系是根据用于对时序变化进行建模的设备参数得出的。使用解析方程对每个过渡边沿与理想过渡边沿的偏差进行建模，以获得峰峰值接地噪声引起的抖动。为了检查所提出的建模，考虑了五个案例研究来涵盖时域和频域估计。使用所提出的方法获得的结果与使用电子设计自动化 (EDA) 工具从模拟中获得的结果非常匹配。声称提出的建模相对于特定技术的独立性，