A potential barrier is one of the most common lag sources for charge transfer in pinned photodiode (PPD) CMOS image sensors (CISs). In this article, an analytical model of the potential barrier is proposed for the PPD combined with the transfer gate (TG). Through detailed electrostatic analysis of the PPD and TG, the potential barrier is analytically expressed as a function of the doping concentrations, TG voltage, spatial dimensions, and other physical parameters. The proposed model is validated by technology computer-aided design (TCAD) simulations, and the results show that the model data are in good agreement with the TCAD simulations in terms of the magnitude and location of the potential barrier. The model can be used for the design, simulation, and optimization of PPD-based pixels in CISs to improve the charge transfer efficiency (CTE) and reduce the image lag noise.

中文翻译：

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钉扎光电二极管 CMOS 图像传感器中电荷转移势垒的分析建模

势垒是固定光电二极管 (PPD) CMOS 图像传感器 (CIS) 中电荷转移最常见的滞后源之一。在本文中，提出了一种结合传输门（TG）的PPD的势垒分析模型。通过对 PPD 和 TG 的详细静电分析，势垒分析表示为掺杂浓度、TG 电压、空间尺寸和其他物理参数的函数。所提出的模型通过技术计算机辅助设计（TCAD）模拟进行了验证，结果表明，模型数据在势垒的大小和位置方面与 TCAD 模拟具有良好的一致性。该模型可用于设计、仿真、