Unclamped inductive switching (UIS) robustness of SiC devices with parallel-connected varistor was evaluated to design the cutoff current capability of solid-state circuit breakers (SSCBs). Because the operation of UIS tests is similar to that in the interruption of SSCBs, UIS tests of SiC devices without varistor and with a parallel-connected varistor were implemented. It was found that the cutoff current of SiC devices with the varistor was much larger than that without varistor. The effect of varistor on the increase of cutoff current depended on the device type and rating current. The cutoff current was 3–6 times higher for planar MOSFETs and 5–10 times higher for trench MOSFETs compared with no varistor condition. In contrast, the effect of varistor for JFET was small because the gate drive condition strongly affected the current switching time from SiC-JFET to varistor. The index of rating current for cutoff current capability was changed by parallel varistor connection because the destruction mechanism of SiC devices was changed because of the change in self-heating timing during the UIS.

中文翻译：

---

具有并联压敏电阻的 SiC 器件的无钳位感应开关鲁棒性,具有并联压敏电阻的 SiC 器件的无钳位感应开关鲁棒性

评估了具有并联压敏电阻的 SiC 器件的非钳位感应开关 (UIS) 鲁棒性，以设计固态断路器 (SSCB) 的截止电流能力。由于 UIS 测试的操作类似于 SSCB 的中断，因此对没有压敏电阻和并联压敏电阻的 SiC 器件进行了 UIS 测试。发现带压敏电阻的 SiC 器件的截止电流远大于不带压敏电阻的器件。压敏电阻对截止电流增加的影响取决于器件类型和额定电流。与无压敏电阻条件相比，平面 MOSFET 的截止电流高 3-6 倍，沟槽 MOSFET 的截止电流高 5-10 倍。相比之下，压敏电阻对 JFET 的影响很小，因为栅极驱动条件强烈影响从 SiC-JFET 到压敏电阻的电流切换时间。由于 SiC 器件的破坏机制因 UIS 期间自发热时间的变化而改变，因此通过并联变阻器连接改变了截止电流能力的额定电流指标。,评估了具有并联压敏电阻的 SiC 器件的非钳位感应开关 (UIS) 鲁棒性，以设计固态断路器 (SSCB) 的截止电流能力。由于 UIS 测试的操作类似于 SSCB 的中断，因此对没有压敏电阻和并联压敏电阻的 SiC 器件进行了 UIS 测试。发现带压敏电阻的 SiC 器件的截止电流远大于不带压敏电阻的器件。压敏电阻对截止电流增加的影响取决于器件类型和额定电流。与无压敏电阻条件相比，平面 MOSFET 的截止电流高 3-6 倍，沟槽 MOSFET 的截止电流高 5-10 倍。相比之下，压敏电阻对 JFET 的影响很小，因为栅极驱动条件强烈影响从 SiC-JFET 到压敏电阻的电流切换时间。由于 SiC 器件的破坏机制因 UIS 期间自发热时间的变化而改变，因此通过并联变阻器连接改变了截止电流能力的额定电流指标。