This brief presents the on-chip background offset and timing-skew calibration of the 1-then-2b/cycle time-interleaved successive-approximation-register analog-to-digital converter (TI SAR ADC). For timing-skew between sub-ADC’s sampling clocks, a comparator offset-based window detector (WD) is used to adjust the clock edge misalignment. In addition, comparator offset calibration is considered both in terms of 1) global offset (between the offset-free reference comparator and the local reference comparator in each sub-ADC) and 2) local offset (between the local reference comparator and the rest of the comparators in the same sub-ADC). The proposed calibration sufficiently suppresses noise floor and spurs, and all calibrations are performed in the background without interfering with normal ADC operation. The prototype 5-way TI SAR ADC is fabricated in a 28 nm CMOS process and occupies a 0.03 mm2 area including on-chip calibration. With the proposed calibration, the prototype achieves SNDR of 40 dB at Nyquist input and consumes 7.57 mW, leading to the Walden figure of merit ( ${\text {FoM}_{W}}$ ) of 37.2 fJ/conversion-step.

中文翻译：

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具有片上背景偏移和时序偏移校准的 2.5 GS/s 7 位 5 路时间交错 SAR ADC

本简介介绍了 1-then-2b/周期时间交错逐次逼近寄存器模数转换器 (TI SAR ADC) 的片上背景偏移和时序偏移校准。对于子 ADC 采样时钟之间的时序偏差，使用基于比较器偏移的窗口检测器 (WD) 来调整时钟边沿失准。此外，比较器偏移校准从以下两个方面考虑：1) 全局偏移（在每个子 ADC 中的无偏移参考比较器和本地参考比较器之间）和 2) 本地偏移（在本地参考比较器和其余部分之间）同一子ADC中的比较器）。建议的校准充分抑制了本底噪声和杂散，并且所有校准都在后台执行，不会干扰正常的 ADC 操作。原型 5 路 TI SAR ADC 采用 28 nm CMOS 工艺制造，占地 0.03 mm2，包括片上校准。通过建议的校准，原型在奈奎斯特输入处实现了 40 dB 的 SNDR，消耗了 7.57 mW，从而达到了 Walden 品质因数（ ${\text {FoM}_{W}}$ ) 的 37.2 fJ/转换步。