Polynomial multiplication is the key and time-consuming operation among various operators in Post-Quantum Cryptography (PQC), which aims to find quantum-resistant algorithms to prevent attacks launched by quantum computers. Number Theoretic Transform (NTT) is an efficient algorithm that can accelerate the polynomial multiplication from $\mathcal {O}(n^{2})$ to $\mathcal {O}(nlog(n))$ . In this brief, we present a pipelined NTT (PipeNTT) hardware architecture in FPGA to achieve high throughput with fewer hardware resources. The dataflow and the butterfly unit are optimized to minimize the latency. To fulfil the proposed dataflow, a Block RAM (BRAM) based reordering unit is designed to further reduce the hardware resource. Moreover, our architecture can also be applied to Inverse-NTT (INTT). Compared to state-of-the-art parallel designs, our design achieves a 30% lower area-time product with 3x less memory space requirement.

中文翻译：

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PipeNTT：流水线数论转换架构

多项式乘法是后量子密码学（PQC）中各种算子之间关键且耗时的运算，旨在寻找抗量子算法以防止量子计算机发起的攻击。数论变换 (NTT) 是一种有效的算法，可以从 $\mathcal {O}(n^{2})$至 $\mathcal {O}(nlog(n))$ . 在本简报中，我们介绍了 FPGA 中的流水线 NTT (PipeNTT) 硬件架构，以更少的硬件资源实现高吞吐量。数据流和蝶形单元经过优化以最小化延迟。为了实现所提出的数据流，设计了一个基于块 RAM (BRAM) 的重新排序单元以进一步减少硬件资源。此外，我们的架构也可以应用于 Inverse-NTT (INTT)。与最先进的并行设计相比，我们的设计实现了面积时间减少 30% 的产品，内存空间需求减少了 3 倍。