In this paper, the ruggedness performance of GaN HEMT and SiC JFET devices in cascode configuration with a low voltage silicon power MOSFET has been evaluated experimentally. The impact of the bus voltage on the drain current and avalanche energy are investigated as well as the temperature sweep to enable analysis of the alternation of these parameters on the Unclamped Inductive Switching (UIS) ruggedness of cascode devices. The experimental measurements show that the GaN cascode devices have lower avalanche energy rating when compared with the closely rated SiC cascode devices just before the failure. SiC cascode devices can also withstand higher bus voltage in comparison to GaN cascode devices when under electrothermal stress by unclamped inductive switching. The analysis of transfer characteristics and leakage current of SiC JFET & GaN HEMT cascode structures following UIS stress have also been performed together with Computed Tomography (CT) Scan imaging to determine the per-area avalanche energy density.

在本文中，对具有低压硅功率 MOSFET 的共源共栅配置中 GaN HEMT 和 SiC JFET 器件的耐用性性能进行了实验评估。研究了总线电压对漏极电流和雪崩能量的影响以及温度扫描，以分析这些参数的交替对级联器件的非钳位感应开关 (UIS) 耐用性的影响。实验测量表明，GaN 共源共栅器件与故障前的额定值接近的 SiC 共源共栅器件相比具有较低的雪崩能量额定值。与 GaN 共源共栅器件相比，SiC 共源共栅器件在非钳位感应开关的电热应力下也能承受更高的总线电压。SiC JFET的传输特性和漏电流分析&