Flexibility on the gate-to-drain/source overlap length is useful for selecting the best compromise between device performance (including short channel effects and gate scaling, ON-state current, parasitic overlap capacitance), and the device reliability to hot-carrier degradation. In this paper, the performance and reliability of transistors with variable overlap is studied in a 40 nm CMOS technology. A double-hump is observed in the substrate current characteristic in function of the gate voltage for low-overlap transistors. An analysis of the origin of the second substrate current hump is conducted, and it is attributed to impact ionization at the drain-side, source-side or both depending on the overlap. TCAD simulations are performed to explain the two possible origins of the double-hump characteristic, which are degradation of the gate control over the channel due to low overlap or hot-carrier trapping. Finally, electrical characterizations are conducted to measure the degradation rate for various overlap lengths. It is observed that a longer overlap gives the transistor a longer lifetime under hot-carrier stress conditions.

栅极到漏极/源极重叠长度的灵活性有助于选择器件性能（包括短沟道效应和栅极缩放、导通状态电流、寄生重叠电容）和器件对热载流子退化的可靠性之间的最佳折衷. 在本文中，研究了在 40 nm CMOS 技术中具有可变重叠的晶体管的性能和可靠性。在低重叠晶体管的栅极电压函数中，在衬底电流特性中观察到双峰。对第二个衬底电流峰的起源进行了分析，它归因于漏极侧、源极侧或两者的碰撞电离，具体取决于重叠。执行 TCAD 模拟以解释双峰特征的两个可能来源，这是由于低重叠或热载流子俘获导致的对沟道的栅极控制的退化。最后，进行电气表征以测量各种重叠长度的退化率。据观察，较长的重叠使晶体管在热载流子应力条件下的寿命更长。