High-speed PLL is highly demanding with the advancement in the VLSI market. PLL performance gets affected due to bandwidth limitation. This paper presents third-order configurable transconductance capacitance ($G_m$-$C$)-based loop filter for high-speed PLL. Operational transconductance amplifier (OTA) serves as a basic cell of the $G_m$-$C$ filter. Quasi-floating gate (QFG) and Bulk-driven qausi-floating gate (BD-QFG) MOS-based differential input folded cascode (FC) OTAs are proposed for low-voltage operation. Here, DC gain of the BD-QFG FC OTA enhanced 5.18% than QFG FC OTA. The proposed OTAs enhanced DC gain, CMRR, UGB and FOM along with reduction in the power consumption in comparison to the state-of-art work. Further, third-order $G_m$-$C$ filters are designed using both QFG and BD-QFG MOS-based OTAs and achieved $-$3$$dB cut-off frequency of 16.51$$MHz and 17.22$$MHz, respectively. The proposed QFG and BD-QFG MOS-based filters achieved 22.42% and 21.53% reduction in power than the reported result, respectively. The locking time of integer-N PLL is calculated as 0.33$$$\mu$s and 0.32$$$\mu$s, respectively, through an analytical approach. The transistor-level simulation has been done in 0.18$$$\mu$m CMOS process.

随着 VLSI 市场的进步，高速 PLL 的要求越来越高。由于带宽限制，PLL 性能受到影响。本文介绍了三阶可配置跨导电容（$G_{米}$-$C$) 基于环路滤波器的高速 PLL。运算跨导放大器 (OTA) 作为基本单元$G_{米}$-$C$筛选。准浮栅 (QFG) 和批量驱动的准浮栅 (BD-QFG) 基于 MOS 的差分输入折叠共源共栅 (FC) OTA 被提议用于低电压操作。在这里，BD-QFG FC OTA 的直流增益比 QFG FC OTA 提高了 5.18%。与最先进的工作相比，拟议的 OTA 增强了 DC 增益、CMRR、UGB 和 FOM，同时降低了功耗。进一步，三阶$G_{米}$-$C$滤波器是使用基于 QFG 和 BD-QFG MOS 的 OTA 设计的，并实现了$-$3个$$dB 截止频率 16.51$$兆赫和 17.22$$兆赫兹，分别。所提出的基于 QFG 和 BD-QFG MOS 的滤波器分别比报告的结果降低了 22.42% 和 21.53% 的功率。整数N PLL的锁定时间计算为0.33$$$\mu$和 0.32$$$\mu$s，分别通过分析方法。0.18已经完成晶体管级仿真$$$\mu$m CMOS 工艺。