Practical microwave design is most often carried out in the nominal sense. Yet, in some cases, performance degradation due to uncertainties may lead to the system failing to meet the prescribed specifications. Reliable uncertainty quantification (UQ) is, therefore, important yet intricate from numerical standpoint, especially when the circuit at hand is to be evaluated using electromagnetic (EM) simulation tools. Tolerance-aware design (e.g., yield improvement) is even more challenging. This article introduces a methodology for low-cost surrogate-based yield optimization of passive microwave components. The novelty of the proposed approach, and, at the same time, its major acceleration factor is to span the metamodel domain with the selected principal vectors, characterized by significant response variability within operating frequency bands of the component under design. This results in a volumewise constriction of the domain (thereby lower cost of the surrogate model setup) without restricting its size along the relevant directions of the parameter space. Consequently, our technique is a one-shot approach for yield optimization that does not require neither domain relocation nor surrogate reconstruction. Our methodology is demonstrated using two microstrip components and favorably compared to benchmark metamodeling techniques in terms of the computational cost of the yield maximization procedure. The average cost is only 130 EM simulations of the respective circuit, versus the average of 800 and over 360 analyses for the benchmark procedures. At the same time, its reliability is verified by means of EM-based Monte Carlo simulation.

中文翻译：

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基于主方向和域限制元模型的微波电路容差优化

实际的微波设计最常在名义意义上进行。然而，在某些情况下，由于不确定性导致的性能下降可能会导致系统无法满足规定的规格。因此，从数值的角度来看，可靠的不确定性量化 (UQ) 既重要又复杂，尤其是在使用电磁 (EM) 仿真工具评估手头电路时。公差感知设计（例如，提高良率）甚至更具挑战性。本文介绍了一种基于替代物的低成本无源微波元件良率优化方法。所提出方法的新颖性，同时，它的主要加速因素是用选定的主向量跨越元模型域，特征是在设计的组件的工作频带内有显着的响应变化。这导致域的体积收缩（从而降低了代理模型设置的成本），而不限制其沿参数空间的相关方向的大小。因此，我们的技术是一种用于产量优化的一次性方法，既不需要域重定位也不需要替代重建。我们的方法使用两个微带组件进行了演示，并在产量最大化过程的计算成本方面与基准元建模技术进行了比较。相应电路的平均成本仅为 130 次 EM 仿真，而基准程序的平均成本为 800 次和超过 360 次分析。同时，