This paper proposed a hardware architecture of a strong block-cipher system dedicated to digital image encryption and decryption. On the one hand, a pseudorandom number generator (PRNG) based on two 3D chaotic systems is created to produce strong keys. On the other hand, a robust algorithm is proposed to ensure high-level security and low computational complexity of image encryption. The algorithm performs image encryption mainly through three processes: pixel values hiding by applying the XOR operation with a key, pixel positions hiding by operating random permutation, and pixel substitution using the S-box method. To increase the complexity, R rounds of encryption could be accomplished in a loop. Then as a final step, using the Xilinx Vivado/system generator tool, the hardware cryptosystem is developed, implemented, and evaluated on an FPGA-Zynq evaluation board. According to the synthesis results, the suggested hardware system performs on a reduced FPGA area and gives a good frequency of 156.813 MHz with a high throughput of 20,072.064 Mbps. Several tools and tests utilizing various images are used to evaluate and analyze the hardware cryptosystem. The experimental results show that the hardware implementation has higher performance compared to other recent works.

中文翻译：

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基于强伪随机数发生器的彩色图像加解密分组密码系统的硬件实现

本文提出了一种专用于数字图像加解密的强分组密码系统的硬件架构。一方面，创建了基于两个 3D 混沌系统的伪随机数生成器 (PRNG) 来生成强密钥。另一方面，提出了一种鲁棒算法来保证图像加密的高安全性和低计算复杂度。该算法主要通过三个过程进行图像加密：通过与密钥进行异或运算隐藏像素值，通过随机排列隐藏像素位置，以及使用S-box方法进行像素替换。为了增加复杂性，可以在循环中完成 R 轮加密。然后作为最后一步，使用 Xilinx Vivado/系统生成器工具，开发、实施硬件密码系统​​，并在 FPGA-Zynq 评估板上进行评估。根据综合结果，建议的硬件系统在减少的 FPGA 面积上运行，并提供 156.813 MHz 的良好频率和 20,072.064 Mbps 的高吞吐量。使用各种图像的几种工具和测试用于评估和分析硬件密码系统​​。实验结果表明，与其他近期作品相比，硬件实现具有更高的性能。