Addition is a ubiquitous operation frequently carried out in most computing applications. Traditionally, three-operand addition is done using either two adders or a carry–save adder. However, there exist applications such as digital signal processing, image processing, floating point arithmetic, etc. wherein among the three operands, one is constant. For such cases, we propose a flagged constant addition methodology, applicable to any constant, to compute the result with the least area, delay and power. The resulting architecture is referred to as general constant flagged adder (GCFA). We propose an Optimized Constant Generation (OCG) algorithm and a Hardware Optimization Algorithm (HOA) to achieve hardware-efficient constant flagged adder. These two algorithms are designed to lower the computational complexity. The OCG algorithm accepts the constant to be added and converts it into an optimized constant. This optimized constant then forms the input to the HOA where the hardware modifications are performed. Unlike the proposed work, the existing flagged adder structures do not provide a general methodology to obtain the optimized constant and hardware for all the constants, resulting from the presence of architectural customization for all constants and word lengths. Exhaustive hardware analyses have been carried out to prove the efficacy of the proposed architecture against the existing designs. Structural Verilog code is synthesized for each to obtain the area, delay and power. Synthesis results show up to 35.85% and 49.24% reductions in area–delay and power–delay products, respectively. The improved speed and lower hardware requirements make the proposed methodology a suitable choice for constant addition.

加法是大多数计算应用程序中经常执行的无处不在的操作。传统上，三操作数加法是使用两个加法器或一个进位保存加法器完成的。然而，存在数字信号处理、图像处理、浮点运算等应用，其中三个操作数中，一个是常数。对于这种情况，我们提出了一种标记的常量加法方法，适用于任何常量，以最小的面积、延迟和功率计算结果。生成的架构称为通用常量标记加法器 (GCFA)。我们提出了优化常量生成 (OCG) 算法和硬件优化算法 (HOA) 来实现硬件高效的常量标记加法器。这两种算法旨在降低计算复杂度。OCG 算法接受要添加的常量并将其转换为优化后的常量。这个优化的常量然后形成对执行硬件修改的 HOA 的输入。与提议的工作不同，现有的标记加法器结构不提供通用方法来获得所有常量的优化常量和硬件，这是由于所有常量和字长的体系结构定制的存在。已经进行了详尽的硬件分析，以证明所提出的体系结构相对于现有设计的有效性。结构Verilog代码被综合为每一个以获得面积、延迟和功率。综合结果显示，面积延迟和功率延迟产物分别减少了 35.85% 和 49.24%。