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One-sided 10T static-random access memory cell for energy-efficient and noise-immune internet of things applications
International Journal of Circuit Theory and Applications ( IF 2.3 ) Pub Date : 2022-08-18 , DOI: 10.1002/cta.3408
Abdolreza Darabi 1 , Mohammad Reza Salehi 1 , Ebrahim Abiri 1
Affiliation  

This paper presents a one-sided 10-transistors static-random access memory (SRAM) cell appropriate for the internet of things (IoT) applications in which energy-efficient SRAM cells are necessary to raise the battery lifetime. The bit-cell core of the proposed SRAM cell is composed of two inverters with different structures based on the gate-wrap-around (GWA) carbon nanotube (CNT)-gate-diffusion input (GDI) technique and only one-bit line to perform both read and write operations to minimize active power consumption. The proposed bit-cell uses a transmission gate network and write-assist schemes to significantly improve the write-ability and stack read-decoupling technique to enhance hold-/read-stability. Moreover, a memory mini-array has been implemented using the proposed cell along with all the principal circuitries. Extensive Monte Carlo (MC) simulations show that write/hold/read static noise margins (SNMs) are improved by about 1.252, 1.196, and 1.152 times, respectively. Also, the results of evaluating the write- and read-yield parameters for the proposed SRAM bit-cell are about 22% and 13% better than counterpart bit-cell designs, respectively. In addition, the bit error rate (BER) and energy dissipation parameters for the proposed memory cell are almost 61% and seven times higher than the studied SRAM bit-cell in the same simulation process. Finally, to evaluate the effectiveness of the proposed SRAM bit-cell in the real-world application, a memory array architecture with an online (or off-chip) adaptive power supply voltage based on a hardware algorithm for storing digital images at a minimum energy dissipation is proposed. Our simulation results emphasize that the proposed memory array can be a good candidate for energy-efficient and noise-immunity IoT platforms.

中文翻译:

单面 10T 静态随机存取存储单元,用于节能和抗噪声的物联网应用

本文介绍了一种适用于物联网 (IoT) 应用的单侧 10 晶体管静态随机存取存储器 (SRAM) 单元,在这些应用中,节能 SRAM 单元对于延长电池寿命是必不可少的。所提出的 SRAM 单元的位单元核心由两个具有不同结构的反相器组成,这些反相器基于栅极环绕 (GWA) 碳纳米管 (CNT)-栅极扩散输入 (GDI) 技术和仅一位线到执行读取和写入操作,以最大限度地减少活动功耗。所提出的位单元使用传输门网络和写入辅助方案来显着提高写入能力和堆栈读取解耦技术以增强保持/读取稳定性。此外,已经使用所提出的单元以及所有主要电路实现了存储器微型阵列。广泛的蒙特卡洛 (MC) 模拟表明写入/保持/读取静态噪声容限 (SNM) 分别提高了约 1.252、1.196 和 1.152 倍。此外,评估建议的 SRAM 位单元的写入和读取良率参数的结果分别比对应的位单元设计好 22% 和 13%。此外,在相同的仿真过程中,所提出的存储单元的误码率 (BER) 和能量耗散参数比所研究的 SRAM 位单元高出近 61% 和七倍。最后,为了评估所提出的 SRAM 位单元在实际应用中的有效性,基于硬件算法的在线(或片外)自适应电源电压的存储器阵列架构用于以最小能量存储数字图像建议耗散。
更新日期:2022-08-18
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